JPS62106643U - - Google Patents

Info

Publication number
JPS62106643U
JPS62106643U JP19853485U JP19853485U JPS62106643U JP S62106643 U JPS62106643 U JP S62106643U JP 19853485 U JP19853485 U JP 19853485U JP 19853485 U JP19853485 U JP 19853485U JP S62106643 U JPS62106643 U JP S62106643U
Authority
JP
Japan
Prior art keywords
thyristor
state
electrostatic precipitator
stop time
intermittent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19853485U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19853485U priority Critical patent/JPS62106643U/ja
Publication of JPS62106643U publication Critical patent/JPS62106643U/ja
Pending legal-status Critical Current

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  • Electrostatic Separation (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A〜Hは、本考案に係る制御ブロツク図
および各部の出力波形図、第2図A〜Cは、本考
案の一実施例を示す図および出力波形図、第3図
A〜Hは、従来の制御ブロツク図および各部の出
力波形図、第4図A〜Cは、その具体例を示す図
である。 1′……サイリスタ制御回路、2……サイリス
タ、8′……電源同期回路、8―1……ゼロクロ
ス検出回路、8―2……波形整形回路、8―3′
……パルスカウンタ、8―4……設定回路、9―
1……パルストランス回路、9―2……移相器。
Figures 1A to 1H are a control block diagram and output waveform diagrams of various parts according to the present invention, Figures 2A to C are diagrams and output waveform diagrams showing an embodiment of the present invention, and Figures 3A to H 4 is a conventional control block diagram and output waveform diagrams of various parts, and FIGS. 4A to 4C are diagrams showing specific examples thereof. 1'...Thyristor control circuit, 2...Thyristor, 8'...Power synchronization circuit, 8-1...Zero cross detection circuit, 8-2...Waveform shaping circuit, 8-3'
...Pulse counter, 8-4...Setting circuit, 9-
1... Pulse transformer circuit, 9-2... Phase shifter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] サイリスタ制御回路を有する電気集じん器の間
欠荷電装置において、サイリスタ制御回路から出
力される出力信号とパルスカウンタから出力され
る出力信号とにより、荷電時間(サイリスタON
状態)のときにサイリスタを制御し、荷電停止時
間(サイリスタOFF状態)のときにサイリスタ
の制御を無効にする手段を具備してなることを特
徴とする電気集じん器の間欠荷電装置。
In an intermittent charging device for an electrostatic precipitator having a thyristor control circuit, the charging time (thyristor ON
1. An intermittent charging device for an electrostatic precipitator, comprising means for controlling a thyristor during charging stop time (thyristor OFF state) and disabling control of the thyristor during charging stop time (thyristor OFF state).
JP19853485U 1985-12-24 1985-12-24 Pending JPS62106643U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19853485U JPS62106643U (en) 1985-12-24 1985-12-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19853485U JPS62106643U (en) 1985-12-24 1985-12-24

Publications (1)

Publication Number Publication Date
JPS62106643U true JPS62106643U (en) 1987-07-08

Family

ID=31159309

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19853485U Pending JPS62106643U (en) 1985-12-24 1985-12-24

Country Status (1)

Country Link
JP (1) JPS62106643U (en)

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