JPS62104211A - Line equalization system - Google Patents

Abstract

PURPOSE:To attain the equalization of a large distortion by placing a digital filter before an automatic equalizer of a MODEM and changing stepwise the tap coefficient of an automatic equalizer and the characteristic of the digital filter from the locking state. CONSTITUTION:The digital filter 10 is provided before the automatic equalizer 9, the pattern I compensates a characteristic (a), the pattern II compensates a characteristic (b), the pattern III compensates a characteristic (c) and the pattern IV compensates a characteristic (d) respectively. A processor 15 reads a rap coefficient of a desired characteristic pattern from a memory 16, sets it to a tap coefficient 14, the digital signal inputted to a buffer 11 and the value of the tap coefficient 14 are multiplied by a computing element 12, an adder 13 makes total sum and the result is outputted to the automatic equalizer 9. Then a training signal is sent to change over the characteristic of the digital filter 10 sequentially as a b c d, the tap coefficient of the automatic equalizer 9 is checked corresponding to each characteristic and the digital filter 10 is set to the characteristic state taking the optimum tap coefficient.

Description

[Detailed Description of the Invention] [Summary] A digital filter is placed in front of the automatic equalizer of the modem,
It is possible to equalize large distortions by changing the characteristics of the digital filter in steps based on the amount of tap coefficients of the automatic equalizer and the synchronization pull-in state.

[Industrial application field]

The present invention relates to a line equalization method in data transmission.

Conventional line equalization methods have problems in that the equalization work performed when switching lines is time-consuming and that the range that can be automatically equalized by the training method is limited, so improvements in this area have been strongly desired.

[Conventional technology]

FIG. 4 is a diagram showing an example of a line equalization method in conventional data transmission.

In FIG. 4, l is an encoder, 2 is a modulator, 3 is a transmission filter, 4 is a reception filter, 5 is a demodulator, 6 is an A/D converter, 7 is an equalizer, 7a is fixed, etc. 7b is an automatic equalizer, 7C is a manual equalizer, and 8 is a decoder. The same symbols represent the same objects throughout all the figures below.

In conventional data transmission using an analog line, as shown in Figure 4, on the transmitting side, the transmitted data is encoded by an encoder 1, which is D/A converted by a modulator 2, and then modulated into a predetermined format. , and is sent out to the line via the transmission filter 3.

On the other hand, on the receiving side, the received signal from the line is received, and after passing through a fixed equalizer 7a or a manual equalizer 7c, a receiving filter 4
extracts only the necessary frequency components, demodulates them with a demodulator 5, converts them into digital format signals with an A/D converter 6, inputs them to an automatic equalizer 7b, and corrects line distortion again. A method was adopted in which the decoder 8 restored the data to the original (number i).

[Problem that the invention seeks to solve]

However, in the above-mentioned conventional system, when switching lines for use, the following method is adopted.

One of them is to configure the equalizer 7 with two equalizers, one of which is an automatic equalizer 7b and the other one is a fixed equalizer 7a,
The automatic equalizer 7b has a function of performing automatic equalization within a limited range, and the fixed equalizer 7a has a plurality of equalizers prepared for each line to be switched. select converter 7a and perform panel replacement.

Another one is to configure the equalizer 7 with two equalizers, one of which is an automatic equalizer 7b and the other one is a manual equalizer 7c, and when switching lines, the manual equalizer 7c is The values of the component coils and capacitors are manually adjusted each time.

In this case, the adjustment work is time consuming and therefore time consuming.

Either method has the problem that it takes a long time to communicate the data.

Further, even if automatic equalization is performed using the training method, the equalization range is limited to a certain limit, and there is also the problem that automatic equalization becomes impossible when line distortion exceeds a certain limit.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the above-mentioned conventional methods and to provide a line equalization method that is easier to perform and has a wider equalization range.

[Means for solving problems]

The above problem occurs when a modem that transmits data using an analog line uses a digital filter 10 constructed by another digital processor in front of the automatic equalizer 9 for line equalization, as shown in FIG. This problem can be solved by preparing a plurality of patterns for the digital filter 10 and switching the patterns of the digital filter 10 depending on the tap coefficients of the automatic equalizer 9 and the synchronous pull-in state.

[Effect]

According to the present invention, multiple types of patterns are prepared in advance in the digital filter, and the automatic equalizer is maintained in the optimum equalization state by automatically switching among these patterns in sequence, so even if the line condition changes. This method has the advantage that the automatic equalizer can be set to the optimum state more accurately and in a shorter time than the conventional method.

〔Example〕

FIG. 1 is an explanatory diagram of the line equalization method according to the present invention, as described above.

FIG. 2(al) is a diagram showing an embodiment of the digital filter according to the present invention, and FIG. 2(b) is a diagram illustrating a pattern of line characteristics.

FIG. 3 is a diagram illustrating the operation sequence of FIG. 2.

In the figure, 9 is an automatic equalizer, 10 is a digital filter, 11 is a buffer (Xi'), 12 is an arithmetic unit, 1
3 is an adder, 14 is a tap coefficient (Ci), 15 is a processor, and 16 is a memory.

In the present invention, a digital filter 1 configured by a digital signal processor is installed before the automatic equalizer 9 on the receiving side.
0 is set, and the characteristics of the digital filter IO are changed stepwise from the tap coefficient amount of the automatic equalizer 9, thereby making it possible to equalize larger distortions without changing the characteristics of the automatic equalizer 9.

As mentioned above, when automatic equalization is performed by the automatic equalizer 9 using the training method, the equalization range is limited to a certain limit, and if the limit is exceeded, the automatic equalizer 9 loses its equalization function. However, line characteristics are originally classified into several types of patterns depending on the line length and other factors.

For example, if the line length is short as shown in Figure 2 (bl),
It has the characteristics shown in , and as the line length increases, the characteristic b
, characteristic C1 changes to characteristic d.

Therefore, a digital filter 10 is provided before the automatic equalizer 9, and several types of patterns I to ■ are prepared in advance in this digital filter 10. Pattern I has the characteristic a, pattern ■ has the characteristic, and pattern ■ is characteristic C, pattern ■
are designed to compensate for the characteristic d, respectively.

The digital filter 10 is composed of a processor 15 (digital signal processor) as shown in FIG. The data is read out from the processor 15 as appropriate. It is effective to use a ROM, for example, as the memory 16, since the stored contents will not be lost even if the device power is turned off.

The processor 15 reads out the tap coefficient value of the desired characteristic pattern from the memory 16 and sets it in the tap coefficient 14.
An arithmetic unit 12 multiplies the digital signal input to the frequency sofa 11 and the value of a tap coefficient 14, and an adder 13 calculates the sum and outputs the sum to an automatic equalizer 9.

In the above state, the training signal is sent out, and the characteristics adopted by the digital filter 10 are sequentially determined at time intervals sufficiently long to allow the automatic equalizer 9 to perform the automatic equalization operation. -+d, examine the tap coefficients taken by the automatic equalizer 9 corresponding to each characteristic, and set the digital filter 10 to the characteristic state that takes the most optimal tap coefficient.
By setting , the automatic equalizer 9 can be made to function satisfactorily from now on.

The operation sequence of the present invention will be explained below with reference to FIG.

First, the processor 15 reads the tap coefficient of pattern I from the memory 16 and sets it to coefficient 14.

Next, start the modem pull-in operation■.

In this state, the synchronous circuit (not shown) checks to see if it is out of synchronization (■).

If the synchronization circuit issues an out-of-synchronization signal, the processor 15 reads the tap coefficient of pattern (2) from the memory 16, sets it to coefficient (14), and starts the modem pull-in operation (2) again.

If synchronization is established, the processor 15 reads from the automatic equalizer 9 each tap coefficient value that the automatic equalizer 9 is taking at the time, and determines the constant value of which the sum of the respective tap coefficient values consists. ■ Check whether it is smaller than the value MR.

If the total value of each tap coefficient value is smaller than the constant value MR, it is determined that the equalization state of the automatic equalizer 9 is good, so the digital filter 10 is fixed to the state of pattern H. ■.

If the total value of each tap coefficient value is not smaller than the constant value MR, it is determined that the equalization state of the automatic equalizer 9 is not optimal, and the characteristic pattern of the digital filter 10 is transferred to the next one. That is, the processor 15 reads the tap coefficient of pattern (2) from the memory, sets it to coefficient (14), and starts the modem pull-in operation (2) again.

As the digital filter 10 repeats such operations, the automatic equalizer 9 can operate accurately in an optimal state.

Note that the error rate deteriorates as the total value of each tap coefficient value taken by the automatic equalizer 9 increases, so a constant value MR is set in advance in consideration of an allowable error rate.

〔Effect of the invention〕

As described above in detail, the present invention has the great effect of automatically setting the automatic equalizer to the optimum state in a short period of time even if the line condition changes.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a line equalization method according to the present invention. FIG. 2 (al is a diagram showing an embodiment of the digital filter according to the present invention. FIG. 2(b) is a diagram illustrating a pattern of line characteristics. FIG. 3 is a diagram showing the operation sequence of FIG. 2. FIG. 4 is a diagram illustrating an example of a line equalization method in conventional data transmission. In the figure, l is an encoder, 2 is a modulator, 3 is a transmission filter, 4 is a reception filter, 5 is a demodulator, 6 is an A/D converter, 7 is an equalizer, 7a is a fixed equalizer, 7b is an automatic equalizer,
7c is a manual equalizer, 8 is a decoder, 9 is an automatic equalizer, 10
is a digital filter, 11 is a buffer (Xi),
12 is an arithmetic unit, 13 is an adder, and 14 is a tap coefficient (C4
), 15 is a processor, and 16 is a memory. 4＼Pharyngeal 1'-, f3 hard mego lL=ji style noe d month hanging mouth tea 1 eye 4〈rikI 3 month (-Jru tenshirashireji 4/shi7 one point 1,74 guku group) ≧ 2 Figure and a)

Claims (1)

[Claims] In a modem that transmits data using an analog line, a digital filter (10) configured by another digital processor is installed before an automatic equalizer (9) for line equalization.
), a plurality of types of patterns are prepared for the digital filter (10), and the pattern of the digital filter (10) is switched depending on the tap coefficient of the automatic equalizer (9) and the synchronous pull-in state. Characteristic line equalization method.