JPS6195106U - - Google Patents
Info
- Publication number
- JPS6195106U JPS6195106U JP17979884U JP17979884U JPS6195106U JP S6195106 U JPS6195106 U JP S6195106U JP 17979884 U JP17979884 U JP 17979884U JP 17979884 U JP17979884 U JP 17979884U JP S6195106 U JPS6195106 U JP S6195106U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- amplifier
- voltage dividing
- taken out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
第1図はこの考案の増幅回路の実施例を示す回
路図、第2図はその変形例を示す回路図、第3図
はこの考案の増幅回路の他の実施例を示す回路図
、第4図は従来の増幅回路を示す回路図である。
20……増幅器、26……帰還回路、28……
分圧回路。
Fig. 1 is a circuit diagram showing an embodiment of the amplifier circuit of this invention, Fig. 2 is a circuit diagram showing a modification thereof, Fig. 3 is a circuit diagram showing another embodiment of the amplifier circuit of this invention, and Fig. 4 is a circuit diagram showing an embodiment of the amplifier circuit of this invention. The figure is a circuit diagram showing a conventional amplifier circuit. 20...Amplifier, 26...Feedback circuit, 28...
Voltage divider circuit.
Claims (1)
に、その帰還量を設定した分圧点を含む2以上の
分圧点を持つ分圧回路を設置し、前記増幅器の出
力を第1の出力として取り出すとともに、前記分
圧回路の分圧点から利得の異なる1または2以上
の第2の出力を取り出し可能にしたことを特徴と
する増幅回路。 (2) 前記第2の出力は、バツフア回路を介して
取り出すことを特徴とする実用新案登録請求の範
囲第1項に記載の増幅回路。[Claims for Utility Model Registration] (1) In a feedback circuit that divides and feeds back the output of an amplifier, a voltage divider circuit having two or more voltage dividing points including the voltage dividing point at which the feedback amount is set is installed, An amplifier circuit characterized in that the output of the amplifier is taken out as a first output, and one or more second outputs having different gains can be taken out from a voltage dividing point of the voltage dividing circuit. (2) The amplifier circuit according to claim 1, wherein the second output is extracted through a buffer circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17979884U JPS6195106U (en) | 1984-11-27 | 1984-11-27 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17979884U JPS6195106U (en) | 1984-11-27 | 1984-11-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6195106U true JPS6195106U (en) | 1986-06-19 |
Family
ID=30737363
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17979884U Pending JPS6195106U (en) | 1984-11-27 | 1984-11-27 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6195106U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53142856A (en) * | 1977-05-19 | 1978-12-12 | Toshiba Corp | Comparator |
-
1984
- 1984-11-27 JP JP17979884U patent/JPS6195106U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53142856A (en) * | 1977-05-19 | 1978-12-12 | Toshiba Corp | Comparator |
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