JPS6193694U - - Google Patents
Info
- Publication number
- JPS6193694U JPS6193694U JP17959184U JP17959184U JPS6193694U JP S6193694 U JPS6193694 U JP S6193694U JP 17959184 U JP17959184 U JP 17959184U JP 17959184 U JP17959184 U JP 17959184U JP S6193694 U JPS6193694 U JP S6193694U
- Authority
- JP
- Japan
- Prior art keywords
- frame
- working machine
- engine working
- frame body
- machine according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Workshop Equipment, Work Benches, Supports, Or Storage Means (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984179591U JPH0115997Y2 (https=) | 1984-11-27 | 1984-11-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984179591U JPH0115997Y2 (https=) | 1984-11-27 | 1984-11-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6193694U true JPS6193694U (https=) | 1986-06-17 |
| JPH0115997Y2 JPH0115997Y2 (https=) | 1989-05-11 |
Family
ID=30737156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984179591U Expired JPH0115997Y2 (https=) | 1984-11-27 | 1984-11-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0115997Y2 (https=) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9423824B2 (en) | 2011-10-03 | 2016-08-23 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
| US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
| US9496243B2 (en) | 2011-10-03 | 2016-11-15 | Invensas Corporation | Microelectronic assembly with opposing microelectronic packages each having terminals with signal assignments that mirror each other with respect to a central axis |
| US9515053B2 (en) | 2011-10-03 | 2016-12-06 | Invensas Corporation | Microelectronic packaging without wirebonds to package substrate having terminals with signal assignments that mirror each other with respect to a central axis |
| US9530458B2 (en) | 2011-10-03 | 2016-12-27 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745255U (https=) * | 1980-08-25 | 1982-03-12 |
-
1984
- 1984-11-27 JP JP1984179591U patent/JPH0115997Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745255U (https=) * | 1980-08-25 | 1982-03-12 |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9423824B2 (en) | 2011-10-03 | 2016-08-23 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
| US9496243B2 (en) | 2011-10-03 | 2016-11-15 | Invensas Corporation | Microelectronic assembly with opposing microelectronic packages each having terminals with signal assignments that mirror each other with respect to a central axis |
| US9515053B2 (en) | 2011-10-03 | 2016-12-06 | Invensas Corporation | Microelectronic packaging without wirebonds to package substrate having terminals with signal assignments that mirror each other with respect to a central axis |
| US9530458B2 (en) | 2011-10-03 | 2016-12-27 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals |
| US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0115997Y2 (https=) | 1989-05-11 |