JPS6193025U - - Google Patents

Info

Publication number
JPS6193025U
JPS6193025U JP17670384U JP17670384U JPS6193025U JP S6193025 U JPS6193025 U JP S6193025U JP 17670384 U JP17670384 U JP 17670384U JP 17670384 U JP17670384 U JP 17670384U JP S6193025 U JPS6193025 U JP S6193025U
Authority
JP
Japan
Prior art keywords
circuit
receiver
pll
voltage controlled
phase comparison
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17670384U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17670384U priority Critical patent/JPS6193025U/ja
Publication of JPS6193025U publication Critical patent/JPS6193025U/ja
Pending legal-status Critical Current

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Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Superheterodyne Receivers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図は、本考案の実施例の構成と動作を示すブロ
ツク図である。 1…混合回路、2…IF増幅回路、3…周波数
弁別回路、5…分周回路、6…切換回路、7…位
相比較回路、8…基準周波数発振回路、9…加算
回路、10…メモリ、4…電圧制御発振回路。
The figure is a block diagram showing the configuration and operation of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Mixing circuit, 2... IF amplifier circuit, 3... Frequency discrimination circuit, 5... Frequency division circuit, 6... Switching circuit, 7... Phase comparison circuit, 8... Reference frequency oscillation circuit, 9... Adding circuit, 10... Memory, 4...Voltage controlled oscillation circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 混合回路とIF増幅回路と周波数弁別回路より
なる受信回路と、電圧制御発振回路と位相比較回
路と基準周波数発生回路よりなるPLL受信回路
にメモリ回路と切換回路を設けた事を特徴とする
PLL受信回路。
A PLL receiver characterized in that a receiver circuit consisting of a mixing circuit, an IF amplifier circuit, and a frequency discrimination circuit, a PLL receiver circuit consisting of a voltage controlled oscillation circuit, a phase comparison circuit, and a reference frequency generation circuit are provided with a memory circuit and a switching circuit. circuit.
JP17670384U 1984-11-22 1984-11-22 Pending JPS6193025U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17670384U JPS6193025U (en) 1984-11-22 1984-11-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17670384U JPS6193025U (en) 1984-11-22 1984-11-22

Publications (1)

Publication Number Publication Date
JPS6193025U true JPS6193025U (en) 1986-06-16

Family

ID=30734296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17670384U Pending JPS6193025U (en) 1984-11-22 1984-11-22

Country Status (1)

Country Link
JP (1) JPS6193025U (en)

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