JPS619087A - Signal processing circuit of video disc player - Google Patents

Abstract

PURPOSE:To record and reproduce properly both a video signal and a sound signal even when a disc stored partially with an address signal in advance is used by applying time axis compression so that a sound signal is not recorded superimposingly on an address signal area and extracting the signal at reproduction by applying time axis expansion. CONSTITUTION:A sound signal inputted from a terminal D is fed to an AD converter via an LPF32. Further, a video signal is fed to a terminal H and a horizontal synchronizing signal fH is generated from the said video signal by a synchronizing separator circuit 43. An address gate signal is inputted to a memory control circuit 47 to generate a write instruction and a read instruction of memories 35a, 35b. The sound signal digitized by the AD converter 34 is written alternately in the memories 35a, 35b at each 16.7ms. On the other hand, the read from the memories 35a, 35b is controlled so that the sound signal and the address gate signal are not superimposed on time axis.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a signal processing circuit for a video disc player, and particularly to a signal processing circuit in which address signals are stored in advance.
spiral or concentric guide tracks (
The present invention relates to a signal processing circuit for a video disc player that records video signals and audio signals in a superimposed manner on a disc-shaped recording medium (disc) having an information recording track, and reproduces the same.

[Background of the invention]

Traditionally, video disc players mechanically irradiate a disc with a light beam such as a laser in a spiral (; I. spiral) or concentric form to convert information such as video signals into two types such as irregularities or shading. There are devices that record and reproduce value signals at high density.

Recording of a video signal in this device involves FM modulating a carrier signal of an appropriate frequency with the video signal, converting it into a binary signal using a limiter, etc., and based on this, for example, recording pit lengths of long and short. It will be done. Furthermore, reproduction is also performed based on the recording bit length.
1. Conventionally, as methods for processing color signals when recording and reproducing video signals on the disk, there are the direct FM method, the Verirad chroma method, and the low frequency conversion method. The following will explain the low-frequency conversion method as an example.

FIG. 10 is a block diagram showing an example of a conventional video signal recording and reproducing apparatus that optically records and reproduces video signals using a low frequency conversion method.

In the figure, 1 is a Y/C separation filter that separates the luminance signal Y and the force 'y'-M signal C, 2 is a Brien 7 assist circuit, 3 is a clamp circuit, 4 is a clip circuit, and 5 is an FM modulator. , 6 is a mixer, 7 is a power 2-signal processing circuit, and 8 is a limiter. Note that 1 to 8 above constitute a recording video signal processing circuit.

'9 is a light modulator; 10 is a pair of lenses for forming an image of the output light of the light modulator 9 on the disk 11; 12 is a disk motor for rotationally driving the disk 11; 13 is a pre-scanning converter;
4 is a regenerative amplifier. Note that 9 to 14 constitute a device for optically recording on or reproducing a disc.

18 is a high-pass filter, 19 is a limiter circuit, 20 is an FM demodulation circuit, 21 is a de-emphasis circuit, 22 is a mixer, 23 is a low-pass filter, and 24 is a color signal processing circuit. Note that 18 to 241 are the disks 11
It constitutes a playback signal processing circuit for returning the playback information from the video signal back to the original video signal.

25 is a low-pass filter, and 26 is an address reading circuit.

11(,) to (h) are diagrams showing examples of two vectors and signal waveforms of each part of the video signal processing circuit of FIG. 10. It should be noted that portions (a) to (h) in FIG. 10 and the same reference numerals in FIG. 10 correspond to each other.

In FIG. 10, a video signal of NTSC system or the like is applied to the terminal. FIG. 11 (&) shows the spectrum of the video signal, and as described above, Y shows the luminance signal and C shows the color signal.

The video signal (&) is separated into a luminance signal Y (FIG. 11b) and a color signal C (FIG. 11C) by a Y/C separation 7 ilter 1, and the luminance signal Y is sent to a pre-emphasis circuit 2. , FM via clamp circuit 3 and clip circuit 4
The signal is supplied to the modulator 5.

The FM modulator 5 performs FM modulation on a carrier signal of an arbitrary frequency using the input luminance signal Y. The spectrum of the FM modulated signal is shown in FIG. 2(d).

On the other hand, the large power 2-signal C separated by the Y/C separation filter 1 is supplied to the color signal 6 logic circuit 7.

Power 2-signal processing circuit 7 is an ACC circuit and 3.58MH
z force 2 - convert the signal to a low frequency (- for example 629IG (
It consists of a balanced modulator, etc. for converting to As a result, the color signal processing circuit 7 outputs the signal from the color signal processing circuit 7 as shown in FIG.
, ), the color signal C converted to the low frequency
' is output.

Next, the FM modulation signal from the FM modulator 5 and the color signal converted to a low frequency band are mixed in a mixer 6. The spectrum at this time is shown in FIG. 11(f), and the signal waveform is shown in FIG.

In FIG. 11(g), the part (() forming the envelope of the signal waveform is a color signal component subjected to low frequency conversion, and the part (b) is a luminance signal component subjected to FM modulation.

The output signal of the mixer 6 is supplied to a limiter 8 and becomes a binary recording signal. This state is shown in FIG. 11(h).

This upper 9 binary recording signal is supplied to the optical modulator 9 and converted into a light beam having a strength corresponding to the recording signal (h) for recording on the disc 11.

The conversion into the light beam by the optical modulator 9 is performed using the recording signal (h) by, for example, changing the drive current of a semiconductor laser.

As a result, when the disk 110 is rotated by the disk motor 12, the video signal is
.

figure It will be recorded on the disc 11.

Next, a case in which a video signal is reproduced from the disc 11 will be briefly described.

During reproduction, the optical modulator 9 irradiates the disk 11 with a weak light beam of constant intensity through the objective lens 10, and the transmitted light from the disk 11 is supplied to the photoelectric converter 13. Note that in this case, the reflected light from the disk 11 may be supplied to the photoelectric converter 13.

The photoelectric converter 13 generates an electric signal depending on the intensity of the transmitted light, and supplies this to the regenerative amplifier 14.

The output regenerative signal from regenerative amplifier 14 is supplied to bypass filter 18 and low pass filters 23,25.

The bypass filter 18 extracts only the FM-modulated luminance signal component and supplies it to the limiter circuit 19. The limiter circuit 19 shapes the waveform of the luminance signal component and supplies it to the FM demodulation circuit 20 . As a result, the luminance signal component is FM demodulated and output as a luminance signal Y. The de-emphasis circuit 21 corrects the frequency characteristics of the luminance signal Y and outputs it to the mixer 22.

The low-pass filter 23 performs low-pass conversion, extracts only the large power 2-signal component, and supplies this to the power 2-signal processing circuit 24 . Power 2 - In the signal processing circuit 24, the well-known AFC
- Signal processing such as APC is performed, and the power 2 signal component is further converted into a 3.58 MHz color signal C using a balanced modulator or the like, and the signal is supplied to the mixer 22.

Next, in the mixer 22, the luminance signal Y obtained by the FMa14 is
and force 2-signal C to create a playback video signal,
This is output via terminal B.

Furthermore, the output reproduction signal from the regenerative amplifier 14 is also supplied to the low-pass filter 25, as described above. The low-pass filter 25 extracts only the frequency component of the address signal previously recorded on the disk 11 and supplies it to the address reading circuit 26 7, resulting in output from the band signal line terminal C.

FIG. 12 is a partially enlarged perspective view showing a portion of the disk 11 cut away and perspectively shown.

In the same figure, 27a to 27f are guide tracks that are carved, for example, in a spiral shape on the surface of the disk 11 with a width w1 pitch p1 depth d.

Reference numeral 28 denotes a recording surface formed by spraying a recording material such as a photosensitive amorphous metal from the surface side.

Further, 29 indicates a substrate. Although not shown in FIG. 12, the actual disc 11 is provided with a protective layer or the like on the recording surface 28.

Referring to FIG. 12, the output light from the optical modulator 9 of FIG.
Minute spot light 30 for recording from the plate 21 NI+ side
It is irradiated as As a result, on the recording surface 28,
Since the minute spots are connected, the recorded information is transferred to the scissors recording surface 2.
8 as local pitting or in the form of blackening.

FIG. 13( ) is a partially enlarged view of one of the guide tracks 27a to 27f viewed from the top surface of the disk 11. FIG. Moreover, FIG. 13(b) is a cross-sectional view taken along the line AA in FIG. 13(,).

In these figures, the same reference numerals as in FIG. 12 indicate the same or equivalent parts. 100 is a protective layer.

As is clear from FIG. 13(b), the guide tracks 27a to 27f are composed of a prerecorded address signal area 31 and an area 32 where no address signal is recorded.

In the address signal area 31, address information is stored discretely in a bit structure with an optical phase change. In addition, information such as video signals is """"°゛′′In
? 4fi′″″c**−5hb°, 1! Next, the frequency relationship between the address signal and the video signal to be recorded is
This will be explained with reference to Figure 4.

FIG. 14 shows the spectrum of the recording signal and the address signal.

In Figure jI114, Y(FM) is F for recording purposes.
An M-modulated luminance signal is shown, and as an example, the FM modulation frequency of the sync tip level is 511Ez, and the modulation frequency of the white peak level is 6.4kmz.

Further, C' indicates a color signal that has been low frequency converted to 629 KHz.

The address signal is generally 7-Aze encoding modulated (
pm) or modified FM modulation (MFM), and is stored in the address signal area 31 of the guide track 27&~27f of the disk 110, as described above.

The spectrum of this address signal, its fundamental wave component, is set to approximately 275 to 550 KHz.
This state is indicated by the symbol A in FIG. Also, the code AJ
It shows the third harmonic component of the address signal.

As is clear from FIG. 14, when a video signal is recorded in an overlapping manner on the address signal area 31, the shicolor signal is invaded by the address signal. For this reason, the address signal area 31 is set so as to be within the vertical retrace period of the video signal, so that the image 1f of the television receiver does not move.

FIG. 15 is a plan view of the disk 11 clearly showing the address signal areas preset on the disk 11 as described above.

In the figure, a 31 m, 31 bti cost signal area is shown.

Disk 11 is typically rotated at 5K 1800 rpm to record 17 frames of video signal in one revolution.

Therefore, the address signal areas 31m and 31b are provided at two locations facing each other by 180°.

By the way, in the video signal recording and reproducing device as described above,
Due to the following reasons, continuous audio signals and video signals may be
The disadvantage was that it was practically impossible to recycle the brass.

In other words, for example, an audio signal is converted into a low frequency color signal and F.
The gap in the spectrum of the M-modulated luminance signal is approximately 1.5
When a 11Ez carrier signal is FM-modulated, frequency-multiplexed with a video signal, recorded, and played back using a well-known method, the address signal stored in advance on the disk, especially its harmonic components, is It will be clear from the 14th m that the quality of the reproduced audio signal is very poor due to the interference from t5.

[Purpose of the invention]

An object of the present invention is to eliminate the drawbacks of the prior art described above and to provide a signal processing circuit for a video disc player that can record and reproduce not only video signals but also audio signals without quality deterioration. .

[Summary of the invention].

A feature of the present invention is that in a video disc player that records and plays video and audio signals using nine discs in which address signals are stored in advance and arranged in a circular manner, the recording is performed within a period in which the address signals are not output. It has means for time-base compressing the audio signal, means for FM modulating the time-base compressed recorded audio signal, and mixing means for mixing the FM-modulated recorded audio signal and the video signal subjected to the recording signal processing. a recording signal processor 11@ for audio signals; means for extracting an FM-modulated reproduced audio signal from the reproduced signal from the disk; means for FM demodulating the extracted reproduced audio signal; and FM demodulated reproduced audio. The present invention is further provided with a reproduction signal processing circuit for an audio signal having means for time-axis expanding the signal so that the signal becomes a continuous reproduction audio signal.

　　　　　　　　　　　　　.

j [Embodiments of the invention] Hereinafter, the present invention will be explained using the drawings.

FIG. 1 shows a recording signal J of an audio signal according to a first embodiment of the present invention.
1 is a block diagram showing a circuit (recording circuit); FIG.

In the same figure, 33.37 is an LPF 134, an AD converter, 35m, 35b is a memory, 36Fi is a DM converter, 38 is a pre-emphasis circuit, 39 is an FM modulator, 4
0 is a mito circuit, 41 is a mixer, 42 is a limiter, 4
3 is a synchronous separation circuit, 44 is a frequency multiplier circuit, 45all
11 is a division circuit, 46 is a second frequency dividing circuit, and 47 is a memory control circuit.

Figure 2 (*'j~(,) and 3rd WA(f)~(k)
1 is a signal waveform diagram (time chart) showing an example of a signal waveform for explaining the operation of FIG. 1. FIG. In addition, Figure 2 (
a) to (-) and FIGS. 3(f) to (2) correspond to the same reference numerals in FIG.

At the 1st m, an audio signal is input from the terminal. The armpit audio signal is supplied to the AD converter 34 via the LPFt13.

In addition, a video signal is applied to the terminal HIC, and the synchronous separation circuit 4
At step 3, a horizontal synchronizing signal (FIG. 2, 1) is created from the video signal. This horizontal synchronization signal fH passes through a frequency multiplier circuit 44 and an Ml frequency divider circuit 45, and thereby becomes a clock signal used by the AD converter 34 for subtracting the audio signal.

Now, as an example, the multiplier of the frequency multiplier 44 is set to 42.
, 0 where the divisor of the first frequency dividing circuit 45 is 21. Therefore, the frequency 2f)I is twice that of the clock signal horizontal synchronization signal in this embodiment. This state is shown in FIG. 2(b). In this way, since the clock signal (b) is 2fl, the cutoff station wave number of LPi (33) is approximately 1 in order to avoid aliasing distortion of the audio signal.
5 KEz has been selected.

es-1112ail(d) shows the relationship between the audio signal (corresponding to the envelope line) at the AD converter 34 and the clock signal (b).

The audio signal thus digitized by the AD converter 34 is written into the memories 35A and 35b as will be described later.

An address gate signal that is synchronized with and includes the address signal area period obtained when the disk is rotated for recording and reproduction is input from the terminal (2).

As such an address gate signal, for example, a vertical synchronization signal separated from a video signal can be used, or it can also be created by a band signal reproduced from a disc. The following description will be made assuming that a vertical synchronization signal is used.

FIG. 3(f) shows the waveform of the address gate signal.

4 In this example, the first
When using the disk shown in FIG. 5, the address gate signal is applied twice within one Dinuk rotation period. Therefore, in this case, as is clear from the address gate signal having the same frequency as the vertical synchronization signal, the time for one rotation of Dinuk is 33.3 mm.

In this embodiment, the address gate signal is input to the memory control circuit 47 to create write commands and read commands for the memories 35a and 35b.

The write command is from the band gate signal to R679 tube 70.
Create using Tsugu etc. The waveform signal of the compliment command created in this way is shown in FIG. 3 (ω2 and (x).

Therefore, since the write commands ω, (h) from the memory control circuit 47 are alternately input to the memory 35m and the memory 35b, the audio signal digitized by the AD converter 34 is 16.7 mm m. The data is written alternately to the memory 35& and the memory 35b.

On the other hand, the read operation from the memo 935m and 35b is 2f□f. ka) (1!,!:A
(BHil1m□, 8□" is controlled so as not to be decoded.Specifically, #i, the read command sends the write command and the address gate signal through the NOR gate, as shown in FIG. 3 (1). Create as shown in j).

For example, since it is created by taking the NOR between the read command (i) a, the write command ω, and the band gate signal (f), after the write operation to one memory 35& is completed and the subsequent address gate signal disappears, This occurs during the period until the next write command is issued. The same applies to read command U).

Therefore, the digitized audio signal written in the meso 935m and 35ti is read out by the read command (
1) and (j), the memory 35a1 and the memory 35
b are read out alternately and supplied to the DA converter 36.

At this time, the readout pk is the first frequency multiplier circuit 4.
It is created by the second frequency dividing circuit 46 using the output of 4.

In order to read out the signal written in the K, 16.7 ms period as described above in a short period excluding the address gate period, the read clock is set to a higher frequency than the write clock (b). Is it necessary?

Normally, the address signal area period during disk rotation is selected to be approximately three horizontal scanning periods (approximately 190 μB). Therefore, while the write period is 16.7 m@, the maximum read period may be approximately 16 jms. This means that the frequency of the read clock can be approximately 1.01 times or more the frequency of the write clock (b).

Therefore, in this embodiment, the divisor of the second frequency dividing circuit 46 is set to 20, and the clock frequency ratio is set to 1.05 times that of the write clock.

FIG. 2(c) K shows the read clock. Further, (e) in the same figure shows the relationship between the reading clock (C) in the DA converter 36 and the analog audio signal (corresponding to the envelope line).

The audio signal converted into analog again by the DA converter 36 is
FM through LPF 37 and pre-emphasis circuit 38
The signal is supplied to a modulator 39.

In the FM modulator 39, for example, a carrier signal of about 1.5 h, which corresponds to the gap between the spectra of the low-frequency converted color signal and the FM-modulated luminance signal, is converted into F as the audio signal.
M modulates.

Then, the cough FM modulated audio signal is sent to the Mieto circuit 4.
0, and is muted during the address gate signal period by the address gate signal (f) input from terminal 2 to eliminate interference with the address signal. This state is shown in Figure 3).

The output of the Mieto circuit 40 is supplied to a mixer 41. The mixer 41 also receives the low frequency converted color signal from the terminal E and the FM modulation signal from the terminal F.
The luminance signal is input. As a result, the mixer 41 mixes the three signals and sends the mixture to the limiter 42, so that a binary recording signal is generated at the terminal G.

Note that the configuration and operation of the recording system thereafter are the same as those described in section 3 of FIG. 10 above, and will therefore be omitted.

Figure 4 shows a reproduction system circuit (
FIG. 2 is a block diagram showing an example of a reproduction signal processing circuit for audio signals.

In the same figure, the same reference numerals as in FIG. 1 indicate the same - snout.

Show equivalent. 52 is a BPF, 53 is an FM demodulator, 5
4 is a de-emphasis circuit, and 55 is an LPF.

5(a) to 5(,) are signal waveform diagrams (time charts) showing examples of signal waveforms for explaining the operation of FIG. 4. 5 (!L) to (,) and the same reference numerals in FIG. 4 correspond.

Terminal J in Fig. 4 has 1mg of Re*1mg from the disk.
″″(IIxoliiO#″′)f″−6″0″”El
].

added. Therefore, the BPF 52 receives the reproduced signal.

The BPF 52 is for separating the FM modulated audio signal from video information. Therefore, F Mtlfi
Only the audio signal is supplied to the ller 53.

The FM demodulator 53 performs FM demodulation on the audio signal and supplies it to the de-emphasis circuit 54. As a result, the frequency characteristics of the FM demodulated audio signal are corrected by the de-emphasis circuit 54 and then supplied to the AD converter 34.

Further, a video signal is applied to the terminal H.

Therefore, in the same way as the recording system shown in FIG. Memory 35m + 35b (described later)
Create a clock for reading and writing.

The FM demodulated audio signal input to the AD converter 34 is digitized here and stored in memories 35a and 3.
5b.

Therefore, the digitized audio signal is written into the memories 35m, 35b by the write clock, and read out by the read clock.

By the way, in this embodiment, in the recording system of FIG. 1, the signal used as the read clock is used as the write clock, and the signal used as the write clock is used as the read clock.

Specifically, the clock signal from the second frequency dividing circuit 46 is supplied to the AD converter 1i34, and the memory 35m,
35b for writing the digitized audio signal, while the first frequency dividing circuit 45
The clock signal from is used as the read clock.

The terminal 1 has a KS'li5 diagram (
The address gate signal shown in a) is applied. and,
The memory control circuit 47 controls the memory 35a based on the #II ground gate signal in the same manner as in FIG.

35b write and read command signals are created.

However, in this embodiment, the write and read command signals are reversed from those of the recording system shown in FIG.

FIGS. 5(b) and 5(c) show signal waveforms of write commands to the memories 35a1 and 35b. That is, writing of the digitized audio signal is performed alternately between the addresses 35m and 35b, and the writing period line and the address gate signal IF! ! This is the period from 1 to the start of the next address gate signal.

FIG. 5(d) $P and (,) are the memory 35m,
This is a signal waveform of a read command for 35bK.

As is clear from this signal waveform, as mentioned above,
The recorded audio signal is memo 935m.

$1 is applied to each of the 3sb, and is performed from the end of the write operation to the beginning of the next address gauge period.

As a result, the digitized round audio signals alternately extracted from the memories 35m and 35b are continuous, and the signals are subjected to Dm conversion! 36. In addition, cough DA converter 3
6 is supplied with a clock signal from the first frequency dividing circuit 45.

Therefore, the digitized audio signal # is continuously outputted by this DA converter 36Kj? l/1 and converted into an analog signal. Then I, PF554I-
It passes through the terminal and is output from terminal K.

As is clear from the above explanation, 1 In this first embodiment,
To prevent the audio signal from being recorded superimposed on the address signal area,
The time axis is compressed and recorded, and when played back, the time axis is expanded and the IIL image is output.゛This result, this first
According to the embodiment, it is possible to record and reproduce an audio signal together with a video signal without deteriorating the quality.

-□・i Next, an embodiment of s2 of the present invention for suitably recording and reproducing two-channel audio signals will be described. .

Figure 4s6 shows the ffi of the audio signal according to the second embodiment of the present invention.
FIG. 2 is a block diagram showing a sickle signal processing circuit (recording circuit). In the pI1 diagram, the same reference numerals as in FIG. 1 indicate the same or equivalent items. 33m, 33b#1LPF, 34
m.

34btiAD converter, 35m, 35b is memory for the audio signal of the first channel, 35c, 35dj;
tjlG This is a memory for 2-channel audio signals.

FIGS. 7(a) to ω are signal waveform surfaces (time charts) showing examples of signal waveforms for explaining the operation of the sixth prisoner. The numbers (,) to ω in the same figure correspond to the same reference numerals in the is6 figure.

In FIG. 6, the 2-channel audio signal is transmitted to the terminal D1.
And D2 is powered by 9 people. and the audio signal quality,
AD conversion 634m via LPF33m, 33b
, 34bK are supplied respectively.

Further, a video signal is input from the terminal H, and the video signal line, the synchronization separation circuit 43, the frequency multiplier circuit 44, and the first frequency divider circuit 45 are connected to the first embodiment shown in FIG. Similarly, the clock signal 2f, is formed into a clock signal of
') tjIA main clock and memory 35m1 to 35
It is used as a write clock for d.

As a result, the backdoor signals supplied to each of the AD converters 34m and 34b are digitized and written into the memories 35a to 35d, as will be described later.

Further, an address gate signal shown in FIG. 7 (&) is inputted from the terminal (2), and based on this, the memory control circuit 47 creates a write/read command signal for the memories 35a to 35d.

In this example, the cane, memory 35m, 35c, and memory 3
The same write command signal is supplied to 5b and 35d! J7 (b) shows the signal waveform of the write command that can be supplied to the memories 35m and 35e, and (c) of the same figure shows the signal waveform of the write command that can be supplied to the memories 35m and 35e.

35d shows a signal waveform of a write command supplied to 35d.

Therefore, the digitized audio signals of the first channel are written into the memories 35m and 35b alternately every 16.7 ms, as in the first embodiment.

Additionally, in the memories 35c and 35d, a second
The digitized audio signal of the channel will be written as well.

In this way, the audio signals written in the memories 35a to 35d are read out so that the read periods of the respective memories and the address gate signal periods do not overlap in time.

That is, reading from the memory 35m is performed as shown in FIG.
d) is done by the read command signal, Memo! J3
The trailing edge of the address gate signal after the write operation to 5m is completed, and the trailing edge of the address gate signal and the blue
The period is approximately halfway between the leading edge of the next address gate signal.

Reading from the memory 35c is performed by the seventh all (.) read command signal, and is carried out for a period from the end of the read command to the memory 351 to the leading edge of the next address gate signal.

Further, reading from the memory 35b is performed as shown in FIG. 7(f).
It is started from the trailing edge of the address gate signal after the end of the write operation of the memory 35b, and the #t point between the trailing edge of the scissors address gate signal and the leading edge of the <am gate signal. The period up to Chukan is naughty.

Reading from the memory 35d is performed by the read command signal shown in FIG. 7(g), and is carried out for a period from the end of the read command to the memory 35b to the leading edge of the next address gate signal.

2. Here, the read command signal (d) I (6
), the read command signal (f), and ω are discontinuous, so it is necessary to tie this switching.
There are a thousand. In this embodiment, this switching timing is determined by counting, for example, the trailing edge of the address gate signal and the horizontal synchronization signal fP+ supplied from the synchronization separation circuit 43.

Further, the reading clock of the memories 35&~35d reads the audio signal written in the period of 16.7 ms as described above, for a further half period of the period from the address gate signal to the next address gate signal, that is, about 8.7 ms. Since it is necessary to read within a period of 2 ms, the first embodiment of the present invention (first
The frequency must be set to the frequency shown in the figure.

Therefore, in this embodiment, the output of the frequency multiplier circuit 44 is supplied to a second frequency divider circuit 46 whose divisor is 10, which is 1/2 of that in the first embodiment. The received clock signal is used as the readout clock signal. Note that the clock signal is also supplied to the DA converter 36.

The audio signals read out from the memories 35 &~35d are D
After being supplied to the A converter 36 and analogized again here, the LP is converted into an LP whose cutoff frequency is set to approximately twice that of the first embodiment (FIG. 1) (approximately 30 KHz).
After passing through F37 and pre-emphasis circuit 38, FM
The signal is supplied to a modulator 39.

The cough FM modulator 39 performs FM modulation on this input audio signal and supplies it to the mute circuit 40 .

In the mute circuit 40, the address gate signal (,) input from the terminal I mutes the address gate signal period and sends it to the mixer 41, as in the first embodiment.

The mixer 41 mixes the low frequency converted color signal and the FM modulated luminance signal supplied from the terminals E and F with the audio signal output from the mute circuit 40 and sends the mixed signal to the limiter 42 .

Therefore, a binary recording signal can be obtained at terminal G.

Note that the subsequent configuration and operation of the recording system are the same as those described in FIG. 10 above, similar to the first embodiment, and will therefore be omitted.

FIG. 8 is a block diagram showing an embodiment of a reproduction system circuit (audio signal reproduction signal processing circuit) corresponding to the recording system circuit of FIG. 9J6.

In this figure, the same reference numerals as in FIGS. 4 and 6 indicate the same or equivalent parts. 36a and 36b are DA converters, 5
5&, 55b is an LPF.

9(&) to (g) are signal waveform diagrams (time charts) showing examples of signal waveforms for explaining the operation of FIG. 8. 9(&) to (g) and the same reference numerals in FIG. 8 correspond.

A reproduction signal from the disk via a reproduction amplifier (see FIG. 10) is applied to Miko J in FIG. 8. Therefore, the BPF 52 extracts the FM modulated audio signal from the reproduced signal and supplies it to the FM demodulator 53.

As a result, the audio signal is FM demodulated by the FM demodulator 53, and then its frequency characteristics are corrected by the de-emphasis circuit 54 and supplied to the AD converter 34.

Further, a video signal is applied to the terminal H.

Therefore, in the same way as the recording system shown in FIG. At the same time, clocks for reading and writing the memories 35a to 35d, which will be described later, are created.

The FM demodulated audio signal input to the AD converter 34 is digitized here and stored in memories 35a to 35d.
supplied to

Therefore, the digitized audio signal is written into the memories 35a to 35dK by the write clock, and read out by the read clock.

Yoyuua, 8□N ``?' Ifi, N 'm El
1° ka □ 6 "i 4th section", contrary to the recording system of FIG. 6, the clock signal from the 20th frequency dividing circuit 46 is supplied to the AD converter 34, and the
~35d is used as a writing clock to write the digitized audio signal, while the first frequency dividing circuit 45
The clock signal from is used as the read clock.

Similar to the recording system shown in FIG. 6, a number-gate signal shown in FIG. 9 (&) is applied to the terminal. Then, the message control circuit 47 generates write and read command signals for the memories 35a to 35d based on the address gate signal in the same manner as shown in FIG.

However, in this embodiment, as in the first embodiment, the write and a-extension command signals are reversed from those in the recording system of FIG. 6.

Each memory 35a, 35c, 35b, 35d
FIGS. 9(b) to 9(b) show write command signal waveforms for
As is clear from e), a memory is written to the memory 35a during the write command period shown in (b) of the same figure, to the memory 35cK during the write command period shown in (C), and a memo is written to the memory 35cK during the write command period shown in (d) K. ! + 35b, it is written to the memo 1135d during the write/write command period shown in (e).

In this case, since the timing of switching between the write command signals (b) l (e) and (d) (-) is discontinuous, it is necessary to take the timing of this switching p.

In this embodiment, as in the case of the recording system shown in FIG. 6,
This is done by counting the horizontal synchronization signal fH supplied from the synchronization separation circuit 43.

Further, reading from each of the memories is performed from the memories 35a and 35c using the read command signal shown in FIG. 9(f).
Memo 1J35b with the read command signal shown at ω in the figure.

From 35d.

The digitized first channel audio signals successively output from the memories 35a and 35b as described above are supplied to the DA converter 36a, while
The digitized second channel audio signals read out continuously from 5c and 35d are sent to the DA converter 36.
b. Note that the DA converters 36a, 36
b is supplied with a glue lock signal from the first frequency dividing circuit 45.

The audio signal of the first channel inputted to the DA converter 36a is converted into an analog signal and sent to the LPF 55a.
It passes through and is output from terminal 1.

Also, the second channel audio signal input to the DA converter 36b is converted into an analog signal and sent to the LPF 5.
When it passes through 5b and is output from terminal 2, it becomes .

As is clear from the above explanation, this second embodiment is
As in the first embodiment, the two-channel audio signal is compressed and recorded on the time axis so that it is not recorded superimposed on the address signal area, and when played back, the audio signal is expanded on the time axis and extracted. There is.

As a result, according to the second embodiment, it is possible to record and reproduce two-channel audio signals together with video signals without causing quality deterioration.

Furthermore, since the address signal and the voice signal do not overlap in time, it is obvious that the voice signal does not interfere with the address signal. This point is also the same in the first embodiment.

Note that when recording and reproducing two-channel audio signals on a disk, in addition to the second embodiment described above, two sets of the first embodiment are used to change the frequency of the two-channel audio signals.・FM transformation with two carrier signals called A,
This can also be achieved by recording and reproducing by frequency multiplexing.

〔Effect of the invention〕

As is clear from the above #JL feathers, according to the present invention,
To prevent the audio signal from being recorded in the address signal area in a superimposed manner,
Since the time axis is compressed and recorded, and when played back, the time axis is expanded and extracted, so even if the preliminary address signal is partially accumulated and nine discs are used, both the video signal and the audio signal can be processed. This has the effect of allowing suitable recording and reproduction. da

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the recording system circuit of the first embodiment of the present invention, FIGS. FIG. 4 is a block diagram showing an example of a reproducing circuit corresponding to the recording circuit of FIG. 1, and FIG.
) to (・) are signal waveform diagrams showing examples of signal waveforms for explaining the operation of the fourth @, FIG. 6 is a block diagram showing the recording system circuit of the second embodiment of the present invention, and FIG. 7 (a) to (g) are signal waveform diagrams showing examples of signal waveforms for explaining the operation of FIG. 6, and FIG. 8 is an example of a reproduction system circuit corresponding to the recording system circuit in #Article 6. The block diagram shown in Fig. 9(a)~
(g) is a signal waveform showing an example of a signal waveform for explaining the operation of FIG. Further, FIG. 10 is a block diagram showing an example of a conventional video signal recording/reproducing device, FIGS.
The figure is a partially enlarged perspective view showing an example of a disk partially cut away and shown in perspective, FIG. 13(a) is a partially enlarged plan view of one of the guide holes of the disk, and FIG.
b) is a cross-sectional view taken along the line A-A in the same figure (,), Fig. 14 is the spectrum of the recorded video signal and '4 ground signal, and Fig. 15 is a disc showing the address signal area set in advance on the disc. FIG. 11-...Disk, 34, 34a, 34b-=
AD converter, 35IL to 35d...Memory, 36...
- DA converter, 39...FMK adjuster, 40...mute circuit, 41...mixer, 43...synchronous separation circuit, 44...frequency multiplication circuit, 45. ．． 46... Frequency dividing circuit, 47... Memory control circuit, 52... BPF,
53...FM demodulator patent attorney Michi Hiraki
Figure 2 Figure 3 Figure 111111 → Figure 4 Figure 5 Figure 1---→t Q 1. i+kJ No. 7 Figure 1------------------
−−−−−−−−−−−−−m−−−→−tri? 4' 8 Fig. 29 (Cl) , -1] - - 11 ■ - - Go - Fig. 10 Fig. 11 (b) (d) (f) 2 12 vA

Claims (3)

[Claims] (1) In a video disc player that records and plays back video and audio signals using a disc-shaped recording medium (hereinafter referred to as a disc) in which information recording tracks on which address signals are stored in advance are arranged in a spiral or concentric pattern. , means for time-axis compressing the recorded audio signal within a period in which the address signal does not exist, means for FM modulating the time-axis compressed recorded audio signal, and the FM-modulated recorded audio signal and video processed by the recorded signal. a recording signal processing circuit for audio signals having a mixing means for mixing signals, a means for extracting an FM-modulated reproduced audio signal from a reproduced signal from the disk, a means for FM demodulating the extracted reproduced audio signal; A signal processing circuit for a video disc player, comprising: a reproduction signal processing circuit for an audio signal having means for time-axis expanding the FM demodulated reproduction audio signal so that it becomes a continuous reproduction audio signal. (2) The means for time-base compressing the recorded audio signal is a method A/A for converting an analog recorded audio signal into a digital signal.
A D converter, a pair of memories to which the output of the A/D converter is applied, means for creating a memory write clock having a predetermined frequency, and a memory read clock having a higher frequency than the write clock. a means of creating;
means for generating a write command signal for alternately supplying the write clock at a scheduled time to the pair of memories; and means for alternately supplying the read clock at a scheduled time at least within a period in which the address signal does not exist. The apparatus is comprised of means for creating a read command signal to be supplied to the pair of memories, and a D/A converter for converting the digital signal read from the pair of memories into an analog recorded audio signal. A signal processing circuit for a video disc player according to claim 1, characterized in that: (3) The invention further comprises means for preventing the recorded audio signal FM modulated by the FM modulating means from being supplied to the mixing means at least during the period in which the address signal exists. A signal processing circuit for a video disc player according to item 1 or 2.