JPS6190511A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS6190511A JPS6190511A JP59212854A JP21285484A JPS6190511A JP S6190511 A JPS6190511 A JP S6190511A JP 59212854 A JP59212854 A JP 59212854A JP 21285484 A JP21285484 A JP 21285484A JP S6190511 A JPS6190511 A JP S6190511A
- Authority
- JP
- Japan
- Prior art keywords
- junction
- leakage current
- same
- semiconductor integrated
- flows
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/06—Frequency selective two-port networks including resistors
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Filters And Equalizers (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分封〕
本発明は、半4体集積[!2回路において、弓)にイ6
弓処51!I8経路等に?、続されたPN接合素子のリ
ーク電流を補償し、リーク電流による回路誤動作、及び
不具合を防止し、しかも構成が容易な半導体集積回路に
関するものである。[Detailed Description of the Invention] [Industrial Application Separation] The present invention is a semi-quadruple assembly [! In 2 circuits, I6 for bow)
Archery 51! Is it on the I8 route? The present invention relates to a semiconductor integrated circuit that compensates for leakage current of connected PN junction elements, prevents circuit malfunctions and defects caused by leakage current, and is easy to configure.
従来よシ、半導体集積回路内の信号処理回路において信
号経路交流カップリング用あるいは、フィルター用等と
してPN接合素子を利用した接合容量が使用さflてい
る。第2図は、接合谷肘によるローパスフィルタを使用
した信号処理回路の一従来実施ドQてあり、増幅回路1
.6.抵抗3.PN接合容量4よシ構成され、増幅回路
lの出力端子2は抵抗3.接合容量4を介して接地され
、抵抗3と接合容量4の共通接続点は、増幅回路60入
力端子5に接続されており、接合容量4には一定の逆バ
イアス電位が与えられており、抵抗3のや一抗値と接合
容気4の容量値で決定される一定のしゃ断尚波数を廟し
たローパスフィルタを形成している○
〔発明が解決しようとする問題点〕
かかる従来(ロ)路側において、接合容量4に逆バイア
スミ圧によるリークち、流が流れるが、特に接合面積の
大きい場合には無視できない値となシ、このリーク電流
によって接合容量に接続された増幅回路の入力端子の直
流バイアス電位がずれる、小信号入力時に応答しない等
の動作不具合を生じるなどという欠点があった。Conventionally, junction capacitors using PN junction elements have been used for signal path AC coupling, filters, etc. in signal processing circuits in semiconductor integrated circuits. Figure 2 shows a conventional implementation of a signal processing circuit using a low-pass filter with junction valley elbow, and an amplifier circuit 1.
.. 6. Resistance 3. The output terminal 2 of the amplifier circuit 1 is composed of a PN junction capacitor 4 and a resistor 3. A common connection point between the resistor 3 and the junction capacitor 4 is connected to the input terminal 5 of the amplifier circuit 60, and a constant reverse bias potential is applied to the junction capacitor 4. It forms a low-pass filter with a constant cut-off wave number determined by the resistivity value of 3 and the capacitance value of junction volume 4. [Problems to be solved by the invention] Such conventional (b) roadside In this case, a leakage current due to the reverse bias voltage flows in the junction capacitor 4, but this leakage current cannot be ignored, especially when the junction area is large. There were drawbacks such as bias potential deviation and operational problems such as not responding when a small signal was input.
本発明の目的は、半導体集積回路の信号処理回路におけ
るPN嵌合素子のリーク電流を補償し、リーク電流によ
る動作不具合等を改善した半導体集積回路を提供するこ
とにある。An object of the present invention is to provide a semiconductor integrated circuit in which leakage current of a PN fitting element in a signal processing circuit of a semiconductor integrated circuit is compensated for and operational defects caused by the leakage current are improved.
本発明江よれば、同導電方向に直列接続された第1と第
2のPN接合素子を具備し、第1と第2のPN接合素子
の共通接続点に1位意のインピーダンスを有する信号経
路が接続され、第1と第20PN接合素子それぞれにほ
ぼ等しい逆バイアス電位が印加されたことを特徴とする
半導体集積回路が得られる。According to the invention, the signal path includes first and second PN junction elements connected in series in the same conductive direction, and has a unique impedance at a common connection point of the first and second PN junction elements. A semiconductor integrated circuit is obtained, in which the first and twentieth PN junction elements are connected to each other, and substantially equal reverse bias potentials are applied to each of the first and 20th PN junction elements.
次に、本発明について図面を参照してより詳細に説明す
る。Next, the present invention will be explained in more detail with reference to the drawings.
第1図は、本発明による一実施例の回路図であり、第2
図と同一機能素子には、同一符号を付す。FIG. 1 is a circuit diagram of an embodiment according to the present invention, and FIG.
Functional elements that are the same as those in the figures are given the same reference numerals.
増幅回路1の出力端子2は抵抗3、第1の接合各賞4を
介して接地され、抵抗3と第1の接合各賞4の共通接続
点は、ra幅回路6の入力端子5に接続されるとともに
、第2の接合谷ki7が、第1の接合容量と同感電力向
に直列接続となるように1第2の接合る量7の電力の端
子が入力端子5に接続され、接合容気7の他力の端子は
基準電圧回路8に接続され、第1.第2の接合各賞には
、等しい逆バイアス電位が与えられ、その容量値は同一
になるように設定されている。The output terminal 2 of the amplifier circuit 1 is grounded via the resistor 3 and each first junction 4, and the common connection point between the resistor 3 and each first junction 4 is connected to the input terminal 5 of the RA width circuit 6. At the same time, the power terminal of the first and second junctions 7 is connected to the input terminal 5 so that the second junction valley ki7 is connected in series with the first junction capacitor in the direction of the same sensitive electric power. The other power terminal of the voltage 7 is connected to the reference voltage circuit 8, and the first terminal is connected to the reference voltage circuit 8. An equal reverse bias potential is applied to each of the second junctions, and their capacitance values are set to be the same.
本実施しらにおいて第1.第2の接合谷蓋それぞれには
、逆バイアス電位により IJ−り電流が17ii;れ
るが、同−逆バイアス電位を印加し、しかも第1゜第2
の接合各賞を同一半導体集積回路基板上に、同一構造で
ほぼ同一面積になるように近接配置にすることKよって
第1.第2の接合容量・Kは、それぞれに等しいリーク
電流が流れると仮定できる。In this implementation, the first. An IJ current of 17mm is applied to each of the second junction valley lids due to the reverse bias potential.
By arranging each of the bonded parts on the same semiconductor integrated circuit board in close proximity to each other so that they have the same structure and approximately the same area, the first. It can be assumed that equal leakage current flows through each of the second junction capacitances K.
従って、第1の接合容量4に入力端子5から接地力向罠
リーク電流It、1が流れるが、 同時に、第2の接合
各賞7においても、基準電圧回路8から入力端子50方
向にリーク電流IL2が流れ、 これにより、 IL
l = It、1となシ、第1と第2の接合容量のそれ
ぞれのリーク電流は、相互のリーク電流によって補償さ
れ、見かけ上、接合容量が接続された抵抗3と増幅回路
60入力端子5にはリーク電流の影響が現われない。Therefore, a leakage current It,1 flows in the direction of the grounding force from the input terminal 5 to the first junction capacitor 4, but at the same time, leakage current also flows from the reference voltage circuit 8 in the direction of the input terminal 50 in each of the second junctions 7. IL2 flows, which causes IL
l = It, 1, and the respective leakage currents of the first and second junction capacitances are compensated by mutual leakage currents, and apparently the junction capacitances are connected to the resistor 3 and the input terminal 5 of the amplifier circuit 60. The influence of leakage current does not appear in .
以上、述べたように、本発明によれば、信号経路に接続
されたPN接合素子のリーク電流カミむ償され、従って
リーク電流による動作不具合が改善され、しかも構成が
各易な半導体集積回路を提供することができる。As described above, according to the present invention, the leakage current of the PN junction element connected to the signal path can be compensated for, the operational defects caused by the leakage current can be improved, and a semiconductor integrated circuit with an easy configuration can be realized. can be provided.
第1図は1本発明の一実施例を示す回路図、第2図は従
来例を示す回路図である。
1.6・・・・・・増幅回路、2・・・・・・出力端子
、3・・・・・抵抗、4.7・・・・・・接合各賞、5
・・・・・・入力端子、8・・・・・・基準電圧回路。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 1.6... Amplifier circuit, 2... Output terminal, 3... Resistor, 4.7... Junction awards, 5
...Input terminal, 8...Reference voltage circuit.
Claims (1)
素子を具備し、前記第1と第2のPN接合の共通接続点
に任意のインピーダンスを有する信号経路が接続されて
いることを特徴とする半導体集積回路。 2、前記第1と第2のPN接合素子それぞれにはほぼ等
しい逆バイアス電位が印加されていることを特徴とする
特許請求の範囲第1項記載の半導体集積回路。[Claims] 1. A signal path comprising first and second PN junction elements connected in series in the same conductive direction, and having an arbitrary impedance at a common connection point of the first and second PN junctions. A semiconductor integrated circuit characterized in that: is connected to the semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein substantially equal reverse bias potentials are applied to each of the first and second PN junction elements.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59212854A JPS6190511A (en) | 1984-10-11 | 1984-10-11 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59212854A JPS6190511A (en) | 1984-10-11 | 1984-10-11 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6190511A true JPS6190511A (en) | 1986-05-08 |
Family
ID=16629413
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59212854A Pending JPS6190511A (en) | 1984-10-11 | 1984-10-11 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6190511A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011221998A (en) * | 2010-03-25 | 2011-11-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
-
1984
- 1984-10-11 JP JP59212854A patent/JPS6190511A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011221998A (en) * | 2010-03-25 | 2011-11-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
US9092710B2 (en) | 2010-03-25 | 2015-07-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
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