JPS6190326U - - Google Patents
Info
- Publication number
- JPS6190326U JPS6190326U JP17529884U JP17529884U JPS6190326U JP S6190326 U JPS6190326 U JP S6190326U JP 17529884 U JP17529884 U JP 17529884U JP 17529884 U JP17529884 U JP 17529884U JP S6190326 U JPS6190326 U JP S6190326U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- circuit
- thyristor
- gate
- terminal thyristor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 7
- 230000001939 inductive effect Effects 0.000 description 1
Landscapes
- Circuit Arrangements For Discharge Lamps (AREA)
- Thyristor Switches And Gates (AREA)
Description
第１図は本考案に係る半導体スイツチ回路を使
用した放電灯点回路の電気回路図、第２図は本考
案に係る半導体スイツチ回路の別の実施例におけ
る電気回路図、第３図は同じく更に別の実施例に
おける電気回路図、第４図は従来の半導体スイツ
チ回路による放電灯点灯回路の電気回路図、第５
図は同じく正サイクル時の電気的等価回路図、第
６図は同じく負サイクル時の電気的等価回路図第
７図は非直線性誘電体素子の印加電圧一蓄積電荷
量のヒステリシス特性を示す図である。
１……放電灯、２……誘導性安定器、４……半
導体スイツチ回路、ＳＣＲ……三端子サイリスタ
、ＮＬ……非直線性誘電体素子、Ｒ……抵抗、Ｃ
……コンデンサ、Ｒ１〜Ｒ８……抵抗、Ｃ１〜Ｃ
３……コンデンサ、Ｄ１〜Ｄ６……ダイオード。
FIG. 1 is an electric circuit diagram of a discharge lamp lighting circuit using a semiconductor switch circuit according to the present invention, FIG. 2 is an electric circuit diagram of another embodiment of the semiconductor switch circuit according to the present invention, and FIG. An electric circuit diagram in another embodiment, FIG. 4 is an electric circuit diagram of a discharge lamp lighting circuit using a conventional semiconductor switch circuit, and FIG.
The figure is an electrical equivalent circuit diagram during a positive cycle, and Figure 6 is an electrical equivalent circuit diagram during a negative cycle. Figure 7 is a diagram showing the hysteresis characteristic of applied voltage versus accumulated charge of a nonlinear dielectric element. It is. 1... Discharge lamp, 2... Inductive ballast, 4... Semiconductor switch circuit, SCR... Three-terminal thyristor, NL... Nonlinear dielectric element, R... Resistor, C
... Capacitor, R 1 to R 8 ... Resistor, C 1 to C
3 ...Capacitor, D1 to D6 ...Diode.
Claims (1)
いて導通し得るように交流入力端子に接続された
三端子サイリスタと、前記三端子サイリスタの正
または負の何れか一方のサイクルの導通時に、こ
の三端子サイリスタに対して直列となるように接
続される非直線性誘電体素子とを備える半導体ス
イツチ回路において、前記三端子サイリスタは、
正または負の一方のサイクル時に前記交流入力電
圧を分圧してゲートを駆動する回路と、正または
負の一方のサイクル時に電荷が蓄積され、蓋積電
荷を他のサイクル時にゲートに与えて三端子サイ
リスタの導通を維持するコンデンサとを備えるゲ
ート回路を有することを特徴とする半導体スイツ
チ回路。 (2) 前記コンデンサは、直列に接続された抵抗
を通して前記三端子サイリスタのゲートとカソー
ドとの間に接続されることを特徴とする実用新案
登録請求の範囲第１項に記載の半導体スイツチ回
路。 (3) 前記コンデンサ及び前記抵抗の直列回路に
対して並列に他の抵抗を接続したことを特徴とす
る実用新案登録請求の範囲第２項に記載の半導体
スイツチ回路。 (4) 前記コンデンサは、正または負の一方のサ
イクル時に前記交流入力電圧を分圧してゲートを
駆動する前記回路と、三端子サイリスタのゲート
との間に直列に接続し、前記回路と前記三端子サ
イリスタのカソードとの間に抵抗を接続したこと
を特徴とする実用新案登録請求の範囲第１項に記
載の半導体スイツチ回路。[Claims for Utility Model Registration] (1) A three-terminal thyristor connected to an AC input terminal so as to be conductive during both positive and negative cycles of an AC input voltage, and either the positive or negative terminal of the three-terminal thyristor. In a semiconductor switch circuit comprising a non-linear dielectric element connected in series with the three-terminal thyristor during conduction in one cycle, the three-terminal thyristor
A circuit that divides the AC input voltage to drive the gate during one positive or negative cycle, and a circuit that accumulates charge during one positive or negative cycle and provides a cap product charge to the gate during the other cycle to form a three-terminal circuit. 1. A semiconductor switch circuit comprising a gate circuit including a capacitor that maintains conduction of a thyristor. (2) The semiconductor switch circuit according to claim 1, wherein the capacitor is connected between the gate and cathode of the three-terminal thyristor through a resistor connected in series. (3) The semiconductor switch circuit according to claim 2, wherein another resistor is connected in parallel to the series circuit of the capacitor and the resistor. (4) The capacitor is connected in series between the circuit that divides the AC input voltage to drive the gate during one of the positive or negative cycles and the gate of the three-terminal thyristor, and connects the circuit and the three-terminal thyristor. The semiconductor switch circuit according to claim 1, wherein a resistor is connected between the cathode of the terminal thyristor and the cathode of the terminal thyristor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17529884U JPH0336077Y2 (en) | 1984-11-19 | 1984-11-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17529884U JPH0336077Y2 (en) | 1984-11-19 | 1984-11-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6190326U true JPS6190326U (en) | 1986-06-12 |
| JPH0336077Y2 JPH0336077Y2 (en) | 1991-07-31 |
Family
ID=30732903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17529884U Expired JPH0336077Y2 (en) | 1984-11-19 | 1984-11-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0336077Y2 (en) |
-
1984
- 1984-11-19 JP JP17529884U patent/JPH0336077Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0336077Y2 (en) | 1991-07-31 |
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