JPS6190034U - - Google Patents
Info
- Publication number
- JPS6190034U JPS6190034U JP17630984U JP17630984U JPS6190034U JP S6190034 U JPS6190034 U JP S6190034U JP 17630984 U JP17630984 U JP 17630984U JP 17630984 U JP17630984 U JP 17630984U JP S6190034 U JPS6190034 U JP S6190034U
- Authority
- JP
- Japan
- Prior art keywords
- setting circuit
- function setting
- function
- circuit
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006870 function Effects 0.000 claims 7
- 239000003990 capacitor Substances 0.000 description 1
Description
図は本考案回路の一実施例を示すものである。
1〜4…操作スイツチ、5…フアンクシヨン設
定回路、6…大容量コンデンサ、14〜18…イ
ニシヤライズ用ダイオード、20…スタンバイ・
スイツチ。
The figure shows one embodiment of the circuit of the present invention. 1 to 4...operation switch, 5...function setting circuit, 6...large capacity capacitor, 14 to 18...initialization diode, 20...standby/
Switch.
Claims (1)
複数の操作スイツチと、該各操作スイツチの操作
により夫々各入力端に指令信号が入力されると共
に該各指令信号の入力により所望のポジシヨンに
設定されるフアンクシヨン設定回路と、録音或い
は再生のタイマー・スタンバイ状態と非タイマー
・スタンバイ状態とをセレクトするスタンバイ・
スイツチと、タイマー・スタンバイ動作時に前記
フアンクシヨン設定回路を予じめメモリーされた
ポジシヨンに設定するよう該フアンクシヨン設定
回路のメモリーをバツクアツプするバツクアツプ
回路と、電源投入時に前記スタンバイ・スイツチ
が非タイマー・スタンバイ状態に設定されている
際には前記フアンクシヨン設定回路のメモリーを
クリヤーする共に該フアンクシヨン設定回路をイ
ニシヤライズ・ポジシヨンに設定するイニシヤラ
イズ回路とを具備してなる事を特徴とするテープ
レコーダー。 A plurality of operation switches that are operated in conjunction with a function switching operation, and a function that inputs a command signal to each input terminal by operating each of the operation switches, and is set to a desired position by inputting each of the command signals. A setting circuit and a standby switch that selects between a timer standby state for recording or playback and a non-timer standby state.
a backup circuit for backing up the memory of the function setting circuit so as to set the function setting circuit to a pre-memorized position during timer standby operation; A tape recorder comprising: an initialization circuit that clears the memory of the function setting circuit and sets the function setting circuit to an initialization position when the function setting circuit is set.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17630984U JPS6190034U (en) | 1984-11-20 | 1984-11-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17630984U JPS6190034U (en) | 1984-11-20 | 1984-11-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6190034U true JPS6190034U (en) | 1986-06-11 |
Family
ID=30733908
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17630984U Pending JPS6190034U (en) | 1984-11-20 | 1984-11-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6190034U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02104411U (en) * | 1989-02-07 | 1990-08-20 |
-
1984
- 1984-11-20 JP JP17630984U patent/JPS6190034U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02104411U (en) * | 1989-02-07 | 1990-08-20 |
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