JPS6188323U - - Google Patents

Info

Publication number
JPS6188323U
JPS6188323U JP17344084U JP17344084U JPS6188323U JP S6188323 U JPS6188323 U JP S6188323U JP 17344084 U JP17344084 U JP 17344084U JP 17344084 U JP17344084 U JP 17344084U JP S6188323 U JPS6188323 U JP S6188323U
Authority
JP
Japan
Prior art keywords
doubler rectifier
voltage doubler
circuit
output
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17344084U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17344084U priority Critical patent/JPS6188323U/ja
Publication of JPS6188323U publication Critical patent/JPS6188323U/ja
Pending legal-status Critical Current

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Landscapes

  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す回路図、第2
図は従来の回路図である。 REC,REC…倍電圧整流回路、SW
…スイツチング回路、SW…ミユーテイングス
イツチ、D…ダイオード、CONT…コントロール信
号、IN…入力端子、OUT…出力端子。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a conventional circuit diagram. REC 1 , REC 2 ... Voltage doubler rectifier circuit, SW 1
...Switching circuit, SW 2 ...Muting switch, D...Diode, CONT...Control signal, IN...Input terminal, OUT...Output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 同じコントロール信号が入力される異なる応答
速度の2つの倍電圧整流回路を設け、これら倍電
圧整流回路の第1の出力端をダイオードを介して
第2の倍電圧整流回路の出力端に接続し、この第
1の倍電圧整流回路の出力電圧によつてオン・オ
フ動作するスイツチング回路を設け、このスイツ
チング回路の出力によつてアナログ信号レベルを
調整するレベル調整スイツチを設けたことを特徴
とする自動レベル制御回路。
Two voltage doubler rectifier circuits with different response speeds to which the same control signal is input are provided, and a first output terminal of these voltage doubler rectifier circuits is connected to an output terminal of a second voltage doubler rectifier circuit via a diode, An automatic device characterized in that a switching circuit is provided that is turned on and off depending on the output voltage of the first voltage doubler rectifier circuit, and a level adjustment switch is provided that adjusts the analog signal level by the output of this switching circuit. Level control circuit.
JP17344084U 1984-11-14 1984-11-14 Pending JPS6188323U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17344084U JPS6188323U (en) 1984-11-14 1984-11-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17344084U JPS6188323U (en) 1984-11-14 1984-11-14

Publications (1)

Publication Number Publication Date
JPS6188323U true JPS6188323U (en) 1986-06-09

Family

ID=30731095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17344084U Pending JPS6188323U (en) 1984-11-14 1984-11-14

Country Status (1)

Country Link
JP (1) JPS6188323U (en)

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