JPS6184032A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6184032A
JPS6184032A JP20590784A JP20590784A JPS6184032A JP S6184032 A JPS6184032 A JP S6184032A JP 20590784 A JP20590784 A JP 20590784A JP 20590784 A JP20590784 A JP 20590784A JP S6184032 A JPS6184032 A JP S6184032A
Authority
JP
Japan
Prior art keywords
wiring
protective film
corrosion
power source
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20590784A
Other languages
Japanese (ja)
Inventor
Junji Tanaka
順治 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20590784A priority Critical patent/JPS6184032A/en
Publication of JPS6184032A publication Critical patent/JPS6184032A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Abstract

PURPOSE:To reduce the corrosion of an Al wiring by a method wherein, in a resin sealed semiconductor device, the first conductive wiring to be connected to the power source of high tension and the second conductive wiring to be connected to the power source of low tension are provided on the surface of a protective film in such a manner that they are opposing to each other. CONSTITUTION:An SiO2 film 2, a poly Si wiring 3, an SiO2 film 4 and an Al wiring 5 are superposed on the Si substrate 1 having an element part, pads 9 and 10 are provided together with the wiring 5. A protective film is coated, and an aperture is provided on the pads 9 and 10. Conductive wirings 7 and 8 are opposingly formed on the protective film 6, one end of them is connected to the pads 9 and 10 respectively, metal fine wires 11 and 12 are connected, one end of them is connected to a high tension power source terminal and other end is connected to a low tension power source terminal and sealed by resin 13. At this time, the positive ions such as Na<+> and the like, which are the cause of corrosion of the Al wiring 5, are pulled closer to a low tension wiring, the negative ions such as Cl<-> and the like are pulled closer to a high tension wiring, and the intrusion of said ions into the Al 5 is prevented, and the corrosion of Al can be reduced or removed to nil.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体装置に関し、特に樹脂封止型半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a resin-sealed semiconductor device.

（従来の技術） 従来よυ樹脂封止型半導体装置の耐湿性が問題となって
おり、特に配線腐食が大きな問題となっている。現在の
半導体装置は、配線金属とじて通常ＡＪが使用されてい
る。ＡＩは通常環境下では表面が酸化物で覆われ、比較
的安定に存在しているが、　Ｎａ　、　Ｃｌ　　等イオ
ン、及び水分の作用により、容易に腐食を生ずる。(Prior Art) Conventionally, the moisture resistance of resin-sealed semiconductor devices has been a problem, and wiring corrosion has become a particularly serious problem. Current semiconductor devices usually use AJ as wiring metal. In a normal environment, the surface of AI is covered with oxides and exists relatively stably, but it is easily corroded by the action of ions such as Na and Cl and moisture.

（発明が解決し工すとする問題点） 上記のＡＩの腐食を防止する対策としては、封止樹脂中
のＮａ、ＣＶ−等のイオン含有量を減する、表面保護膜
を欠陥のなりものに近つける等が考えられるが、まだＡ
／の腐食を防き゛きれないのが現状である。(Problems to be solved by the invention) Measures to prevent the corrosion of AI mentioned above include reducing the content of ions such as Na and CV- in the sealing resin, and removing the surface protective film from defects. It is possible to approach it, but it is still A.
The current situation is that it is not possible to prevent corrosion of /.

本発明の目的は、上記欠点全除去し、Ｎａ”、Ｃ６−等
のイオンによるＡ／の腐食を低減もしくはなくすことの
できる構造を有する半導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a structure that eliminates all of the above-mentioned drawbacks and reduces or eliminates corrosion of A/ by ions such as Na'' and C6-.

（問題点を解決するための手段） 本発明の半導体装置は、素子部が形成されている半導体
基板の前記素子部に接続するＡｌ配線と該Ａ７配線を覆
っている絶縁体の保ご膜と′ｆ！：設けた半導体チップ
金有し該半導体チップ金甜脂封止して成る半導体装置に
おいて、前記保護膜表面に高電圧電源に接続される第１
の導体配線と低電圧電源に接続される第２の導体配線と
金向い合わせて設けることにより構成される。(Means for Solving the Problems) The semiconductor device of the present invention includes an Al wiring connected to the element part of a semiconductor substrate on which an element part is formed, and an insulating protective film covering the A7 wiring. 'f! : In a semiconductor device comprising a semiconductor chip metal and sealed with gold and fat, a first layer connected to a high voltage power supply is provided on the surface of the protective film.
The first conductor wiring and the second conductor wiring connected to the low voltage power supply are arranged to face each other.

（実施例〕 次に、本発明の実施例について図面上用いて説明する。(Example〕 Next, embodiments of the present invention will be described with reference to the drawings.

第１図（ａ）〜（Ｃ）は本発明の一実施例の平面図、Ａ
−Ａ／断面図及びＢ−Ｂ’断面図である。FIGS. 1(a) to 1(C) are plan views of one embodiment of the present invention, A
-A/ sectional view and BB' sectional view.

半導体基板ＩＫは素子部が形成される（図示せず）。半
導体基板表面を絶縁膜２で覆い、この上にポリシリコン
等の配線３を形成する。層間絶縁膜４で覆い、この上に
Ａｌ配線５を設ける。このとき、高電圧電源及び低電圧
電源へ接続するためのパッド９．１０に設けておく。そ
して、絶縁体の保護膜６を被覆し、パッド９，１ｏの部
分を開口する。An element portion is formed on the semiconductor substrate IK (not shown). The surface of the semiconductor substrate is covered with an insulating film 2, and wiring 3 made of polysilicon or the like is formed thereon. It is covered with an interlayer insulating film 4, and an Al wiring 5 is provided thereon. At this time, pads 9 and 10 are provided for connection to a high voltage power source and a low voltage power source. Then, a protective film 6 made of an insulator is covered, and the pads 9 and 1o are opened.

次に、本発明による第１の導体配線７と第２の導体配線
８とを向い合わせて保護膜６の表面に形成する。第１及
び第２の導体配線７，８の一端はパッド９，１０に接続
せしめる。そして金属細線１１．１２ｅそれぞれパッド
１１．１２にボンディングする。金属細線１１．１２の
うちの一方は高電圧側電源端子に、他方は低電圧側電源
端子に接続する。最後に、樹脂１３で封止する。Next, the first conductor wiring 7 and the second conductor wiring 8 according to the present invention are formed facing each other on the surface of the protective film 6. One ends of the first and second conductor wirings 7 and 8 are connected to pads 9 and 10. Then, the thin metal wires 11 and 12e are bonded to the pads 11 and 12, respectively. One of the thin metal wires 11 and 12 is connected to a high-voltage power terminal, and the other is connected to a low-voltage power terminal. Finally, it is sealed with resin 13.

以上説明したような構造にして、導体配線７゜８の一方
に高電圧を、他方に低電正金印加すると、Ａｌ配線５の
腐食の原因となるＮａ等の陽イオンは低電圧デ１１配線
に、ＣＩ−等の陰イオンは高電圧側配線に引寄せられ、
Ａｌ配線５への侵入を防ぐことができ、ＡＪ配線５の腐
食全低減あるいは皆無にすることができる。With the structure explained above, when a high voltage is applied to one side of the conductor wiring 7.8 and a low electric current is applied to the other, cations such as Na, which cause corrosion of the Al wiring 5, are removed from the low voltage de 11 wiring. In addition, anions such as CI- are attracted to the high voltage side wiring,
Intrusion into the Al wiring 5 can be prevented, and corrosion of the AJ wiring 5 can be completely reduced or eliminated.

（発明の効果〕 以上説明し７’Ｃ工うに、本発明にＬれば、Ａｌ配線の
腐食全低減あるいは皆無にすることのできる樹脂封止型
の半導体装置上寿ることができる。(Effects of the Invention) As explained above, if the present invention is applied, a resin-sealed semiconductor device that can completely reduce or eliminate corrosion of Al wiring can be produced.

【図面の簡単な説明】[Brief explanation of drawings]

第１図ｆａ）〜（Ｃ）は本発明の一実施例の平面図、Ａ
−Ａ　／断面図及びＢ−Ｂ′断面図である。 ｌ−・・・・半導体基板、２・・・・絶縁膜、３・・・
、・・配線、４・・・・層間絶縁膜、５・・・・・・Ａ
ｌ配線、６・・・・・保護膜、７，８・・・・・・導体
配線、９．１０・・・・・・パッド、１１．１２・・・
・・金属細線、１゛３・・・・・・樹脂。 ／ｌ− ７１−・・５．＼ 代理人　弁理士　　内　原　　　Ｅａ５、−〇・ ｆ”’　−−”−−−−−−−’−−１へ／１３病　１
　図Figures 1 fa) to (C) are plan views of an embodiment of the present invention;
-A/ sectional view and BB' sectional view. l-... Semiconductor substrate, 2... Insulating film, 3...
,...Wiring, 4...Interlayer insulating film, 5...A
l wiring, 6...protective film, 7,8...conductor wiring, 9.10...pad, 11.12...
...Thin metal wire, 1゛3...Resin. /l- 71-...5. \ Agent Patent Attorney Uchihara Ea5, -〇・ f”'−-”−−−−−−−'−1 to 1/13 disease 1
figure

Claims (1)

【特許請求の範囲】[Claims] 　素子部が形成されている半導体基板の前記素子部に接
続するＡｌ配線と該Ａｌ配線を覆っている絶縁体の保護
膜とを設けた半導体チップを有し該半導体チップを樹脂
封止して成る半導体装置において、前記保護膜表面に高
電圧電源に接続される第１の導体配線と低電圧電源に接
続される第２の導体配線とを向い合わせて設けたことを
特徴とする半導体装置。A semiconductor chip having an Al wiring connected to the element part of a semiconductor substrate on which an element part is formed and an insulating protective film covering the Al wiring, and the semiconductor chip is sealed with a resin. A semiconductor device, characterized in that a first conductor wiring connected to a high voltage power supply and a second conductor wiring connected to a low voltage power supply are provided facing each other on the surface of the protective film.
JP20590784A 1984-10-01 1984-10-01 Semiconductor device Pending JPS6184032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20590784A JPS6184032A (en) 1984-10-01 1984-10-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20590784A JPS6184032A (en) 1984-10-01 1984-10-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6184032A true JPS6184032A (en) 1986-04-28

Family

ID=16514726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20590784A Pending JPS6184032A (en) 1984-10-01 1984-10-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6184032A (en)

Similar Documents

Publication Publication Date Title
JPS62145758A (en) Method for protecting copper bonding pad from oxidation using palladium
JPS6184032A (en) Semiconductor device
JPS59229850A (en) Semiconductor device
JPS59154054A (en) Wire and semiconductor device using it
JP2933554B2 (en) Semiconductor device and manufacturing method thereof
JPH0311736A (en) Wiring electrode of integrated circuit
JPS60144957A (en) Semiconductor device
JPH0142347Y2 (en)
JPS6146056A (en) Semiconductor device
JPS617638A (en) Semiconductor device
JPH01319956A (en) Semiconductor integrated circuit
JPH0426215B2 (en)
JPH03104131A (en) Semiconductor device
JPS61252652A (en) Resin sealed type semiconductor device
JPS60120534A (en) Semiconductor device
JPS61253847A (en) Highly reliable semiconductor device
JPS61114558A (en) Semiconductor integrated circuit device
JPS6092644A (en) Semiconductor device
JPS62216339A (en) Semiconductor device and manufacture thereof
JPS613420A (en) Semiconductor integrated circuit device
JPH05304155A (en) Semiconductor chip and mounting thereof
JPS61232637A (en) Semiconductor device
JPS61187269A (en) Semiconductor device
JPS58197736A (en) Semiconductor device
JPS62237737A (en) Semiconductor integrated circuit device