JPS6181798U - - Google Patents
Info
- Publication number
- JPS6181798U JPS6181798U JP16599584U JP16599584U JPS6181798U JP S6181798 U JPS6181798 U JP S6181798U JP 16599584 U JP16599584 U JP 16599584U JP 16599584 U JP16599584 U JP 16599584U JP S6181798 U JPS6181798 U JP S6181798U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- buffer
- detection circuit
- mode detection
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 238000007599 discharging Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
Description
第1図は本効案におけるステツピングモータ駆
動制御回路の1実施例を示す回路図、第2図は第
1図における各部の状態を示すタイミングチヤー
ト、第3図は本実施例におけるモード検出回路の
一部を示す回路図、第4図は第3図における各部
の状態を示すタイミングチヤート、第5図はバツ
フアモードシークにおけるグラフである。
1…モード検出回路、2…カウンター回路、3
…パルスジエネレータ、4…CR充放電回路、6
…マルチバイブレータ、7…フリツプフロツプ。
Fig. 1 is a circuit diagram showing one embodiment of the stepping motor drive control circuit in this embodiment, Fig. 2 is a timing chart showing the states of each part in Fig. 1, and Fig. 3 is a mode detection circuit in this embodiment. 4 is a timing chart showing the states of each part in FIG. 3, and FIG. 5 is a graph in buffer mode seek. 1...Mode detection circuit, 2...Counter circuit, 3
...Pulse generator, 4...CR charging/discharging circuit, 6
...Multi-vibrator, 7...Flip-flop.
Claims (1)
、シークモードを検出するモード検出回路と、前
記モード検出回路からのスタート信号に応答して
バツフアパルスを発生するパルスジエーネレータ
と、前記バツフアパルスと前記モード検出回路か
らのステツプパルスとをカウントするカウンター
回路と、前記バツフアパルスの間隔を変化させる
CR充放電回路とを設けたことを特徴とするステ
ツピングモータ駆動制御回路。 A recording/reproducing apparatus using a fixed magnetic disk includes a mode detection circuit that detects a seek mode, a pulse generator that generates a buffer pulse in response to a start signal from the mode detection circuit, and a pulse generator that generates a buffer pulse in response to a start signal from the mode detection circuit. 1. A stepping motor drive control circuit comprising: a counter circuit for counting step pulses; and a CR charging/discharging circuit for changing the interval between buffer pulses.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16599584U JPS6181798U (en) | 1984-11-01 | 1984-11-01 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16599584U JPS6181798U (en) | 1984-11-01 | 1984-11-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6181798U true JPS6181798U (en) | 1986-05-30 |
Family
ID=30723831
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16599584U Pending JPS6181798U (en) | 1984-11-01 | 1984-11-01 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6181798U (en) |
-
1984
- 1984-11-01 JP JP16599584U patent/JPS6181798U/ja active Pending
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