JPS6180334A - Electronic computer - Google Patents

Abstract

PURPOSE:To access a bus in the receiving order of I/O access requests by discriminating an I/O instruction or an I/O space by an address conversion unit. CONSTITUTION:An address transducer unit (ATU) decides whether an operand access request (4) from an instruction decoder unit (IDU) is an I/O instruction or not and outputs an access request (5) to a bus interface unit (BIU). If a precedently inputted access request is 'I/O WRITE', the BIU executes and completes the 'I/O WRITE' instruction and then executes an 'I/O WRITE' instruction which is being requested at present. The ATU can discriminates the I/O instruction by receiving an I/O access from the IDU or discriminating a previously set memory space.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the architecture of electronic computers. In particular, it relates to a microcomputer with a pipeline control structure using a bus access control method.

[Conventional technology]

Conventionally, microcomputers made possible by large-scale integrated circuit (hereinafter referred to as rLsIJ) technology have generally been based on the premise of directly controlling input/output in addition to memory reading and writing in order to keep the cost of application equipment down. It was being created.

On the other hand, due to the rapid progress of LSI technology, advanced architectures used in large-scale computers have recently become available.
With the introduction of SI, microcomputers with significantly improved performance have appeared.

One of them is the pipeline control structure. In an electronic computer having a pipeline control structure, the internal operations of the computer are divided into those that can be executed in parallel, as shown in FIG. The divided units are connected like a pipeline, and the instruction is executed by sequentially performing reading (2), decoding (2), operand reading (2), execution (2), and result storage (3).

At this time, the processing for each part can be completed in a short time, so as shown in FIG.
, I4, -1T, each takes 5 units of time to execute, but
Each unit is executed in parallel, and in reality, multiple units of instruction sequences are processed simultaneously in one unit of time.
It is considerably shorter than n unit time.

[Problem that the invention seeks to solve]

However, in microcomputers using LSI,
In general, since direct input/output is controlled, problems unique to the pipeline control structure occur, which did not occur in large-scale computers. This is a problem in which the order of accesses is changed, which is generally called a hazard. That is, in FIG. 5, if the address of result storage ■ of instruction sequence 11 and the address of operand read ■ of instruction sequence I2 are the same, the instruction sequence I2
The program may not operate properly because the operand read (2) is read before the result storage (2) of the instruction sequence 11. For this reason, in large computers, the address for storing the result of instruction sequence ``1'' is compared with the address for reading the operand of instruction sequence I2. A mechanism is provided to make the program wait until execution has finished.

However, in the case of input/output commands, hazard control may be necessary even if the addresses (usually referred to as "boats") are different. ■It was not enough to just look at it.

That is, when a program that causes an input/output control hazard is executed, conventional hazard control cannot solve this problem.

FIG. 2 is a flowchart showing an example of a program in which a human output control hazard occurs.

In this flowchart 4j, data is transferred from memory address M to the register of input/output device I10 called boat A (Il), and input/output status is read from boat B (1).
2) shows a program (I,) that checks its status and proceeds to the next step when it becomes ready. At this time, boat A and boat 1-B often do not have the same address.

FIG. 3 (Δ) is a time chart showing how instructions 1 and I2 in FIG. 2 are executed in a microcomputer with a conventional pipeline control structure.

In other words, the contents of memory (M) are read at time ``5'', boat B is searched for at time ``6'', and the contents of memory (M) are sent to boat A at time ``8''. , the contents of boat B are the state before data is set in boat A, and boat B is the state before data is set in boat A.
If the state changes due to this, the instruction will not be executed correctly.

Since it is generally impossible to make boat A and boat B have the same address, conventional hazard control has not been able to solve this problem.

The present invention has been made in view of these conventional problems, and an object of the present invention is to provide a device capable of input/output control using a microcomputer having a pipeline control structure.

[Means to solve the problem]

The present invention is characterized in that input/output commands or input/output spaces are identified, and input/output access requests are received by accessing the bus in order.

That is, a memory and an input/output device, a bus interface unit connected thereto, an instruction decoder connected to the bus interface unit, and an input device inserted between the output of the instruction decoder and the input of the bus interface unit. In an electronic computer with a pipeline control structure, the address conversion unit is connected to the output of an instruction decoding unit and the output of a bus interface unit, and an instruction execution unit that outputs an instruction execution result to the bus interface unit. The unit is provided with means capable of identifying at least an input/output instruction or an input/output space, and the bus interface unit is configured such that when a bus access request received from the address translation unit is an input/output instruction, the bus access request is arranged in the order of arrival of the bus access request. It is characterized by having a means for accessing the bus.

[For production]

In the present invention, the address translation unit identifies input/output commands, and the bus interface unit can execute the input/output commands received from the address translation unit in the order in which the input/output access requests arrive, regardless of the input/output port number.

Therefore, the bus access execution order of the human output operand read request from the instruction decoding section and the input/output operand write request from the instruction execution section can be executed in the same order as the flow of the program.

That is, a microcomputer with a pipeline control structure can provide an architecture that allows input/output control.

(Example〕 DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In Figure 1, there is a bus interface (UNIS) BItJ that controls the bus, reads and writes data, an instruction decoder IDU that decodes instructions and issues operand access requests, and an instruction decoder IDU that converts addresses from the IDU (for example, from virtual addresses to (convert to real address),
The address translation unit identifies the type of access, whether it is to the input/output device 110 or to the memory, and transmits it to the bus interface unit BIU.The address conversion unit executes the operand read from the bus interface unit BTU and sends the result. It consists of an instruction execution unit EXU that supplies instructions to the bus interface unit BIU, and is connected to the memory and the input/output device I10 via the bus interface unit BIU.

To simplify the explanation, in this embodiment, the instruction reading pipe P1 is located between the bus interface unit BIU and the instruction decoding unit IDU, and the instruction decoding pipe P2 is located between the instruction decoding unit IDU and the instruction execution unit EXU. It is assumed that there is an operand read pipe P3 between the bus interface unit BTU and the instruction execution unit EXU.

An example of the flow of data and control signals in each part at this time is: ■ Memory or interior design? The bus interface unit 1131U reads the instruction from 1iI10, ■ Puts the read instruction into the instruction reading pipe P+', ■ Inputs the instruction from the instruction reading pipe P1 to the instruction decoding unit TDtJ, ■ Deciphers the input instruction in the instruction decoding unit IDU. , sends an operand request to the address translation unit ATU and at the same time sends the decoded instruction to the instruction decoding pipe P2. ■ The operand access request translated by the address translation unit ATU is sent to the bus interface unit BTU.
■ The bus interface unit BIU reads the operand from the memory or input/output device (I/O device) 10, ■ The bus interface unit BTU flows the read operand to the operand reading pipe P3, ■ The instruction decoding pipe P2 and the operand reading pipe P3
The instruction execution unit EXIJ inputs the instructions and operands from the instruction execution unit EXIJ. When the instruction execution unit EXIJ receives the instructions and data, it processes the data according to the instructions and passes the results to the bus interface unit BIU. [Phase] Bus interface The unit BTU provides this data to the memory or input/output device I10, as described above.

When a computer with such a structure executes a program as shown in FIG. 2 and the present invention is applied, instructions 1+, I
A time chart showing how z is executed is shown in FIG. 3(B).

Unlike the conventional example shown in FIG. 3 (A>), access to boat B is delayed until time "9" when writing to boat A ends, indicating that the instructions are executed in an orderly order. There is.

That is, the address translation unit ATU is the instruction decoding unit I.
The bus interface unit B determines whether the operand access request (■) from the DU is an input/output command.
An access request is issued to I tJ (■), and the bus interface unit BIU sends an access request to rT.
If lo-WRITEj, this rIlo-WRIT
After executing and completing the EJ instruction, the rllo currently being requested
- The READJ command is being executed.

The address translation unit (UNISO) ATU is given input/output access from the instruction decoding unit (DU) or can identify input/output instructions by identifying a preset memory space.

〔Effect of the invention〕

The present invention has the advantage of being able to provide an electronic computer that is capable of hazard-free human output control using a microcomputer with a pipeline control structure.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a flowchart showing an example of a program in which an input/output control hazard occurs. FIG. 3(A) is a time chart showing the operation of an electronic computer when a hazard occurs in input/output control in a conventional example. FIG. 3(B) is a time chart showing the operation of the computer when input/output control hazards are avoided according to the present invention. FIG. 4 is a block diagram showing an example of the operation of an electronic computer having a pipeline control structure. FIG. 5 is a time chart showing an example of the operation of an electronic computer having a pipeline control structure. BTU・・・Bus interface unit, IDU・
...Instruction decoding unit, ATU...Address translation unit, EXU...Instruction execution unit, Ilo...Input/output device, PI...Instruction reading pipe, P2...Instruction decoding pipe, P3. ...Operand reading pipe, ■1~In...Instruction sequence.

Claims (1)

[Claims] (1) A memory and input/output device, a bus interface unit connected to this, an instruction decoder connected to this bus interface unit, and a connection between the output of this instruction decoder and the input of the bus interface unit. An electronic pipeline control structure comprising an inserted address translation unit, and an instruction execution unit connected to the output of the instruction decoding unit and the output of the bus interface unit, and further outputting an instruction execution result to the bus interface unit. In the computer, the address translation unit includes means capable of identifying at least an input/output instruction or an input/output space, and the bus interface unit identifies the input/output instruction when the bus access request received from the address translation unit is an input/output instruction. An electronic computer characterized by comprising means for accessing a bus in the order in which bus access requests arrive.