JPS6177968A - Controller of vector register - Google Patents

Abstract

PURPOSE:To eliminate the waste of time and to reduce the load of a program by allocating automatically a vector register in response to the dynamic situation. CONSTITUTION:The DR numbers designating the 1st-3rd operands are sent to a DR/VR converter circuit 30 from an instruction register 21 within a vector control unit 20 of a vector processor. The circuit 30 retrieves the numbers corresponding to the DR numbers and applies the DR numbers to write/read control circuits 50-53 corresponding to the VR groups respectively. Then the arithmetic result of the corresponding VR is written on a vector register 43. Here the contents of the DR indicating each operand are applied to an address generating circuit 41 from the circuit 30. Then a writing request is delivered to a main memory 42 with the address produced by the circuit 41. The circuit 30 is provided with a register group 70 which holds the vector data indicating information, a vector register directory 73, a replacement circuit 76, etc. Thus the data is held when no vector data exists, and the register 21 is automatically allocated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a vector processor, and more particularly to a vector register allocation mechanism.

[Background of the invention]

Generally speaking, vector processors reduce the number of times data is transferred to and from main memory by storing vector data of operation targets and operation results in all vector registers. However, as operations become more complex, the number of required vector registers increases, and a situation often arises in which the number of required vector registers becomes greater than the number of physically installed vector registers. The vector compiler tries to optimally allocate vector data to vector registers based on static analysis of statements, but it cannot accurately grasp the dynamic situation that changes as the operation progresses. ,
Truly efficient allocation cannot be expected.

For example, suppose we have the following sequence of instructions:

1) VRI←A (dinner) 2) VR2←B (4 heat 3) VR4←VR:lVR, 1 4) VR6←VR, 5+VR2 s) VR? ←C(★) The first instruction stores the vector A (+) in the vector register (
(hereinafter abbreviated as VR) 1, and the second instruction is an instruction to load into vector B(')t''VR2. The third instruction multiplies the contents of VR3 and VRI and returns the result. This is an instruction to be stored in VR,4, and the fourth instruction is V
Add the contents of R,5 and the contents of VR,2, and the result is iV
This is an instruction to store in R,6. Here, if there are only 6 VRs, and VR3 to VR6 are scheduled to be used in subsequent instructions, then in the fifth instruction the vector c(+)t
There are two candidates for the load destination (VR?) and shite, V[1 and VR,2, but which one is released first and can be reused is determined by multiple Arithmetic unit is parallel processing I! 'l! When doing so, it can only be determined at runtime. If vRl is randomly assigned to this, even if VR2 is actually released first, the execution of the fifth instruction will be delayed until VRI is released, resulting in wasted time.

[Purpose of the invention]

The purpose of the present invention is to prevent the above-mentioned wasted time by automatically allocating VRs according to dynamic situations, and also to eliminate the need for programs to consider the number of VRs and their allocation. It's about gold wire.

[Summary of the invention]

In the present invention, the vector registers are not placed first in the program instructions, and all the registers are allocated by the software. To this end, the allocation status of each vector register is stored in the vector register directory. is registered, and it is searched to check whether a vector register assigned to the vector data specified by the instruction exists. If it exists, the vector register group is accessed using the corresponding vector register number. death,
The vector register control device is configured such that if the vector register does not exist, the replacement circuit allocates a new vector register and registers the result in the vector register directory.

In an embodiment, an instruction may include a vector instruction register (DR in the embodiment) i that holds vector data instruction information.
By specifying, vector data can be indirectly specified, and also in the vector register directory, vector data assigned to each vector register can be indirectly specified by specifying the vector instruction register. can.

[Embodiments of the invention]

The embodiment described below uses one vector arithmetic unit and 16
This is for a vector processor with VRs. FIG. 2 shows a formant diagram of an instruction in this embodiment. The first byte of instruction 10 is an OP code that specifies the type of operation.

The second to fourth bytes are vector instruction registers (]) for the first to third operands, respectively.
iption R,egister (hereinafter abbreviated as DR)
These DRs hold information indicating the location of each operand on the main storage device. The first operand position is where the calculation result will be stored.9
, the second and third operand positions are where the data to be received by Xt is obtained.

It is assumed that 256 DRs are provided. As shown in FIG. 3, the contents of D R11 consist of four parts. "Data type" indicates the length of the vector element and the type of data (integer, floating point representation, etc.). The "start address" indicates the address of the first element of the vector in the main memory. The "increment value" indicates the address increment value of the main storage device between elements of the vector. Is "vector length" the relevant vector? Indicates the number of constituent elements. The contents of each Dr(11) are set by an appropriate group of instructions prior to the start of the operation.

FIG. 1 shows the overall configuration of a vector processor. The DR number specifying the first to third operands is sent from the instruction register 21 in the vector instruction control unit 2o to the DR-VRR conversion circuit 30 via the data blocks 22 to 24.
sent to. DR-VR transition circuit 30, these DR
, the VR number corresponding to the VII number for the first operand is provided to the first operand vR programmable control circuit 50 via the data line 55, and similarly, the VR number corresponding to the second operand and the third operand is provided. The VR number for reading is given to the second operand VR successive output restriction circuit 51 and the third operand VR read restriction circuit 52 via data lines 56 and 57.

The second and third operands are synchronously read element by element from the specified VR in the R details 43 under the control of the corresponding VR read control circuits 51 and 52,
The data is input to the arithmetic unit 44 via data edges 58 and 59. The calculation result is returned to the VR group 43 via the data line 60, and is sent to the first VR/DO VR.

The data is written to a predetermined VR under the control of the write control circuit 50.

For example, the operation when the second operand does not exist in the group 43 is as follows. First, DI'L
-V IL conversion circuit 30 is connected to the second
The contents of DR, which indicates the operand, are supplied to the address generation circuit 41. The address generation circuit 41 receives D
Based on the contents of R, addresses for each element of the vector are sequentially generated and read is requested to the main memory 42, and the main memory 42 transfers the read data to the VR group 43 via the data line 61. . Meanwhile, the DR-VRR conversion circuit 30 allocates one new VR to this read second operand, gives the V number to the VR read/write control circuit 53 via the data line 54, The vector data of the second operand read from the main storage device 42 is written into the VR. At the same time, this vl (number) is also given to the second operand/do R read control circuit 51, and the written second operand is supplied to the arithmetic unit 44 as is.

Even if the third operand does not exist in the VR group 43, the vector data (z, VR, read from the main storage device 42 is supplied to the arithmetic unit 44 via the group 43) in the same way.

If there is no VR assigned to the first controller, the DR-VRR conversion circuit 30 assigns a VR to it, and sends the VR number to the first controller via the data line 55.
The operand VFL is supplied to the write control circuit 50 and the corresponding V
Write the RKR calculation result. However, allocable Vr
When L decreases, the first operand is written not only to the VR but also to the main storage device 42. At this time, the DR-VRR conversion circuit 30 sends the contents of the DR indicating the first operand to the address generation circuit 41 via the data line 31, and the address generation circuit 41 generates the address of each element of the vector of the first operand. They are generated sequentially and requested to be written to the main storage device 42. At the same time, DIL
-VRR conversion circuit 30 converts the first operand v Ic'+
The VI' (No. 4i) given to the tr included jllll gift 11 circuit 50 is sent to the VR continuous output/write control circuit 53 via the data line 54.
The calculation results stored in the VIT are read out as they are, and transferred to the main storage device 42 via the data line 62.

The vector instruction unit 20, the address generation circuit 41, the main memory 42, the VR group 43, the arithmetic unit 44, and the control circuits 50 to 53 for reading and filling the VR may be conventional ones. Japanese Unexamined Patent Publication No. 58-114274 shows an example of this.

The configuration of the DR-VR father exchange circuit 30 is shown in FIG. The DR group 70 is a register group consisting of 256 DRIIs, and is specified by the outputs 22 to 24 of the instruction word register 21 (7) m2 to the fourth byte, that is, the DR of the @1 to third operands. The contents of DRII are read onto data lines 91-93, respectively. The Vl"t directory (hereinafter abbreviated as VR, D) 73 consists of 161 VR, D registers 94 that correspond one-to-one with each VR. Each VRDR register 94 has a corresponding one, as shown in Fig. In addition to the contents of the DRII (data type, data address, increment value, vector length) that identifies the vector data stored in the VR, the relevant number, validity flag,
Reusable flag and keep all. Among these, the validity flag is "0" if the corresponding VR is unused, and becomes "1" when valid data is stored. Further, the reusable flag is 1" if the corresponding VR can be reused (allocated), and 0" if it is not.

Comparing circuits 77 to 79 in FIG. This is for determining whether R exists or not.

These comparison circuits each include 16 comparators,
Via the data line 74, 16 V 14 from V 几D73
The DR scan code and validity flag in the D register 94 are received at the same time, and these 16 DR numbers are received when the instruction is first executed.
- Compare each in parallel with the Df1 number (data lines 22 to 24) specified for the third operand, and if there is a match, the result of that match.

A corresponding VR is generated based on the position of the comparator. And, is the validity flag in the VRD register set to "1"? The conditions include the VR, number, and a signal that indicates a match. , to data lines 95-97.

This coincidence signal controls the selection circuits 81 to 83,
The VR number is supplied to a corresponding one of the operand VR loading/reading control circuits 50-52 in FIG. 1 via data lines 55-57. In addition, when the presence of a VR assigned to the first operand is detected, data line 9
5, the reusable flag in the VR, D register 94 corresponding to the VR is set to "0" to prevent the VR from being reused before the calculation result to be written therein is read. . Further, when it is detected that the second and third operands are present on VR, data lines 96 and 97 are used to indicate the VR corresponding to the VFt.
Setting the reusable flag in the D register 94 to "1",
It is displayed that there is no problem even if the data is assigned to other vector data.

In the replacement circuit (hereinafter abbreviated as RPL) 76, any one of the first to third operands is VR.

If the VR has not been allocated, determine which VR should be allocated to it. For this purpose, RPL76:
Check the validity flag and reusable flag in each VR and D register 94 through the data line 75. First, search for the VR and D register whose validity flag is "0", and if there is one. Select. If there is no one whose validity flag is "0", one is selected from among those whose reusable flag is "1".

911 For example, a new assignment of VIL to the second operand is performed as follows. The DIR number that matches the DR number specified by the instruction for the second operand is
I? , D73 and the data line 96 from the 1 comparison circuit 78, the rtPL 76 sends the number of VR corresponding to the VrLD register selected by the above procedure to the vrt of FIG. 1 via the data line 54. Read/111 included d: Accepting vector data read from the main storage device 42 by supplying it to the ij direction 1 circuit 53 and supplying it from the selection circuit 82 to the second operand VR read control circuit 51 via the data line 56. Make four preparations. At the same time, It,I'L 76 controls selection circuit 84 to select the DR,11 that the instruction specified for the second operand.
The contents of (Figure 3) wo, from the data line 92 through the data line 31,
The main memory 4 is supplied to the address generation circuit 41 shown in FIG.
2. Perform all readings. The PL 76 further writes the contents of the DR (data line 31) and its DR fragrance into the VRD register 94 selected as described above, and sets its validity flag and reusable flag to "1". Make it.

The new assignment of VR to the third operand is the same as above, except that the determined VR, number is
57 instead of 156, and the third operand V11. The difference is that it is supplied to the readout side Φ1) circuit 52.

When a new VR is assigned to the first operand, the number of this assigned Jt Vl' (is transferred from the selection circuit 81 to the data line 55? to the first operand VR write control circuit 50. At the same time, the contents of DI (11) specifying the first operand are transferred from the data Ifi 191 to the VR, D register 94 corresponding to this VR.
1 and then written. At the same time, that VILD register 9
The validity flag in No. 4 is set to "1".

RPL76 is VIL whose original value of validity flag is “0”.
When assigned to the first operand i, the corresponding V I
Setting the reusable flag of the LD register 94 to "O" prevents the VR from being assigned to the pond vector data.In this case, the address generation circuit 41 of FIG.
And the VRk output/write 1 port 11 circuit 53 is not activated. This is because it is assumed that there are still enough VRs left that can be allocated. However, since there are no VRs whose validity flag is "0" remaining, the validity flag is 1", but the VR whose reusable flag is "1"
When assigned to the first operand, the corresponding VRD
The reusable flag of the register is left as "1", and the VIL number is sent to the corresponding VR read/write control circuit 53 via the data line 54, and the operation result written in that VR is immediately read out. and the corresponding DR.
The content of is sent to the address generation circuit 41 via the data line 31, and the calculation result (data line 62
) k, to be loaded into the main storage device 42. This measure eliminates the monopoly of VR by the first operand and enables allocation to other vector data as a countermeasure against the decrease in the number of Vr models that can be allocated, and also prepares for such reallocation. It is also intended to store the calculation results in the main storage device.

In this example, although there are only 16 VRs in reality, it appears as if 25 VRs exist in the program.
It can be regarded as if there were 6 VRs (the number of DR).

In the present invention, the number of arithmetic units is not limited to one, but a plurality of
i16 is also good. Rather, the advantages of the present invention are more effectively utilized when a plurality of arithmetic units perform all operations in parallel. Further, in the above embodiment, the VR can be reused immediately after being read once, but reuse may be prohibited until an arbitrarily specified number of readings are completed. To this end, for example, a read count designation field is provided in DRll, and a read count field is provided in place of the reusable flag in the VR and D registers 94.

The read count field of the vRD register is W'
Is it the value of the DR read count specification field at the beginning of guessing? After transcribing it, the number is decremented by 1 every time reading from the corresponding VR is performed, and the state where the first shift is "0" is 1l.
It is assumed that the reusable flag in the example is equivalent to 1''.

Furthermore, in the above embodiment, it is assumed that the contents of the DR are fixed during the execution of the program.
If it is possible to update to the contents of R, it is possible to process vector data on one or several bases of DIL. To do this, the search for VR, D73 is performed based on the contents of DI"t, rather than the bud number. For example, in FIG. , instead of the data lines 22-24, receive the data lines 91-93 which are the contents of the DI they point to, and
The other input cuff 4 may also receive the contents of the corresponding fields in the VR and D registers 94.

Furthermore, in the embodiments described above, vector data specification in an instruction is performed indirectly via DRe, and the DR group is a form in which the virtual R is numbered, so to speak.
Group 70 may be completely abolished, and the instruction may directly provide vector instruction information such as the start address, increment number, vector length, etc. of vector data. In this case, the comparison circuits 77 to 79 in FIG. Become.

〔Effect of the invention〕

According to the present invention, there is no need for the program creator to consider the specificity of VR as a physical structure or its allocation.
For example, even if the numerical aperture of VR is different, the program does not need to be changed. In addition, there is no wasted time, such as having to spend money on a pond's \r1( despite the existence of a reusable VI).

[Brief explanation of drawings]

FIG. 1 is a block diagram A of an embodiment of the present invention.
Figure 2 is a format diagram of the request, Figure 3 is a schematic diagram of the contents of DR, Figure 4 is a block diagram of the DR-vf' (conversion circuit) in Figure 1, and Figure 5 is a block diagram of the DR-vf' (conversion circuit) in Figure 4.
FIG. 11 is a schematic diagram of the contents of the ll and D registers. 21... Inquiry register, 30... DR-VI (conversion circuit, 42... Main tQ device, 43... Vector register (VR) group, 50-53... Writing to VRO /Read; till f1 circuit, 70...Register (DB) group for holding vector data instruction information, 73.
...Vector register directory, 7G...librace mate circuit.

Claims (1)

[Claims] 1. In a vector processor that has a plurality of vector registers and uses vector data on these vector registers as operands, a vector register directory that holds information indicating the allocation status of each vector register to vector data. and a circuit that searches this vector register directory to check whether a vector register assigned to the vector data specified by the instruction exists, and if it exists, outputs information indicating the vector register; A vector register control device comprising: a replacement circuit that allocates a vector register if it does not exist and registers the result in the vector register directory. 2. In claim 1, the designation of vector data in an instruction and the display of vector data to which a vector register is allocated in a vector register directory are performed by specifying a vector instruction register that holds vector data instruction information. A vector register control device characterized in that: