JPS6176968A - Screening testing device of semiconductor memory element - Google Patents

Screening testing device of semiconductor memory element

Info

Publication number
JPS6176968A
JPS6176968A JP59199771A JP19977184A JPS6176968A JP S6176968 A JPS6176968 A JP S6176968A JP 59199771 A JP59199771 A JP 59199771A JP 19977184 A JP19977184 A JP 19977184A JP S6176968 A JPS6176968 A JP S6176968A
Authority
JP
Japan
Prior art keywords
pin
refresh
semiconductor memory
memory element
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59199771A
Other languages
Japanese (ja)
Inventor
Kazunori Ishihara
和典 石原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59199771A priority Critical patent/JPS6176968A/en
Publication of JPS6176968A publication Critical patent/JPS6176968A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To execute effectively a screening test by using a line address input clock pin and a refresh pin of a semiconductor memory element having a self- refresh function. CONSTITUTION:A titled device is provided with a semiconductor memory element 1, a line address input clock pin RAS, a refresh pin REF, a power source supply line 3, signal lines 8, 9, etc. In this state, in case when the element 1 is a dynamic RAM having a self-refresh function, the potential of the pin RAS is set to a high level, and the potential of the pin REF is set to a low level, by which the element 1 executes a self-refresh operation. In this case, as for a voltage for setting the potential of the pin RAS to a high level, the same voltage as a power supply voltage in case when the element 1 is operated as an ordinary memory element can be applied, therefore, it is also possible that the signal line 8 is used in common with the supply line 3. Also, an energy of the element 1 is supplied through the signal line 8 from a power source 2, therefore, the test can be realized easily by an ordinary static burn-in device.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はスクリーニング試験を簡易な構成にて有効に達
成できる半導体メモリ素子スクリーニング試験装置に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device screening test apparatus that can effectively perform screening tests with a simple configuration.

〔従来の技術〕[Conventional technology]

半導体メモリの市場は拡大の一途をたどっているが、半
導体メモリには周知のように、初期故障と呼ばれる不良
形態が存在する。これは製造欠陥を含むメモリが使用開
始初期に劣化し不良となるものである、信頼性の高いメ
モリ製品を出荷するためには、出荷前にメモリをある程
度の時間動作させ、劣化すべきものは劣化させ製造欠陥
を含むメモリ、即ち潜在的な欠陥を有する製品を除去す
るというスクリーニング試験(Screening T
e5t)を実施する必要がある。このスクリーニング試
験のために半導体メモリ素子を動作させる方法としては
、通電するのみのスタチックバーンイン(Static
 Burn In)と、通電しクロック、アドレスを与
えるダイナミックバーンイン (DynamicBur
n In)とがある。
Although the semiconductor memory market continues to expand, as is well known, semiconductor memories have a type of failure called early failure. This is because memory that contains manufacturing defects deteriorates and becomes defective in the early stages of use.In order to ship highly reliable memory products, it is necessary to operate the memory for a certain period of time before shipping, and to ensure that the memory that should deteriorate deteriorates. Screening T
e5t) must be implemented. As a method of operating a semiconductor memory device for this screening test, static burn-in (static burn-in) in which only electricity is applied is used.
Dynamic burn-in (Burn In) and dynamic burn-in (Dynamic Bur
n In).

第2図は従来のスタチックバーンイン装置の構成を示す
ブロック図で、図において(1)はスクリーニング試験
を受ける半導体メモリ素子であり、(2)は該半導体メ
モリ素子(1)に電気エネルギーを供給する電源、(3
)は該電源(2)から半導体メモリ素子(1)への電気
エネルギーの通路としての電源供給線である。
FIG. 2 is a block diagram showing the configuration of a conventional static burn-in device. In the figure, (1) is a semiconductor memory element undergoing a screening test, and (2) is a block diagram that supplies electrical energy to the semiconductor memory element (1). power supply, (3
) is a power supply line serving as a path for electrical energy from the power source (2) to the semiconductor memory element (1).

また、第3図は従来のダイナミックバ−ンイン装置の構
成を示すブロック図で、同図において上記第2図と同一
符号は同一構成部分を示し、この説明は省略する。(4
)はクロック発生回路、(5)はクロック信号線、(6
)はアドレス発生回路、(7)はアドレス信号線である
Further, FIG. 3 is a block diagram showing the configuration of a conventional dynamic burn-in device. In this figure, the same reference numerals as in FIG. 2 indicate the same components, and a description thereof will be omitted. (4
) is a clock generation circuit, (5) is a clock signal line, (6
) is an address generation circuit, and (7) is an address signal line.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

一般にメモリ素子の場合、外部からクロックもしくはア
ドレスを与えることによって初めて内部回路全体に電圧
が印加されるようになっているものが多い。上記メモリ
素子の効果的なスクリーニング試験を実施するためには
、第3図に示すダイナミンクバーンイン装置を使う必要
がある。
Generally, in the case of memory devices, voltage is often applied to the entire internal circuit only when a clock or address is applied from the outside. In order to carry out an effective screening test for the above-mentioned memory devices, it is necessary to use a dynamic burn-in apparatus as shown in FIG.

以上のような理由からスクリーニング試験にはダイナミ
ックバーンイン装置が多用されているが、ダイナミック
バーンイン装置にはクロック発生回路やアドレス発生回
路が必要となるため装置の構成が複雑化し、また装置自
体の価格が高くなるという欠点があった。
For the above reasons, dynamic burn-in equipment is often used in screening tests, but dynamic burn-in equipment requires clock generation circuits and address generation circuits, which complicates the equipment configuration and increases the cost of the equipment itself. The drawback was that it was expensive.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は上記点に鑑みてなされたもので、セルフリフレ
ッシュ機能を有する半導体メモリ素子に行アドレス取込
みクロックピンとリフレッシュピンとを設け、上記行ア
ドレス取込みクロックピン及びリフレッシュピンに各々
電圧を印加し、行アドレス取込みクロックピンが高レベ
ルとなリリフレ・ンシュピンが低レベルとなったとき上
記半導体メモリ素子のセルフリフレッシュ機能が動作し
、該動作中に外部電圧を印加するのみでスクリーニング
試験を行なう構成とされる。
The present invention has been made in view of the above points, and a semiconductor memory element having a self-refresh function is provided with a row address capture clock pin and a refresh pin, voltages are applied to the row address capture clock pin and refresh pin, respectively, and the row address When the take-in clock pin is at a high level and the refresh pin is at a low level, the self-refresh function of the semiconductor memory element operates, and a screening test is performed by simply applying an external voltage during this operation.

[作用] この発明においては、行アドレス取込みクロックピンと
リフレッシュピンとの電位差に基づき外部制御信号によ
る半導体メモリ素子の制御動作とセルフリフレッシュ機
能の動作とを切換え、該セルフリフレッシュ機能の動作
中に外部電圧の印加のみでスクリーニング試験を行なう
ことができることとなり、簡易な構成且つ安価なスタチ
ックバーンイン装置でアドレスを指定することにより逐
次メモリセルのスクリーニング試験ができるダイナミッ
クバーンイン装置と同様に効果的なスクリーニング試験
が可能となる。
[Function] In the present invention, the control operation of the semiconductor memory element by an external control signal and the operation of the self-refresh function are switched based on the potential difference between the row address capture clock pin and the refresh pin, and the external voltage is switched during the operation of the self-refresh function. Screening tests can be performed by simply applying voltage, making it possible to perform screening tests as effectively as dynamic burn-in equipment, which can sequentially perform screening tests on memory cells by specifying addresses using static burn-in equipment, which has a simple configuration and is inexpensive. becomes.

〔実施例〕〔Example〕

以下、第1図に基づき本発明の一実施例に係る半導体メ
モリ素子のスクリーニング試験装置を説明する。上記第
1図に本実施例に係る半導体メモリ素子のスクリーニン
グ試験装置の構成ブロックと同一符号は同−又は相当部
分であり、この説明は省略する。上記第1図において、
 (RAS) (RowAdress  5trobe
)は半導体メモリ素子(1)のメモリセルを逐次指定す
る行アドレス取込みクロックピン、(REF)(Rif
resh)はメモリセルを再活性するりフレンシュピン
、(8)は上記行アドレス取込みクロックピン(RAS
)に高レベルの電位を印加する信号線、(9)はリフレ
ッシュピン(REF)に低レベルの電位を印加すると共
に一端を接地される信号線である。なお、上記半導体メ
モリ素子(1)は、一般にダイナミックRAM (Ra
ndom Access Memory)にて構成され
、現在市販されているダイナミックRAM 17)中に
は、セルフリフ1/−/シ、 (Seif Refre
sh)と呼ばれる機能を有するものがあり、電源電圧を
印加した状態で入力ピンに所定の関係で電圧を印加する
とダイナミックRAMに内蔵されたタイマにより自動的
に12〜18g5ごとに行アドレスがリフレッシュされ
、2msですべてのメモリセルがリフレッシュされるも
のがある。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A screening test apparatus for semiconductor memory devices according to an embodiment of the present invention will be described below with reference to FIG. The same reference numerals as the constituent blocks of the semiconductor memory device screening test apparatus according to the present embodiment in FIG. In Figure 1 above,
(RAS) (RowAddress 5trobe
) is a row address capture clock pin, (REF) (Rif
(8) is the row address capture clock pin (RAS) that reactivates the memory cell.
) is a signal line that applies a high level potential to the refresh pin (REF), and (9) is a signal line that applies a low level potential to the refresh pin (REF) and has one end grounded. Note that the semiconductor memory element (1) is generally a dynamic RAM (Ra
Among the dynamic RAMs currently on the market17) are self-ref1/-/shi,
There is a function called "sh)", and when a voltage is applied to the input pin in a predetermined relationship while the power supply voltage is applied, the row address is automatically refreshed every 12 to 18g5 by a timer built in the dynamic RAM. , all memory cells are refreshed in 2 ms.

次に、上記構成に基づく本実施例の動作について説明す
る。まず、半導体メモリ素子(1)がセルフリフレジツ
ユ機能を有するダイナミックRAMである場合において
、行アドレス取込みクロックピン(RAS)の電位を高
レベルとし、リフレッシュピン(REF)の電位を低レ
ベルとなることにより上記半導体メモリ素子(1)はセ
ルフリフレッシュ動作を行なう。ここで、行アドレス取
込みクロックピン(RAS)の電位を高レベルとする電
圧は、半導体メモリ素子(1)が通常のメモリ素子とし
て動作する場合の電#i電圧と同じ電圧を印加すること
ができるため信号線(8)を電源供給線(3)と共用す
ることも可能である。さらに、上記半導体メモリ素子(
1)のセルフリフレッシュ動作はその動作エネルギーを
電源(2)より信号線(8)を通して供給されて行なわ
れる。
Next, the operation of this embodiment based on the above configuration will be explained. First, when the semiconductor memory element (1) is a dynamic RAM having a self-refresh function, the potential of the row address capture clock pin (RAS) is set to a high level, and the potential of the refresh pin (REF) is set to a low level. As a result, the semiconductor memory element (1) performs a self-refresh operation. Here, the voltage that sets the potential of the row address capture clock pin (RAS) to a high level can be the same voltage as the voltage #i when the semiconductor memory element (1) operates as a normal memory element. Therefore, it is also possible to share the signal line (8) with the power supply line (3). Furthermore, the semiconductor memory element (
The self-refresh operation 1) is performed by supplying operating energy from the power supply (2) through the signal line (8).

したがって、第1図に係る本実施例の構成は通常のスタ
チックバーンイン装置で容易に実現出来る。本実施例の
構成の場合、通常のダイナミックバーンインがIJL5
〜10g5程度のサイクルタイムで動作させるのに対し
、12g5〜1B4sと若干サイクルタイムが長くなる
が、スクリーニング試験の効果としては略同様の効果が
得られる。
Therefore, the configuration of this embodiment shown in FIG. 1 can be easily realized with a normal static burn-in device. In the case of the configuration of this embodiment, normal dynamic burn-in is
Although the cycle time is slightly longer at 12g5 to 1B4s compared to the cycle time of approximately 10g5, approximately the same effect as that of the screening test can be obtained.

〔発明の効果〕〔Effect of the invention〕

セルフリフレッシュ機能を有する半導体メモリ素子に行
アドレス取込みクロックビンとリフレッシュピンとを設
け、上記行アドレス取込みクロックピン及びリフレッシ
ュピンに各々電圧を印加し1行アドレス取込みクロック
ビンが高レベルとなりリフレッシュピンが低レベルとな
ったとき上記半導体メモリ素子のセルフリフレッシュ機
能が動作し、該動作中に外部電圧を印加するのみでスク
リーニング試験を行なう構成とを採ったことから、行ア
ドレス取込みクロックビンとリフレッシュピンとの電位
差に基づき外部制御信号による半導体メモリ素子の制御
動作とセルフリフレッシュ機能の動作とを切換え、該セ
ルフリフレッシュ機能の動作中に外部電圧の印加のみで
スクリーニング試験を行なうことができることとなり、
簡易な構成且つ安価なスタチックバーンイン装置でアド
レスを指定することにより逐次メモリセルのスクリーニ
ング試験ができるダイナミックバーンイン装置と同様に
効果的なスクリーニング試験が可能となる効果を奏する
A semiconductor memory element having a self-refresh function is provided with a row address capture clock bin and a refresh pin, and voltages are applied to the row address capture clock pin and refresh pin, respectively, so that the first row address capture clock bin is at a high level and the refresh pin is at a low level. The self-refresh function of the semiconductor memory element operates when Based on this, it is possible to switch between the control operation of the semiconductor memory element using an external control signal and the operation of the self-refresh function, and perform a screening test only by applying an external voltage while the self-refresh function is in operation.
By specifying addresses using a simple and inexpensive static burn-in device, an effective screening test can be performed in the same way as a dynamic burn-in device that can sequentially perform a screening test on memory cells.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例に係る半導体メモリ素子のス
クリーニング試験装置の構成ブロック図、第2図は従来
のスクリーニング試験を行なうスタチックバーンイン装
置の構成ブロック図、第3図は従来のダイナミックバー
ンイン装置の構成ブロフク図を示す。 図において、(1)は半導体メモリ素子、(2)は電源
、 (3)は電源供給線、 (8)、(9)は信号線、 (RAS)は行アドレス取込みクロックビン、(REF
)はりフレンシュビンである。
FIG. 1 is a block diagram of the configuration of a screening test device for semiconductor memory devices according to an embodiment of the present invention, FIG. 2 is a block diagram of a static burn-in device for performing conventional screening tests, and FIG. 3 is a block diagram of a conventional dynamic burn-in device. The block diagram of a burn-in device is shown. In the figure, (1) is a semiconductor memory element, (2) is a power supply, (3) is a power supply line, (8) and (9) are signal lines, (RAS) is a row address capture clock bin, (REF
) The beam is Frenshbin.

Claims (1)

【特許請求の範囲】[Claims] セルフリフレッシュ機能を有する半導体メモリ素子に行
アドレス取込みクロックピンとリフレッシュピンとを設
け、上記行アドレス取込みクロックピン及びリフレッシ
ュピンに各々電圧を印加し、行アドレス取込みクロック
ピンが高レベルとなりリフレッシュピンが低レベルとな
ったとき上記半導体メモリ素子のセルフリフレッシュ機
能が動作し、該動作中に外部電圧を印加するのみでスク
リーニング試験を行なう構成としたことを特徴とする半
導体メモリ素子のスクリーニング試験装置。
A semiconductor memory element having a self-refresh function is provided with a row address capture clock pin and a refresh pin, and voltages are applied to the row address capture clock pin and refresh pin, respectively, so that the row address capture clock pin becomes high level and the refresh pin becomes low level. 1. A screening test apparatus for a semiconductor memory device, characterized in that when the self-refresh function of the semiconductor memory device is activated, a screening test is performed by simply applying an external voltage during the operation.
JP59199771A 1984-09-25 1984-09-25 Screening testing device of semiconductor memory element Pending JPS6176968A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59199771A JPS6176968A (en) 1984-09-25 1984-09-25 Screening testing device of semiconductor memory element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59199771A JPS6176968A (en) 1984-09-25 1984-09-25 Screening testing device of semiconductor memory element

Publications (1)

Publication Number Publication Date
JPS6176968A true JPS6176968A (en) 1986-04-19

Family

ID=16413338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59199771A Pending JPS6176968A (en) 1984-09-25 1984-09-25 Screening testing device of semiconductor memory element

Country Status (1)

Country Link
JP (1) JPS6176968A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0456255A2 (en) * 1990-05-11 1991-11-13 Kabushiki Kaisha Toshiba Dynamic memory device and method for screening the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0456255A2 (en) * 1990-05-11 1991-11-13 Kabushiki Kaisha Toshiba Dynamic memory device and method for screening the same
JPH0417349A (en) * 1990-05-11 1992-01-22 Toshiba Corp Dynamic memory device and burn-in method therefor
US5343430A (en) * 1990-05-11 1994-08-30 Kabushiki Kaisha Toshiba Method and circuitry for screening a dynamic memory device for defective circuits

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