JPS61766A - Wiring testing method and apparatus for circuit substrate - Google Patents

Wiring testing method and apparatus for circuit substrate

Info

Publication number
JPS61766A
JPS61766A JP59121402A JP12140284A JPS61766A JP S61766 A JPS61766 A JP S61766A JP 59121402 A JP59121402 A JP 59121402A JP 12140284 A JP12140284 A JP 12140284A JP S61766 A JPS61766 A JP S61766A
Authority
JP
Japan
Prior art keywords
information
circuit board
wiring
section
measurement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59121402A
Other languages
Japanese (ja)
Other versions
JPH0426435B2 (en
Inventor
Fumihiro Hoshiai
星合 文広
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59121402A priority Critical patent/JPS61766A/en
Publication of JPS61766A publication Critical patent/JPS61766A/en
Publication of JPH0426435B2 publication Critical patent/JPH0426435B2/ja
Granted legal-status Critical Current

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

PURPOSE:To perform a highly reliable wiring test eliminating the manufacture of mask plates for individual substrates, by selecting information position on an array lattice of a measuring probe from N/C boring information for a circuit board to turn ON a switch corresponding thereto. CONSTITUTION:A circuit board 20 to be inspected is positioned and mounted on a support 10 having a measuring probe 11 arrayed in a lattice through a pilot pin 12. Coordinates 6 of boring information with Z1 as origin are inputted into a calculating section 3 through an information reading mechanism 4 to determine coordinates of those for boring with respect to a probe array lattice by coordinate conversion from origin movements DELTAX and DELTAY between the origins Z2 and Z1 of the array lattice of the measuring probe 11 inputted from a keyboard section 5 and additionally, the results are converted into address for a switch group 1. The switch alone corresponding to the specified address from the switch group 1 is turned ON through a control section 2 to perform a wiring test with a measuring section 40. This eliminates the manufacture of mask plates for individual substrates thereby enabling a highly reliable wiring test.

Description

【発明の詳細な説明】 (技術分野) 本発明は回路基板のパターンにおける回路断線。[Detailed description of the invention] (Technical field) The present invention relates to circuit disconnection in a circuit board pattern.

回路間ブリッジを電気的に検査する布線試験方法および
その装置に関するものである。
The present invention relates to a wiring test method and apparatus for electrically testing inter-circuit bridges.

(従来技術) 従来、この種の布線試験は測定プローブ支持板上に一定
ピッチで格子状に配置した測定プローブ群を有する布線
試験装置を用いており、被検査回路基板と測定プローブ
群との間に被検査回路基板の検査必要個所にのみ測定プ
ローブを通過する孔を有する絶縁板を介在させ、必要な
測定プローブを選択することにより布線試験を実施して
いた。
(Prior art) Conventionally, this type of wiring test has used a wiring test device that has a group of measurement probes arranged in a grid pattern at a constant pitch on a measurement probe support plate. During the wiring test, an insulating plate having a hole through which the measurement probe passes is interposed only at the part of the circuit board to be tested that needs to be inspected, and the necessary measurement probe is selected.

第1図は従来方式の1例であり、特開昭53−6879
号公報にて開示されたものである。測定プローブ11は
絶縁性を有する測定プローブ支持板lO上に一定ピッチ
で格子状に配置されており、このピッチは通常検査対象
となる回路基板の設計基準に従って2.54mm、12
7mm等のピッチが採用される。被検査回路基板(以後
基板と略称)20と測定プローブ支持板(以後支持板と
略称)1゜との間にはガラスエポキシ樹脂等の絶縁材料
の板罠基板20の検査個所となるスルホール21に相当
する位置罠孔明けしたマスクプレート3(l介在させる
。この状態で基板2oの布線試験を行うには、基板2o
とマスクプレート3oをそれぞれ支持板10の板面に対
向し、かつ測定プローブ11の配置した格子と基板2o
のスルホール21の設計格子およびマスクプレー)30
の逃げ孔31の設計格子が相互に水平状態で、がり等間
隔に一致するように支持板lo上に植立させたパイロッ
トビン12に基板2o、マスクプレー)30の両ガイド
孔20a、30aを嵌合して位置決め装着する。次に基
板2oと支持板1oとを公知の加圧手段により押圧して
近接させると、マスクプレート30の逃げ孔31のある
個所から測定プローブ11が貫挿し、突出状態で基板2
oの検査必要個所にあるスルホール21と接触する。従
って電気的に検査可能状態となるため、測定プローブ1
1の下端と配線(図示省略)を介して接続された布線試
験機の測定部40により検査必要個所のみの布線試験を
行なっている。このような従来の布線試験方法では、 (イ)基板のパターンが異なるごとにそのパター7に合
せて孔あけしたマスクプレートを製作する必要がある。
Figure 1 shows an example of the conventional method, published in Japanese Unexamined Patent Publication No. 53-6879.
This was disclosed in the No. The measurement probes 11 are arranged in a grid pattern at a constant pitch on an insulating measurement probe support plate lO, and the pitch is usually 2.54 mm, 12 mm, according to the design standard of the circuit board to be inspected.
A pitch such as 7 mm is adopted. Between the circuit board to be tested (hereinafter referred to as the board) 20 and the measurement probe support plate (hereinafter referred to as the support plate) 1°, there are through holes 21 that serve as inspection points in the plate trap board 20 made of an insulating material such as glass epoxy resin. Interpose a mask plate 3 (l) with trap holes at corresponding positions.In order to perform a wiring test on the board 2o in this state, the board 2o
and a mask plate 3o respectively facing the plate surface of the support plate 10, and a grating and a substrate 2o on which the measurement probe 11 is arranged.
Design grid of through holes 21 and mask plate) 30
Both guide holes 20a, 30a of the substrate 2o and mask plate 30 are installed on the pilot bottle 12, which is set up on the support plate lo, so that the design grids of the relief holes 31 are horizontal to each other and the lattices are equally spaced. Fit, position and install. Next, when the substrate 2o and the support plate 1o are pressed by a known pressure means and brought close to each other, the measurement probe 11 penetrates through the relief hole 31 of the mask plate 30, and protrudes from the substrate 2o.
It comes into contact with the through hole 21 at the location where inspection is required. Therefore, the measurement probe 1 becomes electrically testable.
A wiring test is performed only on the portions that require inspection using a measuring section 40 of a wiring testing machine connected to the lower end of the wiring board 1 via wiring (not shown). In such a conventional wiring test method, (a) it is necessary to manufacture a mask plate with holes drilled to match the putter 7 for each different pattern of the board;

そのため製作コストがかかり、かつ準備工数も必要とし
た。
Therefore, the production cost was high and preparation time was also required.

(ロ)マスクプレートは通常基板のN/C孔あけ情報を
そのit用いて製作するので、測定プローブの配列格子
からはずれた個所にも孔あけされることがあり、誤検出
の原因となり易かった。
(b) Since the mask plate is usually manufactured using the N/C hole drilling information of the board, holes may be drilled in locations that are outside the array grid of the measurement probes, which is likely to cause false detection. .

(ハ)またマスクプレートは通常、薄い絶縁板で作られ
るので、耐久性に乏しく、長く使用していると位置決め
精度が劣化して測定プローブがマスクブレニドの逃は孔
i正しく貫挿しなくなるため、測定プローブと基板のス
ルホール間に接触不良が生じて布線試験の信頼性を低下
させていた。
(c) Also, since the mask plate is usually made of a thin insulating plate, it has poor durability, and if used for a long time, the positioning accuracy will deteriorate and the measurement probe will not be able to correctly penetrate the hole in the mask blend. Poor contact occurred between the probe and the through-hole of the board, reducing the reliability of wiring tests.

(目的) 本発明の目的はかかる従来欠点を解決した基板の布線試
験方法およびその装置を提供することにある。
(Objective) An object of the present invention is to provide a wiring testing method for a board and an apparatus therefor which solves the conventional drawbacks.

(構成) 本発明によれば、回路基板のN/C孔あけ情報を入力し
、その情報を所定の移動量だけ移動する工程と、さらに
移動した情報から布線試験機の測定プローブの配置格子
上に位置する情報のみを選択し、前記測定プローブと布
線試験機との間に配設した測定フローツに対応するスイ
ッチのアドレスに変換する工程と、上記アドレスに対応
したスイッチのみをONにする工程とを含む回路基板の
布線試験方法および、回路基板のN/C孔あけ情報を読
取る情報読取り機構と、上記情報読取り機構と接続され
キーボード入力部を有する計算部と、回路基板の被検査
部と接触する測定プローブと布線試験機測定部の間に設
け、かつ前記計算部と接続された制御部により個々にO
N/OFF される前記測定プローブに対応したスイッ
チ群とを有することを特徴とする回路基板の布線試験装
置が得られる。
(Structure) According to the present invention, there is a step of inputting N/C drilling information of a circuit board, moving the information by a predetermined amount of movement, and using the moved information as a layout grid for measuring probes of a wiring tester. A step of selecting only the information located above and converting it into the address of the switch corresponding to the measurement float placed between the measurement probe and the wiring tester, and turning ON only the switch corresponding to the above address. an information reading mechanism for reading N/C drilling information on a circuit board; a calculating section connected to the information reading mechanism and having a keyboard input section; and a circuit board to be tested. The controller is installed between the measurement probe that contacts the measurement section of the wiring tester and the measurement section of the wiring tester, and is connected to the calculation section.
There is obtained a circuit board wiring testing device characterized in that it has a switch group corresponding to the measurement probe that is turned on and off.

(実施例) 以下、本発明の実施例を第2図および第3図(a)。(Example) Examples of the present invention are shown in FIGS. 2 and 3(a) below.

(bl 、 (C1を参照して説明する。(bl , (Explained with reference to C1.

第2図において、従来例と同様に測定プローブ11は絶
縁性を有する支持板10上に2.54 mm、 1.2
7mm等の一定ビッテで格子状に配置されており、基板
20はスルホール21の設計格子と測定プローブ11の
配黄格子とが相互に水平状態で、かつ等間隔に一致する
ように支持板1oの一辺に植立させたパイロットピノ1
2に基板20.マスクプレート30の両ガイド孔2oa
、3oat嵌合して支持板10上に位置決め装着される
。次にスイッチ群1は通常半導体スイッチで構成されて
おり、布線試験機の測定部40と測定プローブ11の一
端と?接続する配線(図示省略)の中間にそれぞれの測
定プローブ11に対応して測定プローブ11の数だけ接
続され、アドレスデコーダ等の論理回路で構成される制
御部2の指示により指定されたアドレスのスイッチをO
N/OFF することにょ秒、指定された位置の測定プ
ローブ11と対応する測定部40の測定回路(通常半導
体スイッチより構成される)との接続を制御できる。
In FIG. 2, similarly to the conventional example, the measurement probe 11 is placed on an insulating support plate 10 with a distance of 2.54 mm and 1.2 mm.
The substrate 20 is arranged in a grid pattern with a constant bit size of 7 mm, etc., and the substrate 20 is arranged on the support plate 1o so that the design grid of the through holes 21 and the yellow grid of the measurement probe 11 are in a horizontal state and coincide with each other at equal intervals. Pilot Pino 1 planted on one side
2 to the substrate 20. Both guide holes 2oa of mask plate 30
, 3oat fit and are positioned and mounted on the support plate 10. Next, the switch group 1 is usually composed of semiconductor switches, and is connected to the measuring section 40 of the wiring tester and one end of the measuring probe 11. A switch corresponding to the number of measurement probes 11 is connected to the middle of the wiring (not shown) to be connected, corresponding to each measurement probe 11, and has an address designated by an instruction from the control unit 2, which is constituted by a logic circuit such as an address decoder. O
By turning N/OFF, the connection between the measuring probe 11 at the designated position and the measuring circuit (usually composed of a semiconductor switch) of the corresponding measuring section 40 can be controlled.

マイクロコアピユータ等で構成される計算部3は情報読
取り機構4t−介して入力したXX座標形式の基板20
のN/C孔あけ情報6をキーボード部5よりあらかじめ
入力したパラメータにより計算し、スイッチ群lのアド
レスに変換して制御部2へ送り込む機能を有している。
The calculation unit 3 composed of a micro core computer etc. receives information from the board 20 in XX coordinate format input through the information reading mechanism 4t.
It has a function of calculating the N/C drilling information 6 from the parameters inputted in advance from the keyboard section 5, converting it into an address of the switch group 1, and sending it to the control section 2.

次に本発明による布線試験の動作工程を第3図(a)伽
)(C)にて説明する。
Next, the operating steps of the wiring test according to the present invention will be explained with reference to FIGS. 3(a) and 3(c).

第3図(blは第2図の基板20の外形Aと測定プロー
ブ11の配置格子Bとの関係を示した説明図であり、座
標点P1〜P、は基板20の外に設けた基準点z1を原
点とする基板20のXX座標値形式(mm単位)のN/
C孔あけ情報で、第2図のN/C孔あけ情報6の7部を
示したものである。
FIG. 3 (bl is an explanatory diagram showing the relationship between the outline A of the substrate 20 in FIG. 2 and the arrangement grid B of the measurement probe 11, and coordinate points P1 to P are reference points provided outside the substrate 20. N/ of the XX coordinate value format (mm unit) of the board 20 with z1 as the origin
This is the C drilling information, which shows part 7 of the N/C drilling information 6 in FIG.

ΔX、ΔYは前述のN/C孔あけ情報の原点Z1と測定
プローブ11の配置格子Bの原点Z2との間のそれぞれ
X、Y方向の距離であり、基板20を支持板10上に位
置決めする時に一意的に決まる値である。
ΔX and ΔY are the distances in the X and Y directions, respectively, between the origin Z1 of the N/C drilling information described above and the origin Z2 of the arrangement grid B of the measurement probe 11, and are used to position the substrate 20 on the support plate 10. It is a value that is uniquely determined.

第3図(a)のフローチャートによると、まずキーボー
ド部5より前述の原点移動量ΔX ΔYt−人力し情報
読取り機構4で読取った基板20のN/C孔あけ情報6
に対して計算部3によりそれぞれX座標、X座標に対し
て原点移動を行うと、例えば第3図(blで示すN/C
孔あけ情報の座標点P1〜P5は配置格子Bの原点Z2
を原点とする情報に変換される。次に計算部3により前
述の原点移動された情報をそれぞれX座標、Y座標共測
定プローブ11の配置格子ピッチ(通常Z54mm等)
で除し、割り切れるもののみ選択すると、例えば第3図
(b)の孔あけ情報の座標点P□〜P5の中でP4は配
置格子Bの交点上に無いため除外され、座標点P1(X
l、Yo)はPI(2,2)のように格子座標系に変換
される。さらに配置格子Bの格子点はそれぞれスイッチ
群1のアドレスに一対一で対応しているので格子座標系
に変換された孔あけ情報は計算部3によりスイッチ群1
のアドレスに変換する。この変換は例えばスイッチ群l
のアドレスが連続していれば計算式により計算して変換
し、断続していれば計算部3の記憶部(図示省略)に対
応表をあらかじめ記憶させその対応表を参照して変換す
ればよい。次の第3図(C)は第3図(b)のN/C孔
あけ情報の座標点P□〜P5がスイッチ群1のアドレス
a□〜a5に変換されたことを示す説明図である。スイ
ッチ群1のアドレスに変換された情報は計算部3から制
御部2に送られ、スイッチ群1の中で指定されたアドレ
スのみをONにする。なお、基板20の端子部22に対
しては、(通常端子部にはN/C孔あけ情報がないので
)あらかじめ端子部22に接触する位置の測定プローブ
llK対応するスイッチのアドレスをスイッチ群1の中
から選択し、キーボード部5より直接入力して、上記の
スイッチをONにすればよい。
According to the flowchart of FIG. 3(a), first, the above-mentioned origin movement amount ΔX ΔYt--the N/C drilling information 6 of the board 20 read by the information reading mechanism 4 from the keyboard section 5
For example, when the calculation unit 3 moves the origin to the X coordinate and the
The coordinate points P1 to P5 of the drilling information are the origin Z2 of the arrangement grid B
is converted into information with the origin as the origin. Next, the calculation unit 3 converts the above-mentioned origin-shifted information into the X and Y coordinates and the arrangement grid pitch of the measurement probe 11 (usually Z54 mm, etc.).
If we select only those that are divisible by dividing by
l, Yo) is transformed into a grid coordinate system like PI(2,2). Furthermore, since each grid point of the layout grid B has a one-to-one correspondence with the address of the switch group 1, the drilling information converted to the grid coordinate system is sent to the calculation unit 3 by the calculation unit 3 of the switch group 1.
Convert to address. For example, this conversion is performed by switch group l
If the addresses are consecutive, they can be calculated and converted using a calculation formula, and if they are intermittent, a correspondence table can be stored in advance in the storage unit (not shown) of the calculation unit 3, and the conversion can be performed by referring to the correspondence table. . The following FIG. 3(C) is an explanatory diagram showing that the coordinate points P□ to P5 of the N/C drilling information in FIG. 3(b) have been converted to addresses a□ to a5 of switch group 1. . The information converted into the address of the switch group 1 is sent from the calculation section 3 to the control section 2, and only the specified address in the switch group 1 is turned on. Note that for the terminal section 22 of the board 20, the address of the switch corresponding to the measurement probe llK at the position where it contacts the terminal section 22 is set in advance in switch group 1 (because the terminal section usually does not have N/C hole drilling information). All you have to do is select one from among them, input it directly from the keyboard section 5, and turn on the above switch.

例えば第3図(C1に示すアドレスb1〜b6は端子部
22に対応するスイッチのアドレスを示す。
For example, addresses b1 to b6 shown in FIG. 3 (C1) indicate the addresses of the switches corresponding to the terminal section 22.

以上の操作により、基板20を支持板10上に位置決め
したときのスルホール21の位置および端子部22の位
置に接触すべき測定プローブ11に対応するスイッチの
みがONされるので、布線試験機の測定部40から見て
基板20の検査必要個所のみに対応する支持板10が形
成されたのと同じとなり、従来例のようにマスクプレー
ト30を介在させた場合と同一の効果をもたらす。従っ
て以後従来例と同様に基板20を支持板10に位置決め
装着し、測定プローブ11と基板20の検査必要個所を
公知の加圧手段により押圧して接触させ、測定部40に
より検査必要個所のみの布線試験が行える。
By the above operation, only the switches corresponding to the measurement probes 11 that should come into contact with the positions of the through holes 21 and the positions of the terminals 22 when the board 20 is positioned on the support plate 10 are turned on. This is equivalent to forming the support plate 10 corresponding only to the portions of the substrate 20 that require inspection when viewed from the measurement unit 40, and the same effect as in the case where the mask plate 30 is interposed as in the conventional example is brought about. Therefore, from now on, the board 20 is positioned and mounted on the support plate 10 in the same way as in the conventional example, and the measuring probe 11 and the part of the board 20 that need to be inspected are pressed and brought into contact with each other using a known pressure means, and the measurement part 40 is used to check only the part that needs to be inspected. Can perform wiring tests.

なお、本実施例ではスイッチ群1は測定部40と独立し
て設置しているが、通常測定部40は電圧を基板に印加
するだめの半導体スイッチから構成されているがスイッ
チの機種によってはON/OFF制御の有効、無効が指
定できるものもおる。
In this embodiment, the switch group 1 is installed independently of the measuring section 40, but normally the measuring section 40 is composed of semiconductor switches that apply voltage to the board, but depending on the switch model, it may be turned on or off. Some models allow you to specify whether /OFF control is enabled or disabled.

この場合、制御部2の指示信号をこれら有効、無効の指
定に用いるように制御部2と測定部40を接続すれば検
査必要個所に対応する測定部40のスイッチのみを有効
にする操作ができ、スイッチ群1を省略することもでき
る。
In this case, if the control section 2 and the measurement section 40 are connected so that the instruction signal from the control section 2 is used to designate whether these are enabled or disabled, it is possible to enable only the switch of the measurement section 40 corresponding to the location that requires inspection. , the switch group 1 can also be omitted.

(効果) 以上、本発明の布線試験方法およびその装置を用いるこ
とにより、゛ (イ)従来のように個々の基板に対してマスクプレート
を製作する必要がない。そのためマスクプレート製作お
よび交換工数を省略することができる。
(Effects) As described above, by using the wiring testing method and apparatus of the present invention, (a) there is no need to manufacture mask plates for each individual substrate as in the past. Therefore, the man-hours for manufacturing and replacing mask plates can be omitted.

(ロ)基板の検査必要個所の選択はすべて入力情報によ
り行われるため、マスクプレートの位置ずれによる接触
不良は皆無となる。
(b) Since the selection of the parts of the board that require inspection is done entirely based on input information, there is no contact failure due to misalignment of the mask plate.

(ハ) コンピュータ等の計算処理によりプローブ配列
格子上の入力情報のみを選択するので、該検出も無くな
り信頼性の高い布線試験が実施できる。
(c) Since only the input information on the probe array grid is selected through calculation processing by a computer or the like, this detection is also eliminated and a highly reliable wiring test can be performed.

等の効果がある。There are other effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例の布線試験方法およびその装置を説明す
る斜視図、第2図は本発明の布線試験方法およびその装
置を説明する斜視図とブロック図、第3図(a) 、 
(bl 、 (C)は本発明の布線試験方法の動作工程
を説明するフローチャート図および説明図である。図に
おいて 1・・・・・・スイッチ群、2・・・・・・制御部、3
・・・・・・計算部、4・・・・・・情報読取り機構、
5・・・・・・キーボード部、6・・・・・N/C孔あ
け情報、10・・・・・・(測定プローブ)支持板、1
1・・・・・・測定プローブ、12・・・・・・パイロ
ットビン、20・・・・・・(被検査回路)基板、21
・・・・・・スルホール、22・・・・・・端子部、3
0・・・・・・マスクプレート、31・・・・・・逃げ
孔、40・・・・・・布線試峡機測定部。 代理人 弁理士  内 原   晋(ツコ幻ハ¥1回 事2@
FIG. 1 is a perspective view illustrating a conventional wiring test method and its apparatus, FIG. 2 is a perspective view and block diagram illustrating the present invention's wiring test method and apparatus, and FIG. 3(a),
(bl, (C) is a flowchart diagram and an explanatory diagram illustrating the operation process of the wiring test method of the present invention. In the figure, 1... switch group, 2... control section, 3
...Calculation unit, 4...Information reading mechanism,
5...Keyboard part, 6...N/C drilling information, 10...(Measurement probe) support plate, 1
1...Measurement probe, 12...Pilot bin, 20...(Test circuit) board, 21
...Through hole, 22...Terminal part, 3
0...Mask plate, 31...Escape hole, 40...Wiring test machine measurement section. Agent: Susumu Uchihara, patent attorney

Claims (2)

【特許請求の範囲】[Claims] (1)絶縁支持板上に複数の測定プローブを所定のピッ
チで格子上に配置した構造を有する布線試験機による回
路基板の布線試験方法において、前記回路基板のN/C
孔あけ情報を入力し、該孔あけ情報を所定の移動量だけ
移動する工程と、該孔あけ情報から前記測定プローブの
配置格子上に位置する情報のみを選択し、前記測定プロ
ーブと布線試験機との間に配設した測定プローブに対応
するスイッチのアドレスに変換する工程と、該アドレス
に対応した前記スイッチのみをONにする工程とを含む
ことを特徴とする回路基板の布線試験方法。
(1) In a circuit board wiring test method using a wiring tester having a structure in which a plurality of measurement probes are arranged on a grid at a predetermined pitch on an insulating support plate, the N/C of the circuit board is
A step of inputting drilling information and moving the drilling information by a predetermined movement amount, selecting only information located on the arrangement grid of the measurement probe from the drilling information, and performing a wiring test with the measurement probe. A wiring test method for a circuit board, comprising the steps of: converting the address of a switch corresponding to a measurement probe disposed between the device and the device; and turning ON only the switch corresponding to the address. .
(2)回路基板のN/C孔あけ情報を読取る情報読取り
機構と、前記情報読取り機構と接続したキーボード入力
部を有する計算部と、回路基板の被検査部と接触する測
定プローブと布線試験機測定部の間に設け、かつ前記計
算部と接続された制御部により個々にON/OFFされ
る前記測定プローブに対応したスイッチ群とを有するこ
とを特徴とする回路基板の布線試験装置。
(2) An information reading mechanism that reads N/C drilling information on a circuit board, a calculation unit that has a keyboard input unit connected to the information reading mechanism, a measurement probe that comes into contact with the part to be inspected on the circuit board, and a wiring test. 1. A circuit board wiring testing device, comprising: a group of switches corresponding to the measurement probes, which are provided between the machine measurement section and are individually turned on/off by a control section connected to the calculation section.
JP59121402A 1984-06-13 1984-06-13 Wiring testing method and apparatus for circuit substrate Granted JPS61766A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59121402A JPS61766A (en) 1984-06-13 1984-06-13 Wiring testing method and apparatus for circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59121402A JPS61766A (en) 1984-06-13 1984-06-13 Wiring testing method and apparatus for circuit substrate

Publications (2)

Publication Number Publication Date
JPS61766A true JPS61766A (en) 1986-01-06
JPH0426435B2 JPH0426435B2 (en) 1992-05-07

Family

ID=14810288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59121402A Granted JPS61766A (en) 1984-06-13 1984-06-13 Wiring testing method and apparatus for circuit substrate

Country Status (1)

Country Link
JP (1) JPS61766A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6352019B1 (en) 1998-07-31 2002-03-05 Nok Corporation Diaphragm actuator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6352019B1 (en) 1998-07-31 2002-03-05 Nok Corporation Diaphragm actuator

Also Published As

Publication number Publication date
JPH0426435B2 (en) 1992-05-07

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