JPS6174104U

JPS6174104U -

Info

Publication number: JPS6174104U
Application number: JP15844084U
Authority: JP
Priority date: 1984-10-22
Filing date: 1984-10-22
Publication date: 1986-05-20

Description

[Brief explanation of the drawing]

第１図は、本考案の一実施例を示す図、第２図
は、被制御装置の一例を示す図、第３図は、メモ
リの記憶情報の一例を示す図、第４図は、被制御
装置の作動の一例を示すタイムチヤートで、ＲＯ
Ｍ：メモリ、Ａ_０ないしＡ_１２：アドレス選択信
号入力端子、Ｄ_０ないしＤ_７：出力端子、ＡＣＴ
：アドレス選択カウンタ、ＭＢＳ：メモリセルブ
ロツク選択回路、Ｓ_１ないしＳ_４：スイツチ回路
、_＋：直流電源接続端子、ＦＦ：始動制御用フ
リツプフロツプ回路、ＴＳ：始動信号入力端子、
ＡＮＤ：アンドゲート回路、ＣＯ：クロツクパル
ス発振回路、ＲＣ：リセツト信号発生回路、ＤＲ
_１ないしＤＲ_４：駆動回路、ＴＡＣ：交流電源接
続端子、Ｐ_１ないしＰ_３：液体ポンプ、Ｐ_４：気
体ポンプ、ＡＴ：試料大気流入管、ＦＬＴ：ダス
トフイルタ、ＦＭ：流量計、ＡＯＴ：向流吸収管
、ＦＶ：流量調整弁、ＰＭ：光電比色計、Ｔ_１：
洗浄液タンク、Ｔ_２：洗浄液回収タンク、Ｔ_３：
吸収発色液タンクである。 FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of a controlled device, FIG. 3 is a diagram showing an example of information stored in a memory, and FIG. 4 is a diagram showing an example of a controlled device. A time chart showing an example of the operation of the control device.
M: Memory, _A0 to _A12 : Address selection signal input terminal, _D0 to _D7 : Output terminal, ACT
: address selection counter, MBS: memory cell block selection circuit, _S1 to _S4 : switch circuit, ₊ : DC power supply connection terminal, FF: flip-flop circuit for start control, TS: start signal input terminal,
AND: AND gate circuit, CO: clock pulse oscillation circuit, RC: reset signal generation circuit, DR
₁ to DR ₄ : Drive circuit, TAC: AC power supply connection terminal, P ₁ to P ₃ : Liquid pump, P ₄ : Gas pump, AT: Sample atmosphere inflow pipe, FLT: Dust filter, FM: Flow meter, AOT: Direction Flow absorption tube, FV: flow rate adjustment valve, PM: photoelectric colorimeter, T ₁ :
Cleaning liquid tank, _T2 : Cleaning liquid recovery tank, _T3 :
This is an absorption coloring liquid tank.

Claims

[Scope of utility model registration request]

A memory that stores required program information, an address selection counter that controls readout of information stored in the memory according to a count value, and a clock pulse oscillation circuit that introduces clock pulses to the address selection counter via an AND gate circuit and causes the address selection counter to count. and a flip-flop circuit that is inverted in response to the arrival of a start signal or a reset signal corresponding to the output signal of the memory to control the setting and reset of the address selection counter and the conduction/discontinuation of the AND gate circuit; A sequence control device for an automatic analyzer, etc., comprising a drive circuit that controls the operation of various parts in a controlled analyzer according to an output signal.