JPS6174058A - Parallel processing system - Google Patents

Abstract

PURPOSE:To make a processing at high speed after transfer between PEs without decreasing the number of an effective PE by providing a register holding a boundary value, a control register and a selector in respective processor element (PE). CONSTITUTION:Registers 78-81, selectors 82-85, and a control register 86 are provided for a PE77. the registers 78-81 hold boundary values and selectors 82-85 select transfer data between PEs or boundary values. The control register 86 holds a judging bit judging whether the boundary values are required or not after the transfer between the PEs. Interfaces 87-94 carry out an interface with other PE.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a parallel processing method that performs highly parallel processing by connecting identical processor elements (PEs) to a network and distributing processing. In particular, the present invention relates to a method for speeding up processing after data transfer between PEs.

[Prior art]

With the remarkable development of VLSIs and microprocessors, various devices have been proposed and constructed that connect identical PEs in a network to perform highly parallel processing. Figure 3 shows the conventional PE configuration in that case.
00 is a calculation unit 2 that performs a predetermined (′ti calculation); a transfer unit 3 that transfers data between PEs; a memory unit that stores the calculation result of the calculation unit 2 or the transfer data of the transfer unit 3 via the selector 4; 5, and a program memory 1, which is omitted in FIG. 3, for storing programs to be executed.

The network form of such PEs is a grid.

There are tree-shaped, cube-shaped, etc. networks, and each network is adopted depending on the form of inter-PE transfer of the problem to be solved.

Now, as an example, consider the case where a two-dimensional Laplace equation with certain boundary conditions is solved using a grid-like device (a grid-like network is suitable for the second type of problem).

Conventionally, this solution method first approximates (1) to the following difference equation.

-uH+, l-+ ul-1, J+4u+ J u
trt IJ 11. +J+1 =0 (2) Here, the first grid point from the left and the jtith grid point from the bottom is (i, j)
and the value of u (x+y) at that grid point is ui
It is expressed as j. Next, by substituting the closeness for each U, we get
New U1. In the Gauss-Seidel method, the new U, + = Va (u; +j-1+u, -1IJ
+u, and 1. J+u, ,J+,) (3) SO
In the R method, new u, j=old J j +w (registered new u, -) - (old uz)) (4). In either case, conventional equipment assigns one or more grid points to the IPE and
Perform inter-E transfer -ui +J-11u+-11Jl u
trt +1+u1, as soon as 1+1 is complete, new u+,
+ is being calculated. Each PE uses inter-PE transfer and new uiJ
Repeat the calculation until a certain condition is met.

Figure 4 shows an example of a device in which 4x4 PEs are connected in a grid pattern, where 1 is a control unit (CU).

6 to 21 are PE. The CU5 is connected to each PE through a control line 22 and a status line 23, obtains the status of each PE through the status line 23, and obtains the status of each PE through the control line 22.
Control E. The PEs 6 to 21 are coupled by an inter-PE interface line 24.

Data transfer between PEs takes place.

Two methods can be considered for PE allocation of grid points, as shown in FIG. FIG. 5 corresponds to the device example shown in FIG. 4, in which one grid is allocated to the IPE, and the boundaries are square. However, even if this is not the case, the problems described below are the same.

In Figure 5 (A), the grid points are 4 x 4, and PE6~
21 and grid numbers 25 to 40, respectively, and assign a boundary value to the outermost PE and an initial value to the other inner PEs. In this assignment, the boundary value is constant, so the outer PE calculates the new uij (replaces direct with the boundary value, so the calculation of the outer PH becomes invalid. Therefore,
Let the number of rows of the grid be M, ≠1. When the government is N, the actual effective new L1+J calculation is executed, and the number of PEs obtained is (M-2)
x(N-2), and the effective number of PEs is (2(M+N)-4
) The problem arises that the amount of food is reduced. In the example in Figure 5 (A), the total number of PEs is ・IX4, and the effective number of PEs is 2X.
It becomes 2. Unfortunately, the grid is not square but rectangular and N=
In the case of 4, there is a problem that the number of effective PEs is less than half.

Figure 5(B) shows 1. The grid points are 6x6. All 1' in Figure 4
Assign an initial value to E6=21, and set the number of effective PEs to the total PEVl.
This is the same method as 4X4 (generally MXN).

In the case of FIG. 5(B), grid numbers 41-56 correspond to PE6-21 in FIG.

FIG. 6 shows a conventional processing flow in the case of the layout shown in FIG. 5(B) in FIG. First, set the initial value to all PEs,
Set boundary values only for outer PEs.

Then, after broadcasting the program to all PEs.

Each PE performs inter-PE transfer and calculation of new u + , 1. In this case, since each PE has the same program (
(If the programs are not the same, the initial setting overhead will be large), and the outer PE will use P when executing calculations.
It is necessary to replace the data transferred between E with the initialized boundary value. Therefore, at each iteration, each PE performs the calculation of the new u+, +, determines whether to replace it with the boundary value, and if so, performs the replacement in software, so this Overhead is a problem.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the drawbacks of the prior art described above and provide a parallel processing method that does not reduce the number of effective PEs and speeds up post-processing after transfer between PEs.

[Structure and operation of the invention]

The present invention provides registers that hold boundary values in each PE, and
By providing a control register that holds a judgment bit that determines whether a boundary value is required after data transfer, and a selector that selects either the boundary value or the transferred data, it is possible to reduce the number of PEs without reducing the number of effective PEs. This speeds up post-transfer processing.

FIG. 1 shows an embodiment of the present invention, in which 77 is a PE with expanded hardware, 78 to 81 are registers that hold boundary values, 82 to 85 are selectors that select inter-PE transfer data and boundary values, Reference numeral 86 denotes a control register that holds a determination bit for determining whether or not to replace with a boundary value, 87 to 94 are interfaces with other PEs, and 100 is a conventional PE component shown in FIG.

FIG. 2 shows the flow of the process shown in FIG. The detailed operation sequence in the RE allocation method of FIG. 5(B) will be described below, taking the device configuration of FIG. 4 as an example. First, the control unit 5 sets initial values to each PE. That is, 41. to PE6. 42° for PE7, 43 for PE8, 4/l for PE9
45° to PE10, 46° to PE11. 47 for PE12. P
48 on E13, 119 on PE14. 50 for PE15. P
51 for E16, 52 for PE17. 53 for PE18. P.E.
54 on 19, 55 on PE20. Initial values of each of the 56 grid points are set in PE21. Next, a boundary value is set in the outer PE. That is, the register 78 of PE6 has 76, the register 80 has 58. 59. in the register 80 of PE7. P.E.
60 in register 80 of PE 8, 63 in register 79 of PE9
, 61. in register 80. 75 in register 78 of PEl0
, 64. in the register 79 of PEl3. 76 in register 78 of PE14, 65 in register 79 of PE17, PE18
73. in the register 78. 71 in register 81, Pel9
70. in register 81. 71 in register 81 of PE20
．． 66° to register 79 of PE21 68 to register 81
Set the boundary value of each grid point in . In addition, Fig. 5 (B)
Grid points 57, 62, 67, and 72 at the four corners of are not used.

Next, control information is set in the control register 86.

Now, the bits of the control register 86 are sequentially set from the left to the left PE,
Corresponding to the right PE, upper PE, and lower PE, if 'o' is used to use the transfer data, and '1'' is used to replace the boundary value, then 'I OI O' is written in the register 86 of PE6, and PE
7. "0010'" in the register 86 of PE8, "0110" in the register 86 of PE9.

"t o o o" in register 86 of PEL0.14,
pEI I, 0000” in register 86 of 12.15.1.6, ’010 in register 86 of PE13,17
0”, “1001” in register 86 of PE18.

PE], “o o o i” in register 86 of 9.20
, writes '0101' to the register 86 of pE2+.

Next, broadcast the program to each PE m, P
Execute inter-E transfer. In other words, all the PEs 6 to 21 perform transfer in the left direction, right direction, upward direction, and downward direction at the same time. At this time, there are outer PEs that require inter-PE transfers and do not have them, but in order to make inter-PE transfers m-pure and to make the transfer-related programs the same for all PEs to enable broadcasting, it is possible to transfer between all PEs. , perform the transfer. Now P towards the left
When performing inter-E transfer, PE 9, 13, 17, 21 transfers the boundary value held in register 79 to interface 92.
Then, other PEs transfer the transferred data to the interface 92.
to notify. In addition, in the case of transfer between PEs in the right direction, PE6
, 10, 14, and 18 notify the interface 91 of the value held in the register 78, and the other PEs notify the transfer data. In addition, in the case of upward inter-PE transfer, PE18
．． 19.20.21 notifies the value stored in the register 81, and other PEs notify the interface 94 of the transfer data. In addition, in the case of downward inter-PE transfer, PE6
, 7.8.9 notifies the value held in the register 80, and the other PEs notify the interface 93 of the transfer data.

After the PF, inter-transfer is completed, each PE calculates the new ui,l, and repeats the inter-PE transfer and the calculation of the new ut,+ until a certain condition (for example, a residual condition or the number of repetitions) is satisfied.

With such a structure, the allocation shown in FIG. 5(B) in which all PEs are effective can be selected without adopting the allocation shown in FIG. 5(A), which deteriorates PE usage efficiency.

Also, the processing time can be shortened because the boundary value replacement, which is conventionally done in software, is done in hardware.

It is also easy to create software related to transfer.

Now, when processing with the conventional device rI! J (assigned to 5th
(Fig. (B)) is T (subordinate).

T (subordinate) knee T (first) ten T (pu) + k (T (turn) ten T (
Size 1) It can be expressed as 10T(α)+T(u)+T(size)). Here, T (first time) is the initial setting time, T (pu) is the program setting time, and is the number of repetitions.
T (transfer) is the transfer time between PEs, T (judge I) is the time to determine whether to use the transferred data, ■ (α) is the time to replace with the boundary value, T (u) is the calculation time for u+, + , T (judgment 2) is the determination time of the repetition condition.

On the other hand, the processing time T (books) according to the present invention is T (tree) - = T (first time) ten T (system) ten T (pu) + k (T (
)+T(u)+T('NJ2n). Note that T (regime) is the setting time of the control information 5
Second, when setting the control information, even if the number of PEs increases, there are at most nine control patterns, so it is sufficient to broadcast each pattern to each PE.

T (control) can be ignored when k is large. Therefore.

In the PE of the present invention, compared to the conventional PE, approximately k (T (α) + T
(Version 1)) The processing time can be shortened.

In the example, a lattice network will be explained as an example,
However, even if the network is in the form of a cube or tree, it is effective when applying a network-like device to a problem field that deals with boundary conditions. Furthermore, the method of the present invention is also effective even if the boundaries have various shapes (for example, convex, concave, etc.). Furthermore, even when multiple grids are allocated to the IPH instead of one grid, the method of the present invention can be applied by increasing the register capacity for holding boundary values and the number of bits of the control register. .

〔Effect of the invention〕

As explained above, according to the present invention, simple hardware is added to a conventional PE.

There is an advantage in that the method can be applied to efficient allocation among PEs, in which data processing after data transfer between PEs is fast.

[Brief explanation of drawings]

FIG. 1 is a PE configuration diagram showing an embodiment of the present invention. Fig. 2 shows the processing flow of Fig. 1, Fig. 3 shows an example of a conventional PE configuration, and Fig. 4 shows PEs arranged in a grid.
Figures 5(A) and 5(B) show an example of a device in which the P of the lattice point is
The E layout is a diagram showing the method, and FIG. 6 is a diagram showing the processing flow of the conventional PE configuration. 5...Control unit (CU). 6-21... Processor element (PE). 77... PE of the present invention, 78-81... Boundary value holding register, 82-85 selectors. 86...Control register, 100A conventional PE. Figure 1, Ward 2, Figure 4, Figure 5

Claims (1)

[Claims] (1) Multiple processors connected in a network
and a control unit that controls each processor element, and each processor element has a program memory that stores a program to be executed, a data memory that stores data, and an arithmetic unit that executes its own program. In a parallel processing system comprising a transfer unit that performs transfer between each processor element, each processor element has a value (
A control register that indicates whether or not a boundary value is required after transfer between processor elements (hereinafter referred to as a boundary value), and a selector that selects a boundary value and inter-PE transfer data. Features parallel processing method.