JPS6170636A - Total adder circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates generally to large scale integrated (LSI) circuits, and more particularly to a 21-digit adder useful in LSI circuits.

(Background Art) As is already known, a binary adder is one of the basic building blocks of a digital computer, and the speed at which the adder operates is directly related to the speed of the digital computer)! ! Give I. The speed of binary adders is particularly important for use in LSI circuits. A relatively high-speed full adder using IEEJ Jour's CM OS technology
nal of 5olid, -8tate C1rcv
, its (Vol. 9, April 1979, 5C-14,
/162, pp. 214-220 N, Ohwadα.

T, Kimura and! , a paper written by Doken [
LsI'5for Digtal Signal P
rocessing J, in combination with a transfer gate. When a transfer gate is added,
The operating speed can be significantly increased compared to conventional full adders that use only exclusive-seven OR gates. Unfortunately, there is a logic delay associated with generating the necessary carry output signal.

That is, the transfer gate that generates the carry output signal is controlled by the A■B or A■B logic signal (A and B (the signals to be added)), and the transfer gate that generates the carry output signal is The inherent delay in processing limits the speed of operation.

Equation (Summary of the Invention) In view of the foregoing background art, it is an object of the present invention to provide an LS system in which the states of the A and B input signals directly determine the carry output signal.
The purpose of the present invention is to provide an I-full adder.

Another object of the invention is to provide a complementary pair 8 of full adder cells that can be directly connected to minimize delay.

The above and 1m objects of the present invention are A, B and C1'I)
The first one has one manual power, a sum output, and an inverted carry output.
Adder cell with A%B and CIN manual input, inverted sum output,
This is achieved by interconnecting the full adder cells with complementary (co/fourimentary lines) with carry outputs. In both adder cells, there are serially connected p-channel and effect transistor (FE)
T) pairs to generate a carry output signal in response to the state of the A, B, and B input signals.

(Explanation of Embodiments Before describing the embodiments with reference to the drawings, it will be appreciated that
Note that it is desirable to use a widely available LSI technology called OS. That is, the circuits (shown in block form in the drawings to illustrate the underlying logic of the invention) are typically formed on a common substrate using Chi OS chips.

Referring to FIG. 1, a full adder 10 in accordance with the present invention is shown which receives A, B and C (carry inno) inputs, S (orono and C0UT (inverted carry
Provides Araton output. Table 1 shows the truth table of the full adder 10.

Dragon 1 From this truth value, it is obvious to those skilled in the art that a pool type like lack can be obtained.

, S'=(A■B)c+CA■B) C(1]y=(
A■B)C+(,A■Bfko (2)COUT"'
(A ■B) C+A ・B (
3 ('0IJT= (A(f3B)c+h -h
(4) The A input signal is transmitted to (α) the input terminal of the in/beta 11, (b) the input terminal of the transmission gate T1, and (c) the p-channel/channel FE, as shown in the figure.
T P and the gate terminal of the n-channel F E T N2. The universal signal is (al inno -
(b) the n-channel terminal of the transmission gate T, and (c) the p-channel terminal of the transmission gate T2.

The B1 word on the output of inverter 13 is connected to (a) the p-channel terminal of transmission gate Tl and (b
) the n-channel terminal of transmission gate T2; and (c) the gate terminal of p-channel FET P2 and n-channel FET #l.

Here, a little bit from the main topic, Tora/Sumitsun Yong Gate is CMO 8's MO
It should be noted that it will be obvious to those skilled in the art to represent the S transistor connection mode. In general, a transmission gate is an n-channel gate terminal that receives a signal from the device's input terminal. When the gate terminal is at the logic "0" level, it is passed to the output terminal of the device. On the other hand, when the n-channel terminal of the opposite IC is at the logic rOJ level and the p-channel terminal is at the logic "1" level, the transmission gate is in the OFF state (ie, it does not pass through the device).

From the above B, it can be seen that inverters 11 and 13, transmission gates T, and T2 generate A*B100 numbers, and inverter 5 generates A*B words. The A and B signals are connected to (α) the n-channel gate terminals of transmission gates T3 and T, and (b)
and the p-channel gate terminal of transmission gate T4η.

The iΦi signal is (α) transmission gate T4
and (b) the P-channel gate terminals of transmission gates T3 and T. The carry-in CI N signal is (
α) valving inverter 17 to connect the input terminal of transmission gate T3 (no reference number); (b) input terminal of transmission gate T4; (c) valving inverter 19 to connect transmission gate T; is added to the input terminal of and .

The oro (S) output is generated by inverter 17 and transmission gate T3 or T4.

Thus, S assumes that (AeE) is a carry with the logical "]"
When (AeE) is logic "O" and C is logic "1" (i.e., transmission gate), When T4 is activated, it becomes logic "1".

The inverted carry-out CoUT is a logic ``1'' when both the A and B inputs are a logic ``0'' (this state is referred to as the ``carry generation'' mode). Conversely, if both the A and B inputs are a logic ``1'' (this state is referred to as ``carry-stop'' mode, the inverted carry-out
yT becomes logic "0".

The p-channel FETs P and P2, which are gated by the A and B inputs, respectively, are gated by connecting the source V to 6OUT when in "carry generation" mode.
n-channel FET with inverted carry-out C0UT and gated by B and A inputs respectively
#I and N2 are in "carry stop" mode (:
By connecting 'OUT to ground, an inverted carry-out εOUT is generated. When the (AeE) signal is logic Ill, the inverted carry-out σOUT is C'
IN is inverted (this state is called the "carry transfer" mode. In this mode, the inverter 19 is
Inverts the IN signal and sends the signal to the transmission
Gate T.

(activated by the AeE signal applied to the n-channel gate terminal of this gate).

It should be noted here that only in the case of "carry propagation" motes is there a logic delay associated with the generation of a counter-intermittent carryout C0UT. In other words, "carry occurrence"
In both the ``carry stop'' and ``carry stop'' modes, the inverted carry-out C0UT signal is generated immediately by the state of the A and B input signals, and in the ``carry transfer'' mode, the εOUT signal is The transmissive gate formed to activate the transmission gate T does not occur until it occurs.

Referring to FIG. 2, a full power multiplier 10 (combinant of FIG. 19) is shown which receives A, B and CXN input signals, inverts 20(S) and carryout (CoU).
T) provide an output signal. Full adder 20 was developed to maintain correct polarity of the carry signal in the adder array. Thus, the full adder 10 (FIG. 1)
The full adder 20 receives an inverted carry-out CoUT and an output signal, and receives an inverted carry-delta signal and generates a carry-out CoUT output signal.

The full adder 20 operates in the same manner as the full adder 10 (FIG. 1, 9).As mentioned above, the inputs to the all-zero adder are A, B, and i, and the outputs are 5rybt and C0UT. The inverters 21, 23 and 25 and the transmission gates T1 and T2 are (A■B) and (A(fjB)
form a signal. Here, the full adder 10 (FIG. 1) is B
Note that full adder 20 has a B input.

In full adder 20, the connections to transmission gates TI and T2 are inverted compared to FIG. 1 to effect a change in polarity. The full adder 20 uses the A■B signal and its complement to valve the inverter 27 and transmission gates T3 and T4 to SUM.
The output is generated by the inverter 29 and the transmission gate T.

to generate the C0UT output signal. As mentioned above, the carry signal is FET P1. P 2 , N 1.
/V2, but to maintain proper polarity of the CoUT signal, FETs PIIP2 and N1. N2
is gated by the A and B signals rather than the A and B1 words.

Referring now to Figures 1 and 2, it can be seen that the generation or termination of the carry signal directly at the carry output point provides speed advantages over conventional adder cells. That is, in carry transfer mode (i.e.,
When the C0UT signal is generated at the transmission gate T, both the SUM and C0UT outputs experience a delay of about 2.5 gates, but in the "Carry Stop" and "Carry Generate" modes, the SUM and C0UT outputs are very fast (C Furthermore, by using adders 10 and 20 in series and alternating the carry output (1'OUT signal), the carry propagation delay can be reduced by l gate delay per pair. .

Referring now to FIG. 3, an array formed by combining adder 10 (FIG. 1) and adder 20 (FIG. 2) is shown. Adders 101 and 10□ are connected to a bank of registers (
A1 and B receive input signals from (not shown). Adder 201 (complement 11 of adder 101 receives A2 and B2 inputs from registers (not shown), CIN input is >10 inverse carry-out εO
It is UT. Adder 20□ (complement of adder 10□) is a register (not shown) that receives A2 manual power,
B input is added to adder 10. With the vO(S) output from, CI
N input is the inverted carry-out C0 from adder 102
This is the UT output. The adder 103 receives registers (A and 13 from the diagram), and the CIN input is connected to the adder 20.
, is the carry ara) COUT output. Adder 10
4 received A3 human power from the register (not shown), and 3
The input is the inverted 0 (S) output from the counter 201, and the GIN input is the carry-out C0UT output from the adder 202.

Best of all, it is desirable to maintain symmetry between complementary adders 10 (FIG. 1) and 20 (FIG. 2), so adder 10 (FIG. 1) requires an input of B or B. It should be noted that The need for human labor does not limit the utility of this device. This is because the input signal to such an adder cell is generally obtained from a register, from which both non-inverting and inverting outputs are obtained.

Although preferred embodiments of the present invention have been described above, it will be apparent to those skilled in the art that other embodiments are possible within the scope of the present invention.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a full adder cell according to the invention. FIG. 2 is a circuit diagram of a complementary adder of the full adder cell of FIG. 1 provided to properly maintain the integrity of the carry signal within the array. FIG. 3 is a diagram showing how the 7IO devices of FIGS. 1 and 2 are combined in an array. (5 other people)

Claims (2)

[Claims] (1) In a full adder circuit that generates the sum of two digital input signals A and B, each at a logic 1 or logic 0 level, accompanied by a digital carry signal at a logic 1 or logic 0 level, ( a) a first gating circuit that generates a logic one level digital carry signal in response to A and B when both have a logic zero level; (b) A and B when both have a logic one level; a second gating circuit that generates a digital carry signal at a logic 0 level in response to B; (2) the first gating circuit comprises a pair of p-channel field effect transistors; the second gating circuit comprises n-channel field effect transistors cascaded across a voltage source; each transistor of each pair controlled by either A or B, the first gating circuit is conductive when both A and B are at a logic 0 level, and the second gating circuit is conductive when both A and B are at a logic 1 level; A full adder circuit according to claim 1.