JPS616776A - Recognizing device of two-dimensional sight - Google Patents

Abstract

PURPOSE:To recognize rapidly and easily an input pattern even if the input pattern is shifted positionally by executing pattern matching while correcting the positional shift of the input pattern from a reference pattern. CONSTITUTION:A picture of a reference model is picked up by a television camera 1 and encoded into a binary signal of white and black by a binary-coding circuit 4 to find out a reference pattern and the length of a black picture element string and a distance up to the black picture element string are calculated by a CPU10 in each horizontal scanning line. Simultaneously, a deviation between a distance up to a specific black picture element string and a distance up to the black picture element string of each line is found out and the length of the black picture element string and the deviation are successively stored in RAMs 12, 13 from their leading addresses. Similarly, the picture of a substance to be recognized is encoded into a binary signal of white and black to find out an input pattern and the length of a black picture element string and its deviation are found out in each horizontal scanning line. At the detection of the leading black picture element string of the input pattern, the length of the black picture element string of the reference pattern and its deviation are read out from the RAMs 12, 13 and compared with the length of the black picture element string of the input pattern and its deviation.

Description

[Detailed Description of the Invention] <Technical Field of the Invention> The present invention obtains an input pattern by imaging a stationary or moving object to be recognized, and compares this input pattern with a standard pattern to recognize the object to be recognized. In particular, the present invention provides a new device that performs matching between patterns while correcting the misalignment of an input pattern with respect to a standard pattern.

<Background of the Invention> Generally, a two-dimensional visual recognition device recognizes an object by superimposing an input pattern and a standard pattern on an image, detecting the degree of superimposition and coincidence of both patterns. Therefore, when performing pattern matching, it is necessary to accurately align both patterns. Conventionally, after positioning the target fabric at a predetermined stopping position using an XY stage, etc., this is imaged with a television camera and input. The N6 turn is obtained, and this input pattern is compared with the standard turn. However, in this type of method, a mechanism for positioning the object to be recognized is required, which makes the overall structure of the device complicated.
Another disadvantage is that pattern matching takes time equal to the time required for positioning operations. However, in this method, the object is positioned and stopped, so it is not suitable for recognizing moving objects flowing on a conveyor.Furthermore, it requires a large capacity image memory for turn-by-turn verification, so the device There were many practical problems such as increased cost.

<Objective of the Invention> The present invention proposes a new method for inputting a standard pattern and performing pattern matching while correcting the positional deviation of the N6 turn without using a large-capacity image memory. To provide a low-cost two-dimensional visual recognition device that can quickly and easily recognize an object even if the position shifts from one turn to the next.

<Structure and Effects of the Invention> In order to achieve the above object, the present invention first converts the image of the standard model into black and white binarized, calculates the turn in the standard model, and calculates the length of the black pixel column and the black color for each horizontal scanning line. Calculate the distance to the pixel column. At the same time, the deviation of the distance to each heated pixel column with respect to the distance to a specific black pixel column is determined, and the length and deviation of the black pixel column are sequentially stored in the memory starting from the first address. Next, using the same procedure, the image of the object to be recognized is converted into black and white binarized to obtain an input pattern, and the length and deviation of the black pixel column are determined for each horizontal scanning line. In this case, when the first black pixel string of the input pattern is detected, the length and deviation of the black pixel string of the standard pattern are read from the first address of the memory, and the length and deviation of the black pixel string of the input pattern are calculated. The comparison is made for each horizontal scanning line.

According to the present invention, since there is no need to position the object to be recognized at a predetermined stop position, a special positioning mechanism is not required, the entire device can be simplified, and the time required for positioning operations can be saved. The efficiency of object recognition processing can be improved.

In addition, since the object does not have to be positioned and stopped, it is suitable for devices that recognize moving objects flowing on a conveyor, and since it does not require a large capacity image memory for pattern matching, it can simplify the device and reduce device costs. It has a remarkable effect of achieving the purpose of the invention, such as making a contribution.

<Description of Embodiments> FIG. 1 shows an example of a circuit configuration of a two-dimensional visual recognition device according to the present invention. A television camera 1 in the figure images an object 2 flowing on a conveyor, for example, from above, and sends an image output (shown as il+ in FIG. 3) related to interlaced scanning to a synchronization separation circuit 3. The synchronization separation circuit 3 extracts a horizontal synchronization signal HD, a vertical synchronization signal VD, and an odd field signal O from the image output.
D (shown in Figure 3 (2)), clock signal CK (shown in Figure 3 (2)),
(shown in FIG. 4), etc., and outputs the video signal VDi to the binarization circuit 4. As shown in FIG. 3 (3), the binarization circuit 4 sets a certain threshold level TH for the video signal VDi, converts odd fields of the video signal VDi into black and white binarization, forms a binary pattern, and outputs it. do.

FIG. 2 shows an example of this binary pattern, FIG. 2 (1) shows the standard pattern P, and FIG. 2 (2) shows the input pattern Pi. In the figure, the shaded areas indicate black pixels, and the areas other than the shaded areas indicate white pixels. In this embodiment, each pattern is composed of black and white pixels of 256 bits in the vertical and horizontal directions.

A white pixel detection circuit 5 and a black pixel detection circuit 6 are connected to the binarization circuit 4, a pixel counter 7 is connected to the white pixel detection circuit 5, and another pixel counter 8 is connected to the black pixel detection circuit 6. are connected to each other. The black pixel detection circuit 6 detects black pixels forming each pattern, and the white pixel detection circuit 5 detects white pixels corresponding to the background portion. One pixel counter 7 counts the output (number of white pixels) of the white pixel detection circuit 5,
When the black pixel detection circuit 6 detects a black pixel, the pixel counting operation for that row is stopped, and the other pixel counter 8 then counts the output of the black pixel detection circuit 6 (the number of black pixels).

These pixel counters 7.8 are connected to the CPU (Centra) of the microcomputer via the Ilo port 9.
lProcessing Unit) l Connected to Q, CP and UIQ take in the count data of pixel counter 7.8, and use this read data etc. to correct the positional deviation of one turn of the input cover with respect to the standard pattern, collate both patterns, etc. , executes a series of calculations and various processes related to object recognition. This C, PUIO is a PROM (Pr
ogramnable Read 0nly Memo
ry) ll, 1st + 2nd RA for storing postscript data regarding the standard pattern, M (Read 0nly
Memory) l 2゜13 are connected respectively, R
AM12.13 has a horizontal scanning line number (256 in this example).
) is provided, and the count data for each horizontal scanning line is stored in the corresponding address area. In the figure, the OR circuit 14 is a circuit that resets the pixel counters 7 and 8, and the gate circuit 15 is a circuit that resets the pixel counters 7 and 8.
The circuit for generating NT, switch SW, is a mode changeover switch.

FIG. 4 +11 +2+ shows an example of the configuration of the standard pattern P and the input pattern Pi, and the positional relationship between the patterns. In the figure, A, A/ are optical surface black pixels in each pattern P, Pi, Xl, Y, N2. Y2 indicates the position data of each black pixel A and A', and one black pixel A/ is shifted from the other black pixel A by N2-Xl in the horizontal direction and by Y2-Yl in the vertical direction.

Also, the histogram H, shown in Fig. 4 (], llf2),
N2 is the number of black pixels for the horizontal scanning line N, , N2, histograms H3 and H4 are the deviation W1.
In addition, the area diagrams of the RAMs 12 and 13 respectively show the storage range of the number N1 of black pixels and the deviation W1 (shaded areas in the figure).

However, after setting the mode changeover switch SW to the learning mode side a, when the TV camera 1 captures an image of the Shibejuku model, binarization processing is executed for the first odd field of the video signal VDi to form a standard pattern, and the pixel A counter 7.8 counts the number of black and white pixels for each horizontal scanning line. And horizontal synchronization signal HD in odd field
At each time timing, interrupt signal I is sent to CPUl0.
NT is generated, and the CPU 10 internally takes in the count data of the pixel counter 7.8 during this horizontal synchronization period.

FIG. 5 shows such an interrupt control operation, and in the figure,
XA indicates the count value of the pixel counter 7, N1 indicates the count value of the pixel counter 8, Yl indicates the count value of the row counter set in the RAM 12, and F indicates the contents of the flag area set in the same RAM 12. Mas CPU 1. Q is
Step 21 Initialize row counter Y1 (Yl-1)
After that, in step 22, the counted value
In other words, detect black pixels in scanning that row.1. Check whether it is correct or not. If the pixel counter 7 has now counted the number of pixel data for one row (256 pieces) without being subjected to counting stop control by the black pixel detection circuit 6, step 22 becomes "YES", and the next step 23 flag F After clearing, at step 24, the count value Y1 of the row counter reaches the final scanning row (25 in this embodiment).
6 rows) is reached. In this case, since the determination in step 24 is "NO", the process returns to the interrupt waiting state at the start, and a similar white pixel counting operation is executed for the next row.

Thus, in the counting process of each row, when the black pixel detection circuit 6 detects a black pixel, the pixel counter 7 stops counting operation in the horizontal scan at that point, and the other pixel counter 8 starts counting the black pixel column from that point on. Start counting. Therefore, in scanning this row, the count value XA of the pixel counter 7 is r25
6j is not reached, and as a result, in the interrupt processing for the next horizontal blanking period, the determination at step 22 becomes "NO'", and the process proceeds to step 25, where it is checked whether the content of flag F is zero. In this case, step 25 is “Y”
ES'', the CPU 20 then reads out the count value N1 of the pixel counter 8 and sets the threshold value T in step 26.
Compare the size with H and l. If the count value N1 of the pixel counter 8 is less than or equal to the threshold value TH1, it is determined that the black pixel row to be counted is, for example, noise, and step 26 becomes -YES'' and the process returns to step 24. When the policy value N□ exceeds the threshold value TH1, step 26 becomes "No", and step 27 pixel counter 7
The count value XA is.

The count value N of the pixel counter 8 is written in the data area X1 set in the RAM 12, and in the subsequent step 28.
1 is stored at the first address of the black pixel number storage area in the aAM 12. Next, in step 29, the CPUIQ calculates the deviation Wl (zero in this case) from the difference between the count value xA of the pixel counter 7 and the contents of the data area
It is stored in the first address of the deviation storage area of AM13.

Furthermore, in step 30, the detection flag F is set to "1", and in subsequent steps 31 and 32, each address counter in the RAMs 12 and 13 is incremented.

Thus, for the horizontal scanning line containing the standard pattern below, "xA=256J" of step 22 is "NO".

rF=OJ in step 25 continues to be “NO”,
In this case, the number of black pixels N1 and the deviation Wl are stored in step 28.29 without going through steps 26.27. The above series of processes are repeatedly executed until the contents of the row counter Y1 reach r256J, and the determination of [y1=256J in step 24 is "YES"]
When this occurs, the row counter Yl is cleared in step 33, and each address counter in the RAM 12.13 is cleared in step 34.3!5, completing a series of processes regarding the standard pattern.

Next, when performing recognition processing for the object to be recognized, after setting the mode changeover switch SW to the recognition mode side, perform the same imaging operation and binarization processing, and then perform the input pattern P.
Find i. Then, as above, at the time timing of the horizontal synchronizing signal HD in the odd field, C, PUIQ
An interrupt signal INT is generated, and the CPU 10 takes in count data of the pixel counter 7.8 during the horizontal synchronization period, and executes pattern matching processing while correcting positional deviation between patterns.

FIG. 6 shows such an interrupt control operation, and in the figure,
XA' is the white pixel count value of the pixel counter 7, N2 is the count value of the pixel counter 8, Y2 is the count value of the row counter set in the RAM 12, and F is the content of the flag set in the same RAM 12. It shows. In the same figure, the processing flow from step 41 to step 47 is shown in the fifth step.
This is similar to the figure, and in step 47, [
The counted value XA' of the pixel counter 7 when the judgment of N2≦THIJ becomes -YES'' for the first time is stored in the RAM 12.
is written to the data area y2.

Then, in step 48, the CPU 10 takes in the count value N2 of the pixel counter 8, and further in step 49, the CPU 10 takes in the count value N2 of the pixel counter 8.
The count value N1 of the address area (in this case, the first address) specified by the address counter of M12 is read out, and both data are compared. As a result, both patterns are matched with the positional deviation corrected, and as a result, the CPU
IQ is the number of mismatched black pixels ΔN from the difference between the two (N1-N2)
is calculated (step 50). Next, in step 51, cpulo calculates the deviation W2 from the difference between the count value XA' of the pixel counter 7 and the contents of the data area The deviation W1 for the standard pattern is read from the address). Furthermore, in the next step 53, the number of mismatched white pixels ΔW is calculated from the difference between the two ("I W2"), and in the following steps 54 and 55, the number of mismatched black pixels ΔN, the number of mismatched white pixels ΔW, and the threshold value TH2 are calculated. are compared.If step 54 "
Determination of ΔN<TH2J and step 55 [ΔW<T
When both H2J determinations are YES n, the cumulative addition value NT of the mismatched black pixel number ΔN is calculated in step 56, and then the address counter of the Hibi RAM 12.13 is incremented.
The address area of each RAM 12.13 is designated (steps 57 and 58).

In the above series of processes, the count value Y2 of the row counter is "256
”, and as a result, the cumulative addition value NT
When the value is smaller than the threshold value TH3, the determination in step 59 becomes "YES", and in the next step 60, CPU10 outputs a coincidence output.

On the other hand, in the iterative processing process, when the number of mismatched black pixels ΔN or the number of mismatched white pixels ΔW is calculated equal to or greater than the threshold value TH2, steps 54 and 55 become "No", and the cumulative addition value NT is equal to or greater than the threshold value TH3. , step 64 becomes ``NO'', and in either case the CPU
0 outputs a non-coincidence output (step 61), and in the next step 62, the count value Y2 of the row counter is cleared.

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram of a two-dimensional visual recognition device according to the present invention, Fig. 2 fl) +2+ is an explanatory diagram showing standard patterns and input patterns, and Fig. 3 is a signal waveform of the circuit configuration example shown in Fig. 1. Timing chart showing Figure 4 (1)
1 (21 is an explanatory diagram showing the principle of correcting the positional deviation of the input pattern with respect to the standard pattern, Fig. 5 is a flowchart showing the interrupt processing operation in learning mode, Fig. 6 + 11
+21 is a flowchart showing the interrupt processing operation in the recognition mode. 1...TV camera 4...Binarization circuit 7.8...Pixel counter 1o...CPU
12.13...RAM minute 3 figure terror '1121 labor 6 figure (g) Tetoshi c2ノ

Claims (2)

[Claims] (1) Means for obtaining a standard pattern and input pattern by converting the object image into black and white binarization, means for calculating the length of a black pixel column and the distance to the black pixel column for each horizontal scanning line for each pattern, specifying for each pattern means for calculating the deviation of the distance from each row to the black pixel column with respect to the distance to the black pixel column; means for sequentially storing the length and deviation of the black pixel column for each horizontal scanning row for the standard pattern from the first address; means for reading out the length and deviation of the black pixel string of the standard pattern from the first address and comparing it with the length and deviation of the black pixel string of the input pattern for each horizontal scanning line when the black pixel string of the input pattern is detected; A two-dimensional visual recognition device comprising: (2) The two-dimensional visual recognition device according to claim 1, wherein the specific black pixel row is the first black pixel row in the pattern.