JPS6166300A - Sampling and holding circuit - Google Patents

Abstract

PURPOSE:To perform the level shift and level conversion independently of each other with no addition of a gain control circuit, etc., by combining three switches and two capacitors. CONSTITUTION:The 1st sampling circuit consists of the 1st switch 1 connected to an input terminal 11 and a capacitor 4 connected to the switch 1. Then the 2nd switch 2 is connected to the 1st sampling circuit. The 3rd switch 3 is provided between earths and in parallel to a capacitor 5 connected to the switch 2, a voltage dividing circuit consisting of the switch 2 and the capacitor 5 respectively. The voltage dividing ratio can be set according to the selection of a capacity ratio between capacitors 4 and 5. At the same time, the level of a terminal 13 is varied by operations of switches 1-3. Thus it is possible to obtain a sampling/holding circuit that can perform the level shift and level conversion operations independently of each other with no addition of a gain control circuit, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit capable of level conversion and level shifting.

(Prior Art) Conventional sample-and-hold circuits of this type cannot perform level shifting or level conversion by themselves, and in order to perform level shifting, etc., it is necessary to connect an additional circuit. The hold circuit will be explained with reference to FIG.

In the same figure, one circuit consists of switch 1 and capacitor ? 4
, an operational amplifier 6, and a resistor 7.8 for setting the gain of the operational amplifier 6.

Now, when switch 1 is turned on, input terminal 11
0 signal passes through switch 19. The voltage is applied to the capacitor 4. Next, when the switch 1 is turned off (OFF'), the accumulated charge in the capacitor 4 is held.

It becomes a hold state. The voltage applied to the capacitor 4 is input to the non-inverting input terminal of the operational amplifier 6, and is amplified by the ratio of the resistance values of the two resistors 7 and 8, and is applied to the output terminal 1.
6 is output.

The signal at the level shift terminal 14 is input to the inverting input terminal of the operational amplifier 6 through the resistor 7, amplified in the same way as the signal input to the non-inverting input terminal, and output to the output terminal 16. . This can be expressed numerically as shown below.

Va-(Rt+FLs>・V/Ry Rs・Vi/R
y・・・・・・・・・・・・ (1) Here, vs is the signal level at the Riki Hatoko 16, V is the signal level at the input terminal 11, and the content? Equal to the level applied to 4. Further, vR represents the signal level at the level shift terminal 14, and R1°all represents the resistance value of the resistor 7.8.

As is clear from the above equation (1), although this circuit is capable of level shifting, the gain cannot be set below 1, and if the gain is set to t-1, level shifting becomes impossible. For this reason, conventionally it was necessary to add a circuit to lower the gain after the sample and hold circuit shown in Figure f'i44.

(Object of the Invention) An object of the present invention is to provide a sample-and-hold circuit that can perform level shifting and level conversion independently without adding a separate circuit.

(Structure of the Invention) The structure of the tensile hold circuit of the present invention includes a sample circuit having a series body of a first switch to which an input is applied and a Fil capacitor, a second switch connected to this, and a A voltage divider circuit having a series circuit with 2:nd/f and '! P.J.
3 switches.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a sample/pull hold circuit according to a first embodiment of the present invention, and FIG. 3 is a time chart showing the operating state of the sample/hold circuit of FIG. 1. In FIG. 1, the two sample and hold circuits are 1. Second. The third switch 1, 2°3 and the content of fil, 342? 4.5.

First, in order to set the level of the output terminal 13 to the reference potential (ground potential in this example), the second capacitor/switch 5 on the output side is set.
Turn on the third switch 3 connected in parallel to
), and the charge on the second capacitor 5 is set to zero. This conde/? Assuming that the capacitance of 5 is C8 and the charge is Q6, the following equation is obtained.

Qs=C+s・0=0 (2) After the discharge period k shown in FIG. 3 has passed and the third switch 3f is turned 7 (OFF), the first content f4
In order to charge a charge proportional to the level of the input terminal 11, the first switch 1t is turned on. Let the level of input terminal 11 be v, the first content? 04m capacity
Letting the stored charge be Q4, the following equation is obtained.

Q4-C,・V ・・・・・・・・・(3) 9. Charging section B shown in FIG. 3 has passed. Turn off the first switch 1
After that, the partial pressure switch 2 is turned on. Here, the first
Content? Is the charge charged in 4 the first content? 4 and the second content? It is divided into two according to the capacity ratio with 5. Since this charge is conserved, a first-order equation can be obtained from equations (2) and (3).

Q4 +QB = C4・V+ O---(4)gJ3
The voltage division period C shown in the figure has passed, and the second switch 2 is turned OFF.
When it becomes F, the interval until the start of the 8th discharge interval A is a hold interval, and the second content? The charge of 5 is retained. At this time, the level vo of the output terminal 13 is (4)
A linear equation is obtained from the equation.

Q4 +Qi -C4・v−(Ca+Cs)・Vo
・” (5) Therefore, the ninth-order equation is obtained from this equation (5).

Vo=Ci・V/CC4+Cs) ・”・”<6> As explained above, by appropriately determining the capacity ratio of the first capacitor 4 and the second capacitor 5, the The pressure ratio can be set, and with the above circuit configuration,? A sample hold circuit can be configured.

FIG. 2 is a circuit diagram of a sample and hold circuit according to a second embodiment of the present invention. This sample-and-hold circuit includes an operational amplifier 6, a resistor 7.8 for setting the gain of the operational amplifier 6, and a circuit section 9 that is the same as the circuit shown in FIG.

Now, when the signal at the input terminal 11 is input to the sample hold circuit section 9, the input signal is '! The voltage is divided by the capacitance ratio of the capacitor 4 and the second capacitor 5 of 1I11,
The signal at the output terminal 13 is connected to the non-inverting input terminal of the operational amplifier 6.

The gain of this operational amplifier 6 is set by an input resistor 7 connected to the inverting input terminal and a feedback resistor 8 connected to the inverting input terminal and the output terminal. When the signal at the level shift terminal 14 is input to the resistor 7, an operation is performed between the signal at the level shift terminal 14 and the signal at the output terminal 13, and the result is output as a signal at the output terminal 16. Now, set the level of V Bern 7 toe 14 to 'k', and set the level of V R# output terminal 13 to Vo, a:l.
Set the level of the blade terminal 16 to V B + resistor 7. Letting the resistance values of the resistors 8 be R1, R@, respectively, a 9th order equation is obtained.

Vll-(R17+FL8) ・VO/R1? -R11
1・Vn/Rrt・・・・・・・・・・・・(7) Here, by substituting the above equation (6) into the above equation (7), 9
The following equation is obtained.

Ys-(FLy+Rs)-c, ・V/Ray ・(C
4+C3)-Rs, Vn/FLt ・Old...-
・" (8) - As an example, if R7=R8, C4-C5, it becomes a linear equation % equation % In other words, it becomes a circuit capable of level shifting.

R7-FL8, 3.C4-C, a linear equation is obtained.

VB=2. V/4 vR-Vz-vR-+・++-+
It is also possible to set the total gain to 1 μ below m(lo), i.e., level 77.

Therefore, depending on the level vR of the level shift terminal 14,
It is possible to level shift the output signal, and the first capacitor 4 and the second capacitor 5° resistor 7. By increasing the value 't, 18 of the resistor 8, level conversion can be performed at a desired ratio.

(Effects of the Invention) According to the present invention, as explained above, level conversion can be performed by combining at least three switches and two capacitors, and a non-inverting amplifier can be combined with this. As a result, effects such as level shifting can be achieved at the same time can be obtained.

[Brief explanation of the drawing]

'W! FIG. 11 is a circuit diagram showing a sample and hold circuit according to the first embodiment of the present invention, and FIG. 2 is a circuit diagram showing a pull and hold circuit according to the second embodiment of the present invention. Figure 83 is a time chart showing the operation of the switch in the sample-and-hold circuit shown in Figure 1, and Figure 4 is a time chart showing the operation of the switch in the sample-and-hold circuit shown in Figure 1.
FIG. 2 is a circuit diagram showing a pull-hold circuit. Furthermore, in [F]. 1.2.3...Switch, 4...1st
capacitor, 5... capacitor of fJII2, 6... operational amplifier, 7, 8... resistor, 9... sample/hold circuit section, 11・
...Input terminal, 13.16...Output terminal, 14...Level shift terminal, A...
Discharging section of the second capacitor, B... Charging section to the first capacitor, C... Voltage dividing section to the second capacitor, D... Holding section , E...
...Switch OFF' section.

Claims (1)

[Claims] a sample circuit having a first switch connected to an input terminal and a first capacitor connected to the first switch; a second switch connected to the sample circuit; and a second switch connected to the second switch. 1. A sample-and-hold circuit comprising: a voltage divider circuit having a second capacitor with a second capacitor; and a third switch connected in parallel with the second capacitor.