JPS6159395A - Drive control circuit for plasma display panel - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to plasma displays (Plasma 85P).
The present invention relates to an erase pulse generation circuit for an AC type FDP drive circuit having a memory function.

For AC type PNP, there are two orthogonal electrodes: vertical and horizontal. There's something about it. A positive and negative pulse voltage V1 (maintenance voltage) that alternates in parallel is applied to all of these cells through the X and Y electrodes.

At this Vl, no cell can start discharging, but the cell has the characteristic of sustaining a discharge caused by some means. And one cell C4j ((=1~Jō.

/=1~%), the voltage (write voltage -) that exceeds the discharge threshold through the electrodes Xt and Xjf belonging thereto and has a time width necessary for discharge growth is converted into a sustaining voltage.

Or if you add it to that gap, the cell will start discharging. - After that, the cell that started carrying discharge has a maintenance voltage of V
Discharge can be repeated with only an amplitude of 8. This is because an internal voltage (wall voltage) equivalent to the discharge is generated, and this is added to the alternately inverted sustain voltage with the same polarity, and even the amplitude of the sustain voltage effectively exceeds the threshold for starting discharge. be. Erasing a discharge-lit cell is achieved by applying an erasing pulse with a voltage and duration that causes a discharge in the cell, but rather consumes the wall charge.

The present invention is directed to a drive circuit for such an AC type PDP.

[Conventional technology]

FIG. 4(A) shows the entire configuration diagram of a conventional PDP, in which 1 is a panel equipped with the above-mentioned 11 cells. Alternating waveforms of a sustaining voltage Vs (Σ90V) are applied to the electrodes in opposite phases.

Further, the above-mentioned write voltage Vw (=150T/) is supplied from the sustain driver 3 on the Y-axis side. Erasing is then carried out by applying a pulse with a width narrower than the normal sustaining pulse, for example about 1 μs, to the selected cell to cause a cell discharge, but rather to consume the wall charge. It is done.

Figure 4 (E) shows an example of a sustain driver.
A transistor Q1 that pulls up the output terminal 8 to a sustaining voltage V8 and a transistor Q2 that pulls it down to the ground potential (OV) are provided. Then, the rising multi-signal of the sustaining voltage supplied to the input terminal 6 (
Since the p-type transistor Q1 is a negative pulse, the transistor Q1 turns on and the sustaining voltage V1 is output. - Applying a falling multi-signal of the maintenance voltage supplied to the terminal 7 (here, Q2 is a positive pulse because it is an out-of-town type) turns the transistor Q2 into an O state.
The ground potential (OV) is output from Nl. In this way, pulses of a predetermined width are repeatedly output to the output terminal 8 of the sustain driver with potential changes from V to Va.

Conventionally, the erase pulse has been generated by combining a multivibrator with a high voltage switching circuit such as the above-mentioned sustain/driver. An example of the circuit is shown in Fig. 3. Conventionally, the erase pulse width is adjusted by using a monostable multivibrator and adjusting the CB time constant to 0.7 to 1.2μ.
The erasing pulse width output from the high voltage switching circuit 10 was determined within the range of s. However, with this method,
It has the disadvantage that the erasing pulse width fluctuates due to voltage value fluctuations and temperature fluctuations. For example, depending on the temperature coefficient of C'C'H, a fluctuation of about 0.1 μs to 0.2 μs can occur in the pulse width.

[Problem that the invention seeks to solve]

As mentioned above, in the prjp drive circuit, it is necessary to generate a highly accurate pulse width with a narrow pulse width (1 to 2 μs or less), but conventional methods such as a multivibrator using C and H time constants are However, the pulse width fluctuates due to voltage and temperature fluctuations, making it difficult and difficult to control with high precision. Furthermore, since the erasing characteristics of a PDP vary greatly depending on the pulse width of the erasing pulse, it has been impossible to widen the operating voltage range of conventional panels.

[Means for solving problems]

The present invention controls the adjustment of the erasing pulse width using only a visual circuit, and makes it possible to adjust the 1ζ pulse width stably against voltage and temperature fluctuations. As the clock input of the register, for example, the falling υ signal of the erase pulse generation is connected to the data input of the shift register, and the falling signal of the erase pulse is delayed by the shift register and applied to the high voltage switching circuit, and the pulse width is control.

〔Example〕 FIG. 1 shows an erase pulse generating circuit according to an embodiment of the present invention.

The erase pulse generation circuit includes a terminal 12 from an IC (not shown).
The erase pulse rising edge signal Esp is input to the terminal 15.
An erase pulse falling multi-signal Edown is applied to. The terminal 12 is connected to the data output terminal of the N-stage shift register 11, and appropriate output terminals 51 (4-1 to N) are connected to the sole up signal input terminal 6 of the high voltage switching circuit 1o. On the other hand, the erase pulse falling signal Ed- is directly connected to the pull-down signal input terminal 7 of the high voltage switching circuit 10. The output terminal 8 of the high voltage switching circuit 10 is connected to the electrode (X in this case) of the panel. Further, a high frequency clock CLK for control is input to the clock terminal C of the shift register 11.

The operation of the above circuit is such that the erase pulse rising signal Eup and the erase pulse falling signal Hjdowth are input to the terminals 12 and 15 with a predetermined time difference from an IC (not shown). Ikp is input to the D terminal of the shift register 11 and is shifted by high frequency CLK. Then, an output terminal Ss to which an appropriate delay time (shift amount) is applied: ((=1 to N) is selected and an erase pulse rising No. Hasp is the input, and in this case transistor Q1 is p, so it is a negative pulse), E
When the voltage UP falls, the transistor Q1 turns ON and outputs the erase voltage Va (in this example, the same level as the sustaining voltage Va) to the output terminal 8 and applies it to the panel. On the other hand, when the erase pulse falling signal Edown is input from the terminal 13 to the pull-down signal input terminal 7 of the high voltage switching circuit 10, the transistor Q2 outputs an on-state ground potential (OV) to the terminal 8, which is applied to the panel.

Before the actual erase pulse is generated in the circuit of FIG. 1, the potential of the output terminal 8 is approximately at the level of the sustaining voltage V8, as shown in the timing chart of FIG. Here, the X electrode is in a floating state, and the transistors Ql and Q2 are turned off. In this state, first, erase pulse falling multiple signal H is applied to terminal 7.
d6w% is applied, and the output Xo%t of the terminal 8 falls from V1 to 0 as shown in FIG.

Next, the erase pulse rising edge signal Eup (Zup) delayed by the shift amount td of the shift register from the predetermined pulse interval t1 (interval between A7dows and l5bp) is applied to the terminal 7, and the output Xo%t becomes the rising edge signal Eup (Zup). →Va. As a result, an erase pulse with a pulse width of +L2-t++td is obtained.

Figure 5 shows the voltage waveform vX of the X electrode of the panel and the waveform 1/y of the Y electrode.
# and are in opposite phase to each other. During writing, a write voltage ->Va is applied, and during erasing, the above-mentioned narrow erase pulse with the pulse width t2 is generated at Vx. Then, when viewed from the cell of the panel, vY-vx is applied to the cell.

Figure 6 shows Vz H'Fy r and VY-V of PDP drive.
In another example of the waveform of By adjusting the Edow% (D Edosun side) using a shift register, the required erasing pulse width t5 can be obtained with high precision.

In the present invention, the output terminal 5 of the shift register ((1-1 to
By selecting and connecting N), the required delay Wf of the erase pulse rising multiple signals or erase pulse falling multiple signals can be easily performed. Moreover, since it is based on high-speed locking shift register shifting, it is extremely stable against voltage and temperature fluctuations.

Therefore, an extremely accurate erase pulse width generator is obtained.

〔Effect of the invention〕

According to the present invention, as described above, adjustment of the erase pulse width can be controlled only by a logic circuit, and the pulse width can be adjusted with high precision without being affected by voltage or temperature fluctuations. As a result, the operating voltage of the PDP It has a wide range and can guarantee stable operation.

Furthermore, depending on the FDP panel, there are variations in the optimal erasing pulse width after completion, but according to the present invention, by selecting the output bin of the shift register, it is possible to easily set the optimal erasing pulse width. Can be set.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a timing diagram of a circuit of an embodiment of the invention, Fig. 3 is a circuit diagram of a conventional erase pulse generation circuit, and Fig. 4 (A) is a PDP. Configuration diagram, (
B) is a circuit diagram of the sustain driver, FIG. 5 is a waveform diagram of the drive voltage of the PDP, and FIG. 6 is a waveform diagram of the drive voltage of other PDPs. 6... (pull-up signal) input terminal 7... (pull-down signal) input terminal 8... (high voltage switching circuit output) terminal 10...
・High voltage switching circuit 11...shift register

Claims (1)

[Claims] Connect the X address driver and Y electrode to the X electrode and Y electrode of the panel.
The erase pulse is applied in a plasma display panel drive circuit that applies a write pulse that provides the discharge start voltage of the cell, an alternating sustain pulse that maintains the discharge, and an erase pulse with a required narrow width through an address driver. The generating circuit connects one of an erase pulse rising signal or an erase pulse falling signal given at predetermined time intervals to a data input of a shift register, connects a high speed clock signal to a control terminal of the shift register, An output terminal of a desired stage of the shift register is connected to one of a pull-up signal input terminal or a pull-down signal input terminal of the high-voltage switching circuit, and the other is connected to the other of the erase pulse rising signal or erase pulse falling signal. A drive control circuit for a plasma display panel, characterized in that: