JPS6157611U - - Google Patents

Info

Publication number
JPS6157611U
JPS6157611U JP14106284U JP14106284U JPS6157611U JP S6157611 U JPS6157611 U JP S6157611U JP 14106284 U JP14106284 U JP 14106284U JP 14106284 U JP14106284 U JP 14106284U JP S6157611 U JPS6157611 U JP S6157611U
Authority
JP
Japan
Prior art keywords
data transfer
transmitting
control data
array antenna
receiving devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14106284U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14106284U priority Critical patent/JPS6157611U/ja
Publication of JPS6157611U publication Critical patent/JPS6157611U/ja
Pending legal-status Critical Current

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Landscapes

  • Variable-Direction Aerials And Aerial Arrays (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の送受信装置の構成図、第2図は
フエーズドアレイアンテナの構成図、第3図はこ
の考案による送受信装置に内蔵する制御回路部の
構成図である。 図においては、1は送受信装置、2は送信用増
幅器、3は受信用増幅器、4はサーキユレータ、
5は移相器、6は高周波入出力端子、7は高周波
線路、8は放射素子、9は制御回路部、10はイ
ンターフエースコネクタ、11はデータ入力端子
、12はデータ出力端子、13はデータ転送回路
、14はシリアルデータ転送装置、15は制御回
路、16は入出力データ比較回路、17はAND
回路、18はデータ入力ピン、19はデータ出力
ピンである。なお、図中同一あるいは相当部分に
は同一符号を付して示してある。
FIG. 1 is a block diagram of a conventional transmitting and receiving apparatus, FIG. 2 is a block diagram of a phased array antenna, and FIG. 3 is a block diagram of a control circuit built into the transmitting and receiving apparatus according to the invention. In the figure, 1 is a transmitting/receiving device, 2 is a transmitting amplifier, 3 is a receiving amplifier, 4 is a circulator,
5 is a phase shifter, 6 is a high frequency input/output terminal, 7 is a high frequency line, 8 is a radiation element, 9 is a control circuit section, 10 is an interface connector, 11 is a data input terminal, 12 is a data output terminal, 13 is data Transfer circuit, 14 is a serial data transfer device, 15 is a control circuit, 16 is an input/output data comparison circuit, 17 is an AND
18 is a data input pin, and 19 is a data output pin. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 多数の送受信装置を任意の面内に配列したアン
テナと、上記送受信装置の動作制御用のデータ転
送装置と、上記データ転送装置よりの制御データ
を上記の各送受信装置に与えるための制御データ
転送回路とで構成されるフエーズドアレイアンテ
ナにおいて、上記制御データ転送回路からの上記
制御データによつて上記送受信装置を駆動する制
御回路を並列構成して、上記送受信装置に内蔵し
たことを特徴とするフエーズドアレイアンテナ。
An antenna in which a large number of transmitting and receiving devices are arranged in an arbitrary plane, a data transfer device for controlling the operation of the transmitting and receiving devices, and a control data transfer circuit for providing control data from the data transfer device to each of the transmitting and receiving devices. A phased array antenna comprising: a phased array antenna comprising: a control circuit configured in parallel to drive the transmitter/receiver according to the control data from the control data transfer circuit and built into the transmitter/receiver; Zudo array antenna.
JP14106284U 1984-09-18 1984-09-18 Pending JPS6157611U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14106284U JPS6157611U (en) 1984-09-18 1984-09-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14106284U JPS6157611U (en) 1984-09-18 1984-09-18

Publications (1)

Publication Number Publication Date
JPS6157611U true JPS6157611U (en) 1986-04-18

Family

ID=30699407

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14106284U Pending JPS6157611U (en) 1984-09-18 1984-09-18

Country Status (1)

Country Link
JP (1) JPS6157611U (en)

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