JPS6156496A - Board for hybrid integrated circuit device - Google Patents

Board for hybrid integrated circuit device

Info

Publication number
JPS6156496A
JPS6156496A JP17871684A JP17871684A JPS6156496A JP S6156496 A JPS6156496 A JP S6156496A JP 17871684 A JP17871684 A JP 17871684A JP 17871684 A JP17871684 A JP 17871684A JP S6156496 A JPS6156496 A JP S6156496A
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
circuit device
board
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17871684A
Other languages
Japanese (ja)
Inventor
冨士 昌章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17871684A priority Critical patent/JPS6156496A/en
Publication of JPS6156496A publication Critical patent/JPS6156496A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は混成集積回路装置用基板で、高集積度で高精度
な多層配線基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a board for a hybrid integrated circuit device, and relates to a highly integrated and highly accurate multilayer wiring board.

〔従来技術〕[Prior art]

近年、電子機器の大規模、高機能化が進むに従ってこれ
らの機器に使用される混成集積回路装置にはますます、
小型、高集積度が要求されて来ている。小型化し、集積
度を上げるために混成集積回路装置用の基板としては、
一般にセラミック多層配線基板が用いられる。これらの
配線基板は通常、アルミナグリーンシート上に厚[4体
層と厚膜絶縁層とを印刷し、焼成した後、碑体表面層に
メッキ処理を施して製造しているため、次のような欠点
があった。
In recent years, as electronic devices have become larger and more sophisticated, the hybrid integrated circuit devices used in these devices have increasingly become
There is a growing demand for smaller size and higher integration. In order to reduce the size and increase the degree of integration, the substrate for hybrid integrated circuit devices is
Generally, a ceramic multilayer wiring board is used. These wiring boards are usually manufactured by printing a thick layer and a thick insulating layer on an alumina green sheet, baking it, and then plating the monument surface layer. There was a drawback.

イ)焼成時の基板の収縮誤差のために、パターン精度が
得られない。
b) Pattern accuracy cannot be obtained due to shrinkage error of the substrate during firing.

(ロ)厚膜導体を印刷しているため、導体幅が狭くて平
担なパターンを得ることが難かしい。
(b) Since thick film conductors are printed, the conductor width is narrow and it is difficult to obtain a flat pattern.

(ハ)メッキ膜はニッケル、金等の2層構造をとるコト
カ多く、プロセスも複雑で、高価格とな)やすい。
(c) Many plating films have a two-layer structure of nickel, gold, etc., making the process complicated and expensive.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記欠点を除去し、平担で、高密度、
高精度のパターンを有する混成集積回路装置用基板を低
価格で提供するととKある。
The purpose of the present invention is to eliminate the above-mentioned drawbacks, to provide a flat, high-density,
K provides a substrate for a hybrid integrated circuit device having a highly accurate pattern at a low price.

〔発明の構成〕[Structure of the invention]

本発明の混成集積回路装置用基板は、アルミナグリーン
シート上に、厚膜導体層と厚膜絶縁層とを交互に印刷し
て焼成した後、薄膜導体及び薄膜抵抗等を付着させ、回
路形成して構成する。
The substrate for a hybrid integrated circuit device of the present invention is produced by alternately printing thick film conductor layers and thick film insulating layers on an alumina green sheet and baking them, and then attaching thin film conductors, thin film resistors, etc. to form a circuit. Configure.

〔実施例の説明〕[Explanation of Examples]

次に本発明による実施例を図面を用いて説明する。第1
図は本発明による混成集積回路装置用基板の断面図及び
その製造方法を示す図である。
Next, embodiments according to the present invention will be described with reference to the drawings. 1st
The figure is a cross-sectional view of a substrate for a hybrid integrated circuit device according to the present invention and a diagram showing a method of manufacturing the same.

アルミナグリーンシー)IKタングステン擲体層2.3
及び4と、アルミナ絶縁層5.6及び7とを交互にスク
リーン印刷する。このとき絶縁層5.6.7には、各導
体層の電気的接続をとるためのスルーホール8が開けら
れている。次に導体の酸化を防ぐため、還元性雰囲気で
、焼成して厚膜多層配線基板を形成する(第1図A)。
Alumina green sea) IK tungsten shell layer 2.3
and 4 and alumina insulating layers 5, 6 and 7 alternately by screen printing. At this time, through holes 8 are opened in the insulating layers 5, 6, 7 for electrically connecting the respective conductor layers. Next, in order to prevent oxidation of the conductor, it is fired in a reducing atmosphere to form a thick film multilayer wiring board (FIG. 1A).

その後、この基板上にニクロム及び金薄膜9をスパッタ
法又は蒸着法によシ付着させる(第1図B)。次K。
Thereafter, a thin nichrome and gold film 9 is deposited on this substrate by sputtering or vapor deposition (FIG. 1B). Next K.

1       フォトエツチング法によシ、薄膜導体
9をエツチングして所望のパターンを形成しく第1図C
)、混成集積回路装置用基板を製造した。
1. Etch the thin film conductor 9 to form a desired pattern using a photo-etching method.
), manufactured a substrate for a hybrid integrated circuit device.

〔発明の効果〕 か〃・る方法により形成された、混成果槓回路!!装置
用基板は、アルミナグリーンシート上に厚膜を印刷し、
焼成した後、最上層に薄膜導体層を形成しているので、
基板の収縮誤差がなくて精度が、高く、平担で、高密度
のパターンが得られ、又、複雑なメッキプロセスも心安
としないので、安価で、信頼性の高いものとなった。
[Effects of the invention] A hybrid output circuit formed by the method! ! The device substrate is made by printing a thick film on an alumina green sheet.
After firing, a thin film conductor layer is formed on the top layer, so
Since there is no shrinkage error of the substrate, a highly accurate, flat, and high-density pattern can be obtained, and since a complicated plating process is not necessary, it is inexpensive and highly reliable.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(5)〜(qは本発明の一実施例の製造工程を説
明する断面図である。 なお、図において、1・・・・・・アルミナグリーンシ
ー)、2,3.4・・・・・・厚膜導体層、5,6.7
・・・・・・厚膜絶縁層、8・・・・・・スルーホール
、9・・・・・・薄膜導体層、である。
FIG. 1 (5) to (q are cross-sectional views explaining the manufacturing process of an embodiment of the present invention. In the figures, 1...Alumina green sea), 2, 3.4, ... Thick film conductor layer, 5, 6.7
. . . thick film insulating layer, 8 . . . through hole, 9 . . . thin film conductor layer.

Claims (1)

【特許請求の範囲】[Claims]  アルミナグリーンシート上に厚膜導体層と厚膜絶縁層
とを交互に印刷し、焼成して形成した多層配線基板上に
薄膜導体及び薄膜抵抗等を付着させて回路形成したこと
を特徴とする混成集積回路装置用基板。
A hybrid circuit characterized in that a circuit is formed by depositing a thin film conductor, a thin film resistor, etc. on a multilayer wiring board formed by alternately printing thick film conductor layers and thick film insulating layers on an alumina green sheet and baking them. Substrate for integrated circuit devices.
JP17871684A 1984-08-28 1984-08-28 Board for hybrid integrated circuit device Pending JPS6156496A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17871684A JPS6156496A (en) 1984-08-28 1984-08-28 Board for hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17871684A JPS6156496A (en) 1984-08-28 1984-08-28 Board for hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6156496A true JPS6156496A (en) 1986-03-22

Family

ID=16053312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17871684A Pending JPS6156496A (en) 1984-08-28 1984-08-28 Board for hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6156496A (en)

Similar Documents

Publication Publication Date Title
JPH06503680A (en) Manufacturing method of fine wiring pattern with impedance matching
JPS6156496A (en) Board for hybrid integrated circuit device
JP2556065B2 (en) Manufacturing method of electronic component with built-in resistor
JPH0363237B2 (en)
JP2530008B2 (en) Wiring board manufacturing method
JPH0744343B2 (en) Multilayer substrate with built-in resistors
JPH0265194A (en) Manufacture of printed wiring board with thick film element
JPS5864093A (en) Multilayer circuit board
JPS6081899A (en) Method of forming ceramic substrate
JPS6154657A (en) Hybrid integrated circuit
JPS5812308A (en) Method of producing thick film resistance circuit substrate
JPH02154496A (en) Manufacture of circuit board
JPH01257397A (en) Metal printed board
JP2569716B2 (en) Method of manufacturing multilayer thick film IC substrate
JPS5918843B2 (en) Resistor circuit board and its manufacturing method
JPS60102763A (en) Multilayer thick film hybrid integrated circuit substrate
JPS58202503A (en) Method of producing thick film resistor
JPS6045095A (en) Method of producing thick film multilayer board
JPH04180691A (en) Manufacture of ceramic circuit board
JPS6185896A (en) Multilayer circuit board
JPS593993A (en) Method of producing thin film circuit board
JPH08255969A (en) Printed-circuit board device
JPH0225276B2 (en)
JPS59161093A (en) Thick film circuit board
JPS6144453A (en) Manufacture of hybrid ic