JPS615618A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To remove evil influence of a glitch signal, etc., by varying the threshold value voltage of an inverter circuit through a driving circuit which has a bootstrap function according to an input signal voltage or output voltage. CONSTITUTION:An output Out varies from ''0'' to ''1'' in the process of the transition of an input In from ''0'' to ''1''. This signal is received by a transistor (TR) 7 at its gate and a node N11 varies from ''1'' to ''0''. Then, a TR2 decreases in (gm) and the threshold voltage of the inverter I1 decreases. Therefore, ''1'' of the input In is recognized securely. Thus, the circuit threshold voltage of the inverter is varied without being fixed, so the evil influence of the glitch signal, etc., is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit having a MOS configuration suitable as a drive circuit having a Pootstrap function.

[Technical background of the invention and its problems]

FIG. 5 shows a conventional drive circuit with a gate strap function. This circuit is a MOS transistor Trl ~Tr
y (Trl, Tr4 to Tr@ are of N-channel enhancement type, Tr4 and yTr3 are of desolation type), capacitor C1 and resistance R. The operation of this circuit is such that when the input signal In'0# level changes to 'l'' level, the current flows through the transistors Tr3+Tr4.
, ar flows through the capacitor C and the transistor Tr5, and charges are accumulated in the capacitor C. transistor T
When the node Nl becomes 'Om with a delay of inverter I, which is greater than rl + Trl, the transistor Tr@ turns off and the node N goes up to the power supply voltage vcc side.
3 is the node N that separates the accumulated electricity from the mother C! Since the stain pressure becomes high, the transistor Tr6 operates as a triode, and the power supply voltage VCC is obtained at the output terminal Out. on the other hand,
When the input signal ■Y is 0#, the transistor Tr5 is on, so that the ground level is obtained at the output terminal Out. In this way, this circuit can reduce current consumption while keeping the output terminal O
The potential of t is made to swing fully from the power supply voltage VCC to the ground level.

However, the circuit shown in FIG. 5 has the following problems (a) and ←). (b) Input signal, from 0” to 1#
In the process of changing to , a glitch signal (
When a (original expected signal waveform) enters, the signal enters. As the current becomes low, the current is input through the transistor Tr3.■
In order to escape to the U side, the '41'' (high) potential of the output terminal Out is
Power supply voltage V. .

The value is reduced by the threshold voltage VTH of the transistor Tr6. As a result, the operating speed of an integrated circuit using this type of circuit is lowered, or a sufficient VCC potential cannot be obtained at the output terminal Out. (b) If the slope of the rise/fall time of the input signal of the amplifier at the front stage of the circuit in Figure 5 is long,
Near the threshold voltage of the circuit shown in the figure, a state occurs in which the output signal at the output terminal Out is neither "1" (high) nor 0" ([3). This is because the inverter! ″
This is because the transistor Tr5 is in an intermediate state where it is neither on nor off. At this time, by using the circuit shown in FIG. 5 in the output stage of the decoder circuit, mutual interference between selected memory cells may occur.

The cause of the above-mentioned conventional problem is that the circuit threshold voltage of the inverter 1 (voltage value determined by the ratio of the characteristics β to gm of the transistors Trt+Tr2) is constant.

[Purpose of the invention]

? The present invention has been made in view of the above-mentioned circumstances, and solves the above-mentioned conventional problems by changing the circuit threshold voltage of the inverter of the puto-sotra/f circuit according to the input signal voltage or output voltage. The present invention aims to provide an improved semiconductor integrated circuit.

[Summary of the invention]

In the present invention, in order to change the threshold voltage of the inverter of the above-mentioned Pootstrap circuit, for example, the mutual conductance of the MO8 transistor on the load side of the inverter, which is composed of the MOB transistor on the load side and the MO8 transistor on the drive side, is changed. gm may be changed depending on the input voltage applied to the drive-side MO8 transistor or the output voltage of the Pootstrap circuit. That is, when the input voltage is at a high level, the gm of the MO8 transistor on the load side is made small, and when the input voltage is at a low level, the gm is made large. This eliminates the need for the above inverter,
The circuit threshold voltage determined by the characteristic β ratio of the transistor has a so-called hysteresis characteristic, which is low when the input voltage is at a high level and high when the input voltage is at a low level.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings. Figure 1,
Fig. 2 is a circuit diagram showing each embodiment, but since this is an example in which there is no correspondence with that in Fig. 5, corresponding parts are given the same reference numerals and explanations are omitted. Let me explain the points. In Figure 1, it is enhanced
The O8 transistor Tr7 and the delusion type MOS transistor Trs are connected in series between the power supply VCC and the ground, and the transistor 'rr2t is connected between the transistor Try @Tr@
connected to the gate of Trl and f-) of transistor Try.
Connect to the output terminal Out.

In Fig. 2, enhancement transistor) N-channel MO8 transistor Tr17, depressi
r111 is the power supply Vcc and the transistor Trl.

A transistor Tr17* is connected in series between T11 and T11.
Transistor Tr! between Tr11! and transistor Try
H, and the gate of the transistor Tr17 is connected to the input terminal I! Connect to 1.

In the circuit shown in Figure 1, the input In is from 0'' to N1''
In the process of increasing, the output Out also changes from N0'' to °1''. The gate of the transistor Tr7 receives this signal, and the node Nll changes from N1'' to '0#.Then, the gm of the transistor Tr2 decreases from dog to small, and the circuit threshold of the inverter I increases. The value voltage decreases.Therefore, "1" of the input In is reliably recognized.

In the circuit shown in FIG. 2, the potential of the node N111 decreases as the transistors Trl and Tr17 detect the process in which the input goes from O'' to N1''. The gate of the transistor Tr2 receives this potential, and the gm of the transistor Tg decreases. Then, the circuit threshold voltage of the inverter Il drops, so that the input "1" is reliably recognized.

The effect on the input glitch signal of FIG. 1 or 2 is as follows. In other words, the amount of charge charged to the capacitor and the capacitor C is supplied by the potential difference between the input In1 and the output Out when the input signal In rises. Ha, Impatae! Glitch signal due to low circuit threshold voltage VTH.

signal is easily sensed, and the voltage of the output Out decreases. On the other hand, in the circuit of the present invention, since the circuit threshold voltage is high, the glitch signal is not sensed, and the voltage of the output Out is stable. , occurs until .

Also, the input signal construction shown in Figure 1 or Figure 2. The effect when the slope of the rising/falling time is long is as follows.

That is, as shown in FIG. 4, the input signal ■. The gate voltage of the transistor Trz is input. is applied in the opposite phase of the inverter Il, and the circuit threshold voltage of the inverter Il is the node Nll
Or it changes following the voltage change of N1m. This allows the input signal In to be input to the inverter I more than in the conventional system shown in FIG.

Since the time during which the output voltage remains near the circuit threshold voltage becomes shorter, the period during which the output Out is neither at a high level nor at a low level becomes extremely short.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit which has remarkable effects on green and tea signals and when the slope of the rising/falling time of an input signal is long.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams showing an embodiment of the present invention, FIGS. 3 and 4 are waveform diagrams for explaining the operation of the circuit, and FIG.
The figure shows a drive circuit diagram with a conventional bootstrap function.
FIG. 6 is a diagram of the input signal waveform. Trl+-+Try +Tr17+TrH-MOS
) Lanzosta, C... Capacitor, ■! ...Inverter. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 5 Figure 6

Claims (2)

[Claims] (1) First MOS transistor and second MOS transistor between power supplies
the first MOS in which S transistors are connected in series and the source of the first MOS transistor and the input signal are supplied;
a bootstrap circuit in which a capacitor is provided between the gate of the S transistor and an inverter is connected between the input terminal to which the input signal is supplied and the gate of the second MOS transistor; 1. A semiconductor integrated circuit comprising: means for detecting a source voltage of a transistor and changing a circuit threshold voltage of the inverter. (2) When the voltage of the input signal becomes high, the circuit threshold voltage of the inverter becomes low, and when the voltage of the input signal becomes low, the circuit threshold voltage of the inverter becomes high. A semiconductor integrated circuit according to claim 1.