JPS6155767A - Input output bus connection change-over device - Google Patents

Input output bus connection change-over device

Info

Publication number
JPS6155767A
JPS6155767A JP59177805A JP17780584A JPS6155767A JP S6155767 A JPS6155767 A JP S6155767A JP 59177805 A JP59177805 A JP 59177805A JP 17780584 A JP17780584 A JP 17780584A JP S6155767 A JPS6155767 A JP S6155767A
Authority
JP
Japan
Prior art keywords
processor
switch
over
bus connection
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59177805A
Other languages
Japanese (ja)
Inventor
Yoshiji Morioka
森岡 義嗣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Hokushin Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hokushin Electric Corp filed Critical Yokogawa Hokushin Electric Corp
Priority to JP59177805A priority Critical patent/JPS6155767A/en
Publication of JPS6155767A publication Critical patent/JPS6155767A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Abstract

PURPOSE:To attain I/O bus connection change-over of a load sharing mutual back-up system with simple construction by providing plural switch parts, a manual changing-over means and an automatic changing-over means, and changing over switchs in accordance with a trouble generating condition. CONSTITUTION:When a processor 1a is at fault, an automatic changing-over means 5 detects the trouble and connects a switch part 3a to a side (b). Thus, respective I/O ports 2a and 2b are connected to a processor 1b. When the processor 1b is at fault, the means 5 detects this fault and connects a switch 3b to a side (a). Thus, I/O ports 2a and 2b are connected to the processor 1a. A manual changing-over switch 4 is connected to a C terminal at the time of automatic changing-over and when the processor 1a or 1b is selected manually, a manual knob 40 is turned to a side A or B, connected and changed over. In such a way, by providing the means 4 and 5 and switches 3a and 3b, I/O bus connection changeover of a load sharing mutual back-up system can be attained with simple construction.

Description

【発明の詳細な説明】 (産業上の利用分野) 、本発明は、プロセッサを二重化して高信頼度構成とし
たシステムにおける入出力(以下仁れを170と略す)
バス接続切換装置に関するものである。更に詳しくは、
本発明は、第1.第2のプロセッサと、第1.第2のI
10ポートとを備え、通常の場合、第1のプロセッサと
第1のVOボート、第2のプロセッサと第2のVOボー
トの接続で動作するが、例えば第1のプロセッサが故障
時罠は、第2のプロセッサと第1.第2のI10ボート
の接続となり、また、第2のプロセッサが故障時区は、
第1のプロセッサと第1.第2のI10ボートの接続と
なるような、所謂ロードシェア相互バックアップ方式の
■んバス接続切換装置に関するものである。
[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an input/output system (hereinafter referred to as 170) in a system with a highly reliable configuration by duplicating processors.
This invention relates to a bus connection switching device. For more details,
The present invention has the following features: 1. a second processor; second I
Normally, it operates by connecting the first processor and the first VO boat, and the second processor and the second VO boat. 2 processors and the first . A second I10 boat is connected, and if the second processor fails,
a first processor; This invention relates to a so-called load share mutual backup type bus connection switching device that connects a second I10 boat.

(従来の技術) 従来、スタンバイ方式のバックアップに対応した二重化
制御が考えられていたが、ロードシェア相互バックアッ
プ方式の凶バス接続切換装置はこれまでなかった。スタ
ンバイ方式では、常にどちらか一方にしか、I10バス
の制御が許されていないので、ロードシェア方式がとれ
なかったのである。
(Prior Art) Duplex control compatible with standby backup has been considered in the past, but there has been no load sharing mutual backup backup bus connection switching device up to now. In the standby system, only one bus is allowed to control the I10 bus at any given time, so a load sharing system cannot be used.

(発明が解決しようとする問題) 本発明は、このような従来技術に訃ける問題点に鑑みて
なされたもので、その目的は、簡単な構成で、ロードシ
ェア相互バックアップ方式のI10バス接続切換装ff
1t実現しようとするものである。
(Problems to be Solved by the Invention) The present invention has been made in view of the problems that plague the prior art, and its purpose is to provide I10 bus connection switching using a load sharing mutual backup method with a simple configuration. outfit ff
This is what we are trying to achieve.

(問題点を解決するための手段) このような目的t−達成するための本発明の構成は、第
1.第2のプロセッサと、第1.第2の入出力ポートと
、前記第1の入出力ボートと前記第1、第2のプロセッ
サとのバス接続切換えを行なう第1のスイッチ部と、前
記第2の入出力ポートと前記第1.第2のプロセッサと
のバス接続切換えを行なう第2のスイッチ部と、前記第
1.第2のスイッチを手動によって切換動作させる手動
切換手段と、前記第1.第2のプロセッサの正常異常を
判断し前記各プロセッサが正常な場合は第1の入出力ボ
ートは第1のプロセツサ側第2の入出力ボートは第2の
プロセッサにそれぞれ接続されるように1g1.第2の
スイッチを切にかえるとともに、前記第1.第2のプロ
セッサのいずれか一方が異常となった場合正常のプロセ
ッサに前記第1、第2の入出力ポートがともに接続され
るように前記第1.第2のスイッチを切換る自動切換手
段とを備えた点に特徴がある。
(Means for Solving the Problems) The configuration of the present invention for achieving such objective t- is as follows. a second processor; a second input/output port, a first switch section for switching bus connections between the first input/output port and the first and second processors; a second input/output port and the first switch section; a second switch section for switching the bus connection to the second processor; manual switching means for manually switching the second switch; and a manual switching means for manually switching the second switch; It is determined whether the second processor is normal or abnormal, and if the respective processors are normal, the first input/output port is connected to the first processor side, and the second input/output port is connected to the second processor. At the same time as turning off the second switch, the first switch is turned off. If either one of the second processors becomes abnormal, the first and second input/output ports are both connected to the normal processor. It is characterized in that it includes automatic switching means for switching the second switch.

(実施例) 纂1■は、本発明に係る装置の一例を示す構成プロ、り
図である。この図において、1aは第1のプロセッサ、
11)は第2のプロセッサ、2昌は第1のX10ノボー
ト、2bは第2のVOポート、3aは各プロセッサとI
10ボートとの間に設けられ、第1のI10ポート2龜
と第1.第2のプロセッサ1m、1bとのバス接続切換
えを行なう第1のスイッチ部、3bは同じく纂2のX1
0ポー)2b七第1.第2のプロセッサ1ajbとのバ
ス接続切換えを行なう第2のスイッチ部である。4は第
1.第2のスイッチ部5m、5b 1に手動によって切
換動作させる手動切換手段、5は第1.第2の各プロセ
ッサ1ajbの動作が正常か異常かを監視する手段を有
し、−ずれが一方のプロセッサが異常と判断され九場合
、正常動作をしているプロセッサ側に第1.第2のI1
0ホー) 1m、1bの両方が接続されるように、第1
゜第2のスイッチ部5m、5b f切換える自動切換手
段でるる。
(Example) Summary 1 is a diagram showing an example of the configuration of an apparatus according to the present invention. In this figure, 1a is a first processor;
11) is the second processor, 2sho is the first X10 port, 2b is the second VO port, 3a is each processor and I
10 boats, the first I10 port 2 and the first I10 port. The first switch section 3b switches the bus connection with the second processors 1m and 1b, and the X1
0 po) 2b 7th 1. This is a second switch section that performs bus connection switching with the second processor 1ajb. 4 is the first. Manual switching means for manually switching the second switch portions 5m and 5b 1; It has a means for monitoring whether the operation of each of the second processors 1ajb is normal or abnormal, and if one of the processors is determined to be abnormal, the processor that is operating normally is replaced with the first processor. second I1
0ho) so that both 1m and 1b are connected.
゜Second switch section 5m, 5b There is an automatic switching means for switching f.

このように構成した装置の動作上次に説明する。The operation of the apparatus configured as described above will be explained next.

通常、第1.g2のプロセッサ1i、lbが正常に動作
している状態では、i第1、第2のスイッチ部3畠。
Usually, the first. When the processors 1i and lb of g2 are operating normally, the first and second switch sections 3 and 3 of the i first and second switch sections 1b and 1b of g2 are in normal operation.

5bは、いずれも1側に接続嘔れ、第1のプロセッサ1
&からのバスは第1のI10ポー)2mに、第2のプロ
セッサ1bからのバスは7g2のI10ボー)2blC
それぞれ接続されている。
5b are both connected to the 1 side, and the first processor 1
The bus from
each connected.

いま、第1のプロセッサ1aが故障すると、自動切換手
段5は、この故障を検出し、第1のスイッチ部3aをb
側に接続する(第2のスイッチ部5bの接続はその11
)。これによって、第2のプロセッサ1bに各Iハボー
) 2m、2bが接続される。また、第2のプロセッサ
1bが故障すると、自動切換手段5はこれを検出しsw
L2のスイッチ部5bt−b@に接続する(第1のスイ
ッチ部3aの接続はそのtま)。
Now, if the first processor 1a fails, the automatic switching means 5 detects this failure and switches the first switch section 3a to b.
side (the connection of the second switch part 5b is 11)
). As a result, each I hub (2m, 2b) is connected to the second processor 1b. Further, when the second processor 1b fails, the automatic switching means 5 detects this and switches
It is connected to the switch section 5bt-b@ of L2 (the first switch section 3a is connected until then).

これKよって、第1のプロセッサ1aK各I10ポート
2へ2bが接続される。
2b is thereby connected to each I10 port 2 of the first processor 1aK.

このような動作によって、ロードシェア相互バックアッ
プ方式のx10バス接続の切換えが行なわれる。
By such an operation, switching of the x10 bus connection in the load sharing mutual backup method is performed.

なお、第1.第2のプロセッサの両方が異常となった場
合、第11第2のスイッチ部3m、 5bは埴ずれもa
側に接続される。
In addition, 1. If both of the second processors become abnormal, the 11th and 2nd switch sections 3m and 5b will be damaged.
connected to the side.

また、手動切換スイ25盲、自動切換時、Ci子に接続
されるが、第1又は第2のプロセッサを手動にて選択す
る場合、手動つまみ40をA側又はB側に操作して、接
続切換えを行なう。
In addition, when the manual switching switch 25 is blind, it is connected to the Ci when switching automatically, but if you want to manually select the first or second processor, operate the manual knob 40 to the A side or B side to connect. Perform switching.

第2図は、第1.第2のスイッチ部の前記した動作を示
すタイムチャートである。
Figure 2 shows the 1. It is a time chart which shows the above-mentioned operation of a 2nd switch part.

なお〜第1図では、第1.第2のスイッチ部3畠。In addition, in FIG. 1, 1. Second switch section 3.

3bの切換えを、コイルの励磁によって行なうような例
を示したが、論理素子あるいはスイッチ素子等、他の構
成要素を用iて実現してもよい。
Although an example has been shown in which the switching of 3b is performed by excitation of a coil, it may be realized using other components such as a logic element or a switch element.

(本発明の効果) 以上説明したように1本発明によれば簡単な構成で、ロ
ードシェア相互バックアップ方式のI10バス接続切換
装置が実現できる。
(Effects of the Present Invention) As described above, according to the present invention, an I10 bus connection switching device of load sharing mutual backup type can be realized with a simple configuration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係る装置の一例を示す構成ブロック図
、第2図はその動作の一例を示すタイムチャートである
。 1、.1b・−プロセ、す、 2 m 、 2 b−I
10ボート、3m。 3b・・・スイッチ部、4・・・手動切換手段、5・・
・自動切換手段。
FIG. 1 is a configuration block diagram showing an example of the device according to the present invention, and FIG. 2 is a time chart showing an example of its operation. 1. 1b・-Process, Su, 2m, 2b-I
10 boats, 3m. 3b...Switch section, 4...Manual switching means, 5...
・Automatic switching means.

Claims (1)

【特許請求の範囲】[Claims] (1)第1、第2のプロセッサと、第1、第2の入出力
ポートと、前記第1の入出力ポートと前記第1、第2の
プロセッサとのバス接続切換えを行なう第1のスイッチ
部と、前記第2の入出力ポートと前記第1、第2のプロ
セッサとのバス接続切換えを行なう第2のスイッチ部と
、前記第1、第2のスイッチを手動によって切換動作さ
せる手動切換手段と、前記第1、第2のプロセッサの正
常異常を判断し、前記各プロセッサが正常な場合は第1
の入出力ポートは第1のプロセッサに第2の入出力ポー
トは第2のプロセッサにそれぞれ接続されるように第1
、第2のスイッチを切りかえるとともに、前記第1、第
2のプロセッサのいずれか一方が異常となった場合は正
常のプロセッサに前記第1、第2の入出力ポートがとも
に接続されるように前記第1、第2のスイッチを切換る
自動切換手段とを備えた入出力バス接続切換装置。
(1) A first switch that switches bus connections between first and second processors, first and second input/output ports, and between the first input/output port and the first and second processors. a second switch unit for switching bus connections between the second input/output port and the first and second processors; and a manual switching unit for manually switching the first and second switches. Then, it is determined whether the first and second processors are normal or abnormal, and if each of the processors is normal, the first processor is
The first input/output port is connected to the first processor and the second input/output port is connected to the second processor, respectively.
, the second switch is switched, and the first and second input/output ports are both connected to a normal processor if either the first or second processor becomes abnormal. An input/output bus connection switching device comprising automatic switching means for switching first and second switches.
JP59177805A 1984-08-27 1984-08-27 Input output bus connection change-over device Pending JPS6155767A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59177805A JPS6155767A (en) 1984-08-27 1984-08-27 Input output bus connection change-over device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59177805A JPS6155767A (en) 1984-08-27 1984-08-27 Input output bus connection change-over device

Publications (1)

Publication Number Publication Date
JPS6155767A true JPS6155767A (en) 1986-03-20

Family

ID=16037392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59177805A Pending JPS6155767A (en) 1984-08-27 1984-08-27 Input output bus connection change-over device

Country Status (1)

Country Link
JP (1) JPS6155767A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04184557A (en) * 1990-11-20 1992-07-01 Hitachi Ltd Request contention generating system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52123141A (en) * 1976-04-08 1977-10-17 Fujitsu Ltd Device control system
JPS5685131A (en) * 1979-12-13 1981-07-11 Fujitsu Ltd Information transfer controlling system for block multiplexer channel

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52123141A (en) * 1976-04-08 1977-10-17 Fujitsu Ltd Device control system
JPS5685131A (en) * 1979-12-13 1981-07-11 Fujitsu Ltd Information transfer controlling system for block multiplexer channel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04184557A (en) * 1990-11-20 1992-07-01 Hitachi Ltd Request contention generating system

Similar Documents

Publication Publication Date Title
JPS6155767A (en) Input output bus connection change-over device
JP2006323551A (en) Plant control system
KR0146966B1 (en) Duplex method in the ring production
JPH01226037A (en) Duplex output circuit
JP2564397B2 (en) Redundant system data output device
JPS62213347A (en) Line switching system
JPS6343558Y2 (en)
JPS61184020A (en) Digital multiplex conversion system
JPH04205102A (en) Dual system
JPS62196702A (en) Output controlling circuit for programmable controller
JPH0244401A (en) Multiple type electrical process controller
JPS61239334A (en) Information processor
JPH0567989A (en) Changeover system
JPS59200531A (en) Dual switching system
JPS63180102A (en) Duplex system
JPH04205103A (en) Dual system
JPH096638A (en) Dual computer system and its switching device
JPH0514322A (en) Changeover control system
JPH0437320A (en) Line switching system for transmission system
JPH01144756A (en) Electronic switchboard system
JPH04113726A (en) Line changeover controller
JPS6083452A (en) Redundancy constitution system
JPS6175912A (en) Device switching device
JPH0498538A (en) Redundant switching device
JPS60138606A (en) Control system