JPS6155199B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for driving a semiconductor memory device, and more particularly to a method for driving an insulated gate field effect semiconductor device that realizes a nonvolatile random access memory.

Memory device with semiconductor integrated circuit structure (IC memory)
has always had high density, large integration, high speed, and low power consumption as its development philosophy. Furthermore, as for the memory function, a random access memory (RAM) that can introduce information "1" and "0" to a selected address is ideal in terms of versatility. Conventionally, RAM-type IC memories have been put into practical use using flip-flops, dynamic MOS transistors (three-element type), and C-load type 1MOS transistors (1Tr type) as memory cells.

However, these IC memories not only have a complicated circuit structure, but also require power consumption to retain information, which essentially limits their ability to achieve high density and large scale integration. A nonvolatile memory that injects and stores charges into a trap center or a floating gate in an insulated gate film and utilizes the nonvolatility of the stored charges is expected to be a memory cell that may solve this problem. Although such known non-volatile memory does not require power consumption to retain information, it is difficult to use as RAM because it is necessary to change the address selection method when writing information “0” or information “1”. However, it has been developed as a programmable read-only memory (PROM) in which the information to be selectively written is either "1" or "0", and the other is written to all bits at once.

As described above, according to the prior art, non-volatile RAM, which is desired as an ideal function of IC memory, has been technically unresolved.

An object of the present invention is to provide a preferred method for driving a semiconductor memory device that realizes a nonvolatile RAM with high density, large integration, and low power consumption.

A feature of the present invention is that a series circuit of a decode transistor and a memory transistor whose gate threshold is transferred is arranged at each matrix intersection where matrix lines intersect, and the side of the source or drain region of the decode transistor that is not connected to the memory transistor is connected to the row. The information lines are connected in common in the direction, and their gates are commonly connected in the column direction, and the sides of the drain or source regions of the memory transistors that are not connected to the decode transistor are all connected in common, and the gates are all connected in common. The matrix line is selected and one of electrons and holes is accumulated in the floating gate of the memory transistor at a predetermined address by controlling the potential of the information line. When changing the information of the memory transistor at an address, select the matrix line and apply the other of electrons and holes to the floating gate to a level that does not affect the memory transistor at the unselected address. The present invention provides a method for driving a semiconductor memory device, which is performed by applying a voltage to the information line. As described above, in the semiconductor device of the present invention, the memory cell is composed of only two transistors, and information "0" and information "1" can be selectively written to a selected address by controlling the information signal line. In addition, since the memory transistor is a nonvolatile memory, the peripheral circuit configuration of the memory section and the circuit configuration of the memory cell itself are extremely simple, making it possible to realize a RAM that is easy to achieve high density and large integration, and reduces power consumption to zero during the information retention period. Moreover, it is possible to selectively electrically rewrite and erase predetermined memory cells without using a high voltage.

Next, in order to better understand the present invention, embodiments of the present invention will be described using figures.

FIGS. 1A and 1B show a circuit diagram and a cross-sectional view of a memory cell according to an embodiment of the present invention. In this embodiment, a series circuit consisting of a decode transistor Q _D and a memory transistor Q _M is introduced as a memory cell at each intersection of a matrix formed by row lines D ₁ , D ₂ and column lines W ₁ , W ₂ . be. This series circuit connects the gate electrode of the decode transistor Q _D to a predetermined column line W _1k , one of its drain and source to a predetermined row line D ₁ , and the other to one of the drain and source of a memory transistor Q _M . The other of the drain and source of Q _M is connected to the reference line GND, and the gate electrode is connected to the common information line DL together with the memory transistors at each address. Also, the base electrode of all transistors
SUB is common, and a predetermined bias is applied between it and the reference line GND.

A preferred integrated circuit structure of the memory cell has a specific resistance of 10 Ω-cm with a principal plane of 100 as shown in FIG. 1B.
A P-type region 102 with a surface concentration of 8×10 ¹⁵ to 5×10 ¹⁶ cm ^-3 is provided in an inactive region on one surface of a P-type silicon single crystal substrate 101 , and an active region surrounded by this region has a surface concentration of 10 Phosphorus diffusion of ²⁰ to 10 ²¹ cm ^-3 is performed to provide N+ type regions 103 , 104 , 105 , and aluminum electrode wirings 107 , 108 , 109 , 110 extending over the upper surface of the surface insulating protective film 106 are provided. An insulating film 111 of about 500 Å of silicon dioxide deposited on the surface of the active part of the base 101, N+ type regions 103 and 104 for drain and source, and electrode wiring 10
Polycrystalline silicon gate electrode 1 conductively connected to 8
Reference numeral 12 constitutes an insulated gate type decode transistor _QD , and a lead-out electrode wiring 10 from the N+ region 103
7 is connected to the row line D ₁ , and the electrode wiring 108 is connected to the column line W ₁
Connect to. Further, the insulating film 111, the N+ type regions 104 and 105 which become the drain and the source, and the N
A P+ type region 113 with a surface concentration of 5×10 ¹⁶ to 10 ¹⁸ cm ^-3 forms a low breakdown voltage PN diode in contact with a part of the + type region 104 , and a silicon layer of about 1000 Å is deposited on the upper surface of the insulating film 111 . Another insulating film 114 mainly composed of nitride or alumina and a floating gate 115 embedded in the boundary between these insulating films.
and a gate electrode 109 capacitively coupled to the floating gate 115 via another insulating film 114 constitute a nonvolatile memory transistor Q. The gate electrode 109 is connected to the information line DL, and the N+ type region 105
The lead-out electrode wiring 110 is connected to the reference line GND,
N+ region 104 is used as a common region for decode transistors and memory transistors to form a series circuit. A base electrode 116 is provided on the back surface of the base 101 and serves as a base terminal SUB.
An N-channel memory transistor with a floating gate has a gate electrode, an insulating film, a floating gate, and a floating gate.
It has an MI ₁ MI ₂ S type gate structure consisting of an insulating film and a semiconductor substrate. In this embodiment, such a memory transistor has a P ⁺ type region 113 under the floating gate 115, but the present invention is not limited to having this P ⁺ type region 113 ^. An example without the mold region 113 will be explained. For the source potential V _S , drain potential V _D , base potential V _sub , and gate electrode potential V _G , set V _S = V _D = Vsu _B = OV, and after applying a voltage to V _G for about 1 second. When the gate threshold value V _T of a memory transistor is measured in an N-channel memory transistor, for example, in an N-channel memory transistor, when the initial V _T is positive V _G , negative charge is accumulated with +50V as the critical value +V _C , and −40 V as the critical value − It exhibits an indirect tunnel injection type charge accumulation effect that releases negative charges as V _C .
On the other hand, in the embodiment shown in FIG. 1B, an insulating film having a silicon nitride film or an alumina film is used for _I1 ,
A low breakdown voltage diode made of P ⁺ region 113 was formed below it. In this way, the P ⁺ type region 113
When there is a low breakdown voltage diode of
Even when the gate voltage V _G does not reach V _C or -V _C , the gate threshold value is transferred. This characteristic is a kind of avalanche injection operation that occurs because electrons and holes generated by avalanche breakdown in the reverse direction of the diode are drawn toward the floating gate in response to the gate electric field. By using this characteristic, information "1" or "0" can be sent to the memory cell at the selected address by simply controlling the potential of the gate electrode of the memory transistor.
At other addresses, the decode transistor does not work, so diode breakdown does not occur, and a voltage below the critical value is simply applied to the gate electrode of the memory transistor, so information is not disturbed. I don't accept it.

FIG. 2 shows voltage waveforms for selective write/read operations in the embodiments described above. To select an address, apply driving voltages V _D and V _W to the matrix line to the address,
It controls the potential V _DL of the information line to selectively write information "1" or "0", and receives the current flowing from the column line through the memory cell as the output Iout. That is, the substrate is kept at a potential of OV, and at time t ₁
Drive voltage V of about 30V to the address selected at ~t _2
D and _VW are applied, and the potential _VDL of the information line is set to about 30V, and when the reference line GND is cut off from the circuit connection or rises by about +10V with respect to the substrate, the memory transistor becomes non-conductive and the memory transistor at the selected address is N+ type. A low voltage diode formed in a part of the area undergoes avalanche breakdown at approximately +15V. At this breakdown point, an electric field is applied at the potential of the information line to induce negative charges from the gate electrode of the memory transistor, and therefore electrons are injected from the breakdown point toward the floating gate. In memory transistors at other addresses that are not selected at this time, the potential of the N+ type region of the memory transistor is OV even if the decode transistor is non-conductive or conductive, so a breakdown phenomenon occurs in the diode at the address that is not selected. does not occur, and no charge is transferred to or from the floating gate to transfer the gate threshold of the memory transistor. Due to this selective writing, negative charges are accumulated in the floating gate, and the gate threshold of the memory transistor shifts to a positive direction of about 8V. If information writing due to an increase in the gate threshold is defined as information "0", this information "0" means that the drive voltages V _D and V _W of +5V in the time width from time t ₃ to _{t 4} are applied to the matrix line to the same address. By simultaneously applying a +5V potential V _DL to the information line, the "0" output current from the address is zero current because the gate threshold of the memory transistor is higher than the potential V _DL as the read signal.

Further, drive voltages V _D and V _W of approximately +30V are applied to the matrix line at the selected address from time t ₅ to _{t 6} in the same way as when writing information "0", and at the same time, the potential of the information line V _DL is applied.
When the voltage is set to 0 to -20V, positive charge accumulation is induced in the floating gate of the memory transistor at this address, the gate threshold value is lowered, and information "1" is selectively written. This writing of information "1" occurs because the low breakdown voltage diode of the memory transistor at the selected address undergoes avalanche breakdown, and because the potential of the gate electrode is low, an electric field acts that draws holes toward the floating gate. When information "0" is written in the memory transistor at the address, the information is rapidly changed to "1". Further, the transition of the gate threshold value of information "1" in the negative direction is controlled by the potential of the gate electrode, and when the potential of the information line is set to OV and the signal for writing information "1" is used, the gate threshold value of the memory transistor is -1 to When it is +1V and -20V, it becomes about -1 to -5V, and the level of information "1" can be controlled.

At time _t7 to _t8 , the selective read operation is performed again in the same manner as time _t3 to _t4 , and the drive voltage V _D of +5V is applied to the selected address.
When V _W is applied, and at the same time the information line is driven with +5V, the memory transistor in which information "1" is written becomes conductive because the gate threshold is less than 5V, and the flow flows from the row line to the address to the reference line. A “1” output current can be obtained. A low breakdown voltage diode formed in the N+ type region immediately below the floating gate of the memory transistor is provided at least in part of one of the drain and source, and has reverse breakdown voltage characteristics lower than the drain junction breakdown voltage of the decode transistor. For this reason, the diode is formed not only by bringing the highly doped P-type region into contact with the N+-type region as in the previous embodiment, but also by making the insulating film between the floating gate and the substrate thinner than the insulating gate film of the decode transistor. Favorable properties can be obtained even if the

Furthermore, the potential of the information line for writing information "1" does not necessarily require a negative voltage, and information "0" in the memory transistor can be selectively rewritten to information "1". When the potential of the information line and the diode breakdown voltage are set so that the gate threshold of the memory transistor by writing information "1" is in the depletion region and the gate threshold by writing information "0" is in the enhancement region, the information line in the read operation is set. The potential of can be set to the same potential as the reference line.

[Brief explanation of the drawing]

FIGS. 1A and 1B are a circuit diagram and a cross-sectional view of a memory cell of an embodiment of the present invention, and FIG. 2 is a voltage waveform diagram showing the operation of an embodiment of the invention, with Q _D
is a decoding transistor, Q _M is a memory transistor, D ₁ and D ₂ are row lines, W ₁ and W ₂ are column lines, DL is an information line, GND is a reference line, SUB is a base electrode, 101
is a P-type silicon single crystal substrate, 103,104,1
05 is an N+ type region, 111 and 114 are insulating films, and 115 is a floating gate.

Claims (1)

[Claims] 1 A series circuit of a decode transistor and a memory transistor whose gate threshold is transferred is arranged at each matrix intersection where the matrix lines intersect, and the side of the source or drain region of the decode transistor that is not connected to the memory transistor is commonly connected in the row direction. , and the gates are commonly connected in the column direction, and the sides of the drain or source regions of the memory transistors that are not connected to the decode transistor are all commonly connected, and
The gates are all commonly connected and led out as an information line, and the matrix line is selected and one of electrons and holes is sent to the floating gate of the memory transistor at a predetermined address to control the potential of the information line. Therefore, when storing and changing the information of the memory transistor at the predetermined address, select the matrix line and transfer the other of electrons and holes to the floating gate and to the memory transistor at the unselected address. 1. A method of driving a semiconductor memory device, characterized in that the method is introduced by applying a potential to the information line to a level that does not have any influence.