JPS6154468A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6154468A
JPS6154468A JP59175836A JP17583684A JPS6154468A JP S6154468 A JPS6154468 A JP S6154468A JP 59175836 A JP59175836 A JP 59175836A JP 17583684 A JP17583684 A JP 17583684A JP S6154468 A JPS6154468 A JP S6154468A
Authority
JP
Japan
Prior art keywords
voltage
external terminal
circuit
gate
vcc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59175836A
Other languages
Japanese (ja)
Other versions
JPH0349393B2 (en
Inventor
Yoshihiro Takemae
義博 竹前
Kimiaki Sato
公昭 佐藤
Masao Nakano
正夫 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59175836A priority Critical patent/JPS6154468A/en
Publication of JPS6154468A publication Critical patent/JPS6154468A/en
Publication of JPH0349393B2 publication Critical patent/JPH0349393B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To prevent an internal circuit from breaking when performing operation different from normal operation by interposing a clamping circuit between an external terminal and an internal circuit. CONSTITUTION:When a voltage of, for example, about 10-15V is applied to the external terminal, gate-source voltages of transistors (TR) of a voltage decision circuit rises above a threshold voltage and those TRs turn on. A positive voltage is developed at an output node N and a testing circuit 8 is actuated to perform specific testing operation, etc. In this case, the TR5 of the voltage clamping circuit 4 is cut off when the gate of a TR3 rises up to a level Vcc-Vth even if the voltage at an external terminal 1 rises above Vcc, thereby preventing the high voltage at the external terminal 1 from being applied to the input TR3 directly. At this time, the voltage applied between the drain and gate of the TR5 is the difference voltage between the plus voltage applied to the external terminal 1 and Vcc, so the gate dielectric strength is the same with the TR3 and there is no gate destruction occurring.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、半導体装置に関し、特に試験その他の目的で
通常動作とは異なった動作をさせるため、通常使用範囲
外の電圧または電流を外部から印加する場合に内部回路
を的確に保獲する手段を設けた半導体装置に関する。
Detailed Description of the Invention (Industrial Application Field) The present invention relates to a semiconductor device, and particularly relates to a method for applying a voltage or current outside the normal usage range from the outside in order to cause a semiconductor device to operate differently from its normal operation for testing or other purposes. The present invention relates to a semiconductor device provided with means for accurately securing an internal circuit when applying voltage.

(従来の技術) 従来、半導体記憶装置等の半導体装置において、外部端
子に通常使用範囲外の電圧を印加し、この電圧を装置内
部に設けた検出回路によって検出することにより通常動
作とは別の動作をさせることが行なわれている。例えば
、消去可能なプログラマブルリードオンリメモリ(EP
ROM )においては、ある外部端子に通常の論理動作
における信号電圧よシも高い電圧を印加することにより
全ビットのメモリセルをクリアすることが可能である。
(Prior Art) Conventionally, in a semiconductor device such as a semiconductor memory device, a voltage outside the normal operating range is applied to an external terminal, and this voltage is detected by a detection circuit provided inside the device. Actions are being taken. For example, erasable programmable read-only memory (EP)
In a ROM (ROM), it is possible to clear all bits of memory cells by applying a voltage higher than the signal voltage in normal logic operation to a certain external terminal.

しかしながら、このような従来形の半導体装置において
は、入力耐圧の低い内部回路部分に接続されている外部
端子を利用しようとすると、その外部端子に通常使用範
囲外の電圧を印加した場合に通常動作に使用するための
内部回路が破壊されるという不都合があった。特に、通
常使用範囲外の電圧として通常使用時における電源電圧
より高い電圧を比較的長時間印加する場合等には内部回
路の入力トランジスタのダート絶縁膜が破壊される等″
の不都合があるため、このような外部端子は高電圧印加
による動作モード変更に利用できないという問題があっ
た。
However, in such conventional semiconductor devices, if you try to use an external terminal connected to an internal circuit part with a low input withstand voltage, if a voltage outside the normal usage range is applied to the external terminal, normal operation will not be possible. This had the disadvantage that the internal circuitry used for this purpose was destroyed. In particular, if a voltage higher than the power supply voltage during normal use is applied for a relatively long time as a voltage outside the normal usage range, the dirt insulation film of the input transistor of the internal circuit may be destroyed.
Due to these inconveniences, there has been a problem in that such external terminals cannot be used to change the operating mode by applying a high voltage.

(発明が解決しようとする問題点) 本発明の目的は、前詠の従来形における問題点に鑑み、
辿常決用範囲外の電圧、電流を印加することにより通常
動作とは異なった動作をさせる半導体装置において、外
部端子と内部回路との間にクランプ回路を挿入するとい
う構想に基づき、通常動作と異なる動作をさせる場合に
おける内部回路の破壊を防止することにある。
(Problems to be Solved by the Invention) The purpose of the present invention is to solve the problems in the conventional form of the prelude,
In semiconductor devices that operate differently from normal operation by applying voltages and currents that are outside the normal operating range, this method is based on the concept of inserting a clamp circuit between the external terminal and the internal circuit. The purpose is to prevent damage to the internal circuit when performing different operations.

(問題点を解決するための手段) 上述の問題を解決するため、本発明によれば、外部端子
の電圧が通常使用範囲外の電圧か否かを判定する電圧判
定回路、および外部端子と内部回路との間に挿入され外
部端子の電圧が通常使用範囲外の電圧である場合は外部
端子の電圧が直接内部回路に印加されることを防止する
クランプ回路を具備し、外部端子の電圧が通常使用範囲
外の電圧の場合は通常動作と異なった動作を行なうこと
を特徴とする半導体装置が提供される。
(Means for Solving the Problem) In order to solve the above-mentioned problem, the present invention provides a voltage determination circuit that determines whether the voltage at the external terminal is outside the normal usage range, and a voltage determination circuit that determines whether the voltage at the external terminal is outside the normal usage range. It is equipped with a clamp circuit that is inserted between the external terminal and the circuit and prevents the external terminal voltage from being directly applied to the internal circuit when the external terminal voltage is outside the normal usage range. A semiconductor device is provided which is characterized in that it performs an operation different from normal operation when the voltage is outside the usable range.

(作 用) 上述のような構成により、試、験その他の目的で外部端
子に例えば通常使用状態における電源電圧よシも高い電
圧を印加した場合には、該クランプ回路によって外部端
子の電圧が直接内部回路に印加されることがなくなシ内
部回路の破壊が的確に防止される。
(Function) With the above-described configuration, when a voltage higher than the power supply voltage in normal use is applied to the external terminal for testing, testing, or other purposes, the voltage at the external terminal is directly controlled by the clamp circuit. Since no voltage is applied to the internal circuit, destruction of the internal circuit is accurately prevented.

(実施例) 以下、添付の図面を参照して本発明の1実施例につき説
明する。添付の図面は、本発明の1実施例に係わる半導
体装置の入力部の回路を示す。同図の回路においては、
外部端子1と通常動作を行なうための内部回路2の入力
トランジスタ3のダートとの間に電圧クランプ回路4が
接続されている。電圧クランプ回路4は、例えばMIS
トランジスタ5を有し、ソースおよびドレインがそれぞ
れ外部端子1および入力MIS )ランノスタ3のダー
トに接続されている。MIS )ランジスタ5のダート
は例えば5vの電源VCCに接続されている。また、外
部端子1には、診外部端子とグランド間に直列接続され
たMIS )ランジスタロー1.6−2゜・・・、6−
nとMIS)ランジスタ5−nに並列接続されたデプレ
ッション型トランジスタ7とを有する電圧判定回路が接
続されており、この電圧判定回路の出力ノードN1には
例えば内部回路2の動作試験を行なうための試験回路8
が接続されている。電圧判定回路の各トランジスタ6−
1.6−2゜・・・、6−nはそれぞれf−)とドレイ
ンが接続されており、デプレッション型MIS)ランジ
スタフはダートとソースが接続されている。なお、試験
回路8としては、内部回路の動作試験を行なう回路に限
定されず、例えば記憶装置のすべてのメモリセルをクリ
アする回路であってもよい。
(Embodiment) Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings. The accompanying drawings show a circuit of an input section of a semiconductor device according to an embodiment of the present invention. In the circuit shown in the same figure,
A voltage clamp circuit 4 is connected between the external terminal 1 and the terminal of the input transistor 3 of the internal circuit 2 for normal operation. The voltage clamp circuit 4 is, for example, an MIS
It has a transistor 5, and its source and drain are respectively connected to the external terminal 1 and the dart of the input MIS (MIS) lannoster 3. MIS) The dart of the transistor 5 is connected to a 5V power supply VCC, for example. In addition, the external terminal 1 has MIS transistor rows connected in series between the diagnostic external terminal and the ground.
A voltage determination circuit having a depletion type transistor 7 connected in parallel to the MIS transistor 5-n is connected to the output node N1 of the voltage determination circuit. Test circuit 8
is connected. Each transistor 6- of the voltage determination circuit
1.6-2°..., 6-n have their drains connected to f-), and the depletion type MIS transistors have their darts connected to their sources. Note that the test circuit 8 is not limited to a circuit that tests the operation of an internal circuit, but may be a circuit that clears all memory cells of a storage device, for example.

上述の回路によって、外部端子1に例えば電源VCCの
電圧からグランド電圧の範囲に近い通常使用範囲の電圧
が印加されている場合には、電圧クランプ回路4のトラ
ンジスタ5がオンとなっており、外部端子1の電圧がほ
ぼそのまま入力トランジスタ3に印加され、通常動作が
行なわれる。なお、電圧判定回路のトランジスタ6−1
 、6−2 。
With the circuit described above, when a voltage in the normal use range close to the range from the voltage of the power supply VCC to the ground voltage is applied to the external terminal 1, the transistor 5 of the voltage clamp circuit 4 is turned on, and the external The voltage at terminal 1 is applied almost unchanged to input transistor 3, and normal operation is performed. Note that the transistor 6-1 of the voltage determination circuit
, 6-2.

・・・、6−nの数は外部端子1に通常使用範囲の電圧
が印加されている場合にはすべてカットオフされるよう
に選択されている。したがって、電圧判定回路の出力N
1が低レベルとなっており、試験回路8は起動されない
. . , 6-n are selected so that they are all cut off when a voltage within the normal use range is applied to the external terminal 1. Therefore, the output N of the voltage determination circuit
1 is at a low level, and the test circuit 8 is not activated.

これに対して、外部端子1に例えば10から15’/程
度の電圧が印加された場合には、電圧判定回路のトラン
ジスタ6−1.6−2.・・・、6−nの各f−)ソー
ス間の電圧がしきい値電圧以上となり、これらのトラン
ジスタがオンとなる。これにより、出力ノードN1に正
の電圧が発生し試験回路8が起動されて所定の試験動作
等が行なわれる。この場合、電圧クランプ回路4のトラ
ンジスタ5は外部端子1の電圧がvcc以上となっても
トランジスタ3のf−)カV。c −vthのレベル(
vthはトランジスタ5の閾値)まで上昇するとカット
オフし、したがって外部端子1の高電圧が直接入力トラ
ンジスタ3に印加されることが防止される。このときト
ランジスタ5のドレイン(外部端子1側)とダート間に
加わる電圧は外部端子1へ印加された正電圧とvccと
の差電圧であるから、ダート耐圧はトランジスタ3と同
様のものでもダート破壊を生じない。
On the other hand, when a voltage of, for example, about 10 to 15' is applied to the external terminal 1, the transistors 6-1, 6-2. ..., 6-n, each f-) source voltage becomes equal to or higher than the threshold voltage, and these transistors are turned on. As a result, a positive voltage is generated at the output node N1, the test circuit 8 is activated, and a predetermined test operation is performed. In this case, the transistor 5 of the voltage clamp circuit 4 maintains the f-) voltage of the transistor 3 even if the voltage at the external terminal 1 exceeds vcc. c - level of vth (
When vth rises to the threshold value of transistor 5), it is cut off, thus preventing the high voltage at external terminal 1 from being directly applied to input transistor 3. At this time, the voltage applied between the drain of transistor 5 (external terminal 1 side) and dart is the difference voltage between the positive voltage applied to external terminal 1 and vcc, so even if the dart breakdown voltage is the same as transistor 3, dart breakdown will occur. does not occur.

上述においては、試験等の場合に外部端子IK通常使用
範囲外の電圧を使用する場合につき説明したが、試験等
を行なう場合外部端子1に通常使用@回外の電流を回す
ようにしてもよいことは明らかである。なお、上述の回
路におけるデプレッション厘トランジスタ7は外部端子
1の電圧が通常使用範囲内の場合に電圧判定回路の出力
ノードN1の電圧を確実にグランド電位にするために設
けられているものである。
In the above, we have explained the case where a voltage outside the normal use range of the external terminal IK is used for tests, etc. However, when conducting tests, etc., it is also possible to run the normal use @ supination current to the external terminal 1. That is clear. Note that the depletion transistor 7 in the above-described circuit is provided to ensure that the voltage at the output node N1 of the voltage determination circuit reaches the ground potential when the voltage at the external terminal 1 is within the normal use range.

(発明の効果) 以上のように、本発明てよれば、外部端子に通常使用範
囲外の電圧または電流を印加して通常動作とは異なった
動作を行なう場合に、内部回路に過電圧、過′FtL流
が印加されることが防止され内部回路の破壊が的確に防
止される。
(Effects of the Invention) As described above, according to the present invention, when a voltage or current outside the normal usage range is applied to an external terminal to perform an operation different from the normal operation, the internal circuit is affected by overvoltage or overvoltage. Application of the FtL current is prevented, and destruction of the internal circuit is precisely prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

添付の図面は、本発明の1実施例に係わる半導体装置の
入力部を示すブロック回路図である。 1:外部端子、2:内部回路、3:入力トランジスタ、
4:電圧フラング回路、5.6−1゜6−2 、− 、
6− n : MIS トランジスタ、7:デプレッシ
ョン型MIS トランジスタ、8:試験回路。
The accompanying drawing is a block circuit diagram showing an input section of a semiconductor device according to an embodiment of the present invention. 1: External terminal, 2: Internal circuit, 3: Input transistor,
4: Voltage flag circuit, 5.6-1゜6-2, -,
6-n: MIS transistor, 7: depression type MIS transistor, 8: test circuit.

Claims (1)

【特許請求の範囲】[Claims] 外部端子の電圧が通常使用範囲外の電圧か否かを判定す
る電圧判定回路、および外部端子と内部回路との間に挿
入され外部端子の電圧が通常使用範囲外の電圧である場
合は外部端子の電圧が直接内部回路に印加されることを
防止するクランプ回路を具備し、外部端子の電圧が通常
使用範囲外の電圧の場合は通常動作と異なった動作を行
なうことを特徴とする半導体装置。
A voltage judgment circuit that determines whether the voltage at the external terminal is outside the normal usage range, and an external terminal that is inserted between the external terminal and the internal circuit to determine if the voltage at the external terminal is outside the normal usage range. 1. A semiconductor device comprising a clamp circuit that prevents a voltage from being directly applied to an internal circuit, and performing an operation different from normal operation when a voltage at an external terminal is outside a normal use range.
JP59175836A 1984-08-25 1984-08-25 Semiconductor device Granted JPS6154468A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59175836A JPS6154468A (en) 1984-08-25 1984-08-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59175836A JPS6154468A (en) 1984-08-25 1984-08-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6154468A true JPS6154468A (en) 1986-03-18
JPH0349393B2 JPH0349393B2 (en) 1991-07-29

Family

ID=16003063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59175836A Granted JPS6154468A (en) 1984-08-25 1984-08-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6154468A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57133656A (en) * 1981-02-12 1982-08-18 Nec Corp Semiconductor integrated circuit incorporated with test circuit
JPS5863172A (en) * 1981-10-12 1983-04-14 Nec Corp Input/output protecting device
JPS5873162A (en) * 1981-10-28 1983-05-02 Toshiba Corp Semiconductor device and manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57133656A (en) * 1981-02-12 1982-08-18 Nec Corp Semiconductor integrated circuit incorporated with test circuit
JPS5863172A (en) * 1981-10-12 1983-04-14 Nec Corp Input/output protecting device
JPS5873162A (en) * 1981-10-28 1983-05-02 Toshiba Corp Semiconductor device and manufacture thereof

Also Published As

Publication number Publication date
JPH0349393B2 (en) 1991-07-29

Similar Documents

Publication Publication Date Title
US5828596A (en) Semiconductor memory device
US7629802B2 (en) Semiconductor device including fuse and method for testing the same capable of suppressing erroneous determination
JP2006139900A (en) Method and device for programming anti-fuse using internally generated programming voltage
KR980005018A (en) How to Program Binary States in Nonvolatile Memory Cells and Nonvolatile Memory
US5450417A (en) Circuit for testing power-on-reset circuitry
EP0756379A1 (en) Unbalanced latch and fuse circuit including the same
EP0602708A2 (en) Control electrode disable circuit for power transistor
US6791373B2 (en) High-voltage detecting circuit
KR20020053769A (en) Fuse circuit
US20030214337A1 (en) Latch circuit
JP2522381B2 (en) Semiconductor device
JPH0482188B2 (en)
KR100233224B1 (en) High voltage detection circuit
US6271692B1 (en) Semiconductor integrated circuit
US5786716A (en) Signal generator for generating test mode signals
US6819597B2 (en) Row decoder in flash memory and erase method of flash memory cell using the same
JPS6154468A (en) Semiconductor device
JP3539194B2 (en) Power MOSFET circuit
US6606264B2 (en) Programmable circuit and its method of operation
KR100282708B1 (en) An input circuit of a semiconductor device (INPUT CIRCUIT OF SEMICONDUCTOR DEVICE)
KR100487914B1 (en) Anti-Fuse Stabilization Circuit
KR0164802B1 (en) Driver circuit of burn-in test mode
JP3211881B2 (en) Semiconductor storage device
KR950013395B1 (en) Non-volatile semiconductor memory device with input-stage circuit
US20010015661A1 (en) Device for the detection of a high voltage

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees