JPS6154254B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a semiconductor integrated circuit, in which polycrystalline silicon is used as an element electrode, an interconnect between elements, or both, and an active region and a field region are formed by selective oxidation of silicon using a silicon nitride film. The present invention relates to a method of manufacturing an integrated circuit in a self-aligned manner using a method, and particularly provides a manufacturing method for easily realizing a structure that can solve problems that arise when miniaturization is performed.

Hereinafter, as an aid to clarifying the effectiveness of the present invention, the conventionally known silicon gate field effect transistor (hereinafter referred to as silicon gate MOSFET) will be described.
First, we will discuss the structural defects that are highlighted when semiconductor integrated circuits are miniaturized.

FIG. 1a shows that a p-type impurity diffusion layer 12 as a channel stopper and a thick field oxide film 13 are formed by selective oxidation in a field region of a p-type silicon substrate 11 having a resistivity of several Ωcm, which is to be used as an active region. Gate insulating film 14 on the silicon substrate surface
After forming a polycrystalline silicon gate electrode 15G and an inter-device interconnection 15C, a polycrystalline silicon gate electrode 15G and an inter-device wiring 15C are formed, and then the active region (device region represented by the source, gate, and drain) not covered by the polycrystalline silicon gate electrode 15G is deposited. A high concentration of n-type impurity is added by diffusion etc. to a semiconductor substrate (which is a region involved in the carrier phenomenon in the semiconductor substrate including an additional area represented by the internal wiring area), and the source also functions as the internal wiring area. forming a region 16 and a drain region 16;
1 is a schematic cross-sectional view showing the basic structure of a semiconductor integrated circuit including a silicon gate MOSFET. In addition, here, p type is used as the first conductivity type,
Furthermore, although n-type is illustrated as the second conductivity type, this is only an example.

As mentioned above, when miniaturizing a semiconductor integrated circuit that includes a silicon gate MOSFET as a functional element and polycrystalline silicon as an inter-element wiring, the problems are the layer resistance of the polycrystalline silicon part and the n-type which becomes the source or drain. The layer resistance of the diffusion layer becomes extremely high. The main reason for this is that in order to miniaturize silicon gate MOSFETs without damaging their electrical characteristics, the dimensions must be reduced not only in the two-dimensional direction of the semiconductor surface, but also in the three-dimensional direction, that is, in the depth direction, in accordance with the so-called scale-down law. Because it has to be.

For example, the width of the gate polycrystalline silicon of the commonly used silicon gate MOSFET is 5.
~6μm, source/drain junction depth 1.5~
On the other hand, in the case of short-channel silicon gate MOSFETs that are currently in the development stage, the gate polycrystalline silicon width is approximately 2 μm or
It is less than that. Along with this, the n-type diffusion layer junction depth in both the source and drain regions has also become very shallow, 0.5 μm or less.

When making particularly shallow junctions like this, the impurity concentration of the n-type layer cannot be made sufficiently high, so the layer resistance becomes several tens of Ω/□ or more, and usually at the same time the n-type The layer resistance of polycrystalline silicon into which impurities are introduced also ranges from several tens of Ω/□.
It may reach 100Ω/□. In addition, since the thickness of polycrystalline silicon does not directly affect the electrical characteristics of the silicon gate MOSFET, it is not necessary to follow the scale-down rule, but as the width of polycrystalline silicon becomes narrower, As long as it happens,
In reality, the film thickness must be made thinner in order to maintain the processing accuracy and to reduce the probability of wire breakage at subsequent steps such as metal wiring, which also causes an increase in layer resistance. ing.

Figure 1b shows a perspective partial cross-sectional view of a conventional large-scale integrated circuit that uses polycrystalline silicon and n-type impurity diffusion layers with high layer resistance as inter-element wiring, intra-element wiring, etc. To further clarify the point.

As is clear from Figure 1b, from the feed point F from the higher-order metal wiring to the electrode part of the field effect transistor.
The intra-element wiring by the n-type impurity diffusion layer 16 that reaches E1 or E2 is connected to the same power supply point F in terms of the circuit, if the resistance of each part is ignored. However, in reality, the resistance of each of these parts cannot be ignored as the scale of the integrated circuit increases, and it is difficult to place the elements and feed points at equal distances due to various constraints. This will cause problems. In particular, the internal wiring of the n-type impurity diffusion layer 16 leading to the electrode E1 is longer than that leading to the electrode E2 , and an unnecessary high resistance component is present.
The voltage drop there becomes impossible to ignore. For example, if the feed point F is at ground potential, there is a risk that the actual ground potential will rise;
If F is the power supply potential, there is a risk that the actual power supply voltage will drop, resulting in a significant reduction in the operating margin of the integrated circuit. Furthermore, if polycrystalline silicon 15C, which similarly has a high layer resistance, is used as an inter-element wiring in an electrical signal transmission circuit, the signal propagation delay time increases, which becomes a major obstacle to speeding up the integrated circuit.

Therefore, a structure has been proposed that can eliminate the drawbacks of the conventional structure described above, especially the drawbacks when miniaturized. That is, as shown in a perspective partial cross-sectional view in FIG. 2, it has a shallow junction depth as shown in FIGS. N-type impurity diffusion layer 16
The structure is separated into two continuous structures, and a new impurity diffusion layer 18 is provided which functions exclusively as the internal wiring to lower the resistance of the internal wiring, which could not be achieved with the shallow impurity layer 16 in FIGS. 1a and 1b. realized,
In addition to effectively solving the problems related to the arrangement of the feed points, etc., the device electrode component parts, which must maintain a shallow junction depth in accordance with the scale-down rule, have a conventional shallow junction depth. Impurity layer 1
By leaving the number 7, the desired large-scale integrated circuit can be realized.

However, even with the structure proposed by this proposal, the amount of impurity diffusion into the silicon substrate or polycrystalline silicon is limited by the solid solubility, and on the other hand, the junction depth and the thickness of the polycrystalline silicon are also affected by the increase in junction capacitance and the difference in level. A layer resistance value of about 10Ω/□ has been the limit for reasons such as the need to suppress the occurrence of situations such as an increase in the probability of wire breakage.

Therefore, a structure has been proposed in which it is possible to further reduce the layer resistance values of the internal wiring made of impurity diffusion layers and the inter-element wiring made of polycrystalline silicon by about an order of magnitude, and the surface level difference is small. That is, as shown in a perspective partial sectional view in FIG.
The surface of the n-type impurity diffusion layer 18 which becomes the internal wiring following the n-type impurity diffusion layer 17 which is the shallow junction depth source or drain electrode shown in the figure, and the polycrystalline silicon which becomes the gate electrode of the element or the inter-device wiring 15G. A thin metal silicide layer 19 is provided on the surface of 15C to reduce the layer resistance value, and the junction depth of the impurity diffusion layer 18, which becomes the internal wiring of the device, is made shallow to reduce the junction capacitance. By reducing the thickness of silicon and reducing surface steps, it is attempted to realize large-scale integrated circuits with desired high performance and high yield.

It is an object of the present invention to enable the new structure proposed above to be realized reliably and easily.

The manufacturing method according to the present invention has the following features.

That is, a first silicon nitride film is formed on the surface of the first conductivity type semiconductor substrate in areas other than regions to be used as inter-element isolation regions, a channel stopper and a field oxide film are formed using this first silicon nitride film as a mask, and then A partial region of the first silicon nitride film, that is, a second conductivity type impurity layer with a shallow junction depth is formed in the first region of the region to be a future device region, including a region to be formed as a source and a drain.
After removing the silicon nitride film, a thin insulating film that will become a gate insulating film in the future is formed on the entire surface of this removed area, and a polycrystalline silicon layer is further formed in the area that will become a gate electrode in the future and the area that will become an inter-element wiring. is patterned and formed together with a second silicon nitride film placed thereon, and the exposed thin film is formed using the second silicon nitride film, the polycrystalline silicon layer, and the remaining portion of the first silicon nitride film as a mask. The impurity exhibiting the second conductivity type is introduced into the first layer through the insulating layer.
A second conductivity type impurity layer is shallowly introduced into the surface layer of the conductivity type substrate to form a shallow junction depth layer with the source and drain, and then an exposed thin insulating film and an exposed polycrystalline silicon layer are formed. A silicon oxide film is formed on the surface layer, the remaining first silicon nitride film and second silicon nitride film are removed, and an impurity exhibiting a second conductivity type is introduced from the removed region to form the first silicon nitride film region. A second conductivity type impurity layer having a deep junction depth connected to the second conductivity type impurity layer having a shallow junction depth is formed on the first conductivity type semiconductor substrate to form an inter-element wiring region; The polycrystalline silicon layer in the silicon nitride film region is also
This method of manufacturing a semiconductor integrated circuit is characterized in that conductivity type inter-element wiring is formed, and the surface of the second conductivity type impurity layer and the polycrystalline silicon layer with the deep junction depth are covered with a thin metal silicide.

Hereinafter, the main steps of a typical embodiment of the present invention will be explained with reference to FIG.

Figure 4 a shows a p-type silicon substrate 3 with a specific resistance of Ωcm.
1, a silicon nitride film 34 is patterned and used as a mask, and a p ⁺ layer 32 and a field oxide film 33 as a channel stopper are formed by selective oxidation. In the conventional method, at this point, the silicon nitride film 34 on the active region used for selective oxidation is completely removed and a gate insulating film is deposited.

However, in the present invention, as shown in FIG. 4b, n
Leaving the silicon nitride film 34 covering the surface of the active region A where a two-layer structure consisting of a type impurity diffusion layer and a thin metal silicide layer on the surface thereof is to be formed, both source and drain regions with a shallow junction depth will be formed in the future. After removing the silicon nitride film on the surface of the active region where a high-performance short channel MOSFET with (38 in Figure 4 d, e, f, g, h) is to be formed, approximately 400 Å A polycrystalline silicon film 36 with a thickness of about 2500 Å and a silicon nitride film 37 are further deposited on the surface of the silicon oxide film 35 by, for example, ordinary CVD.

Normally, when only polycrystalline silicon is used for gate electrodes and inter-element wiring, the thicker the better in terms of layer resistance, and the thinner the better in terms of pattern cutting accuracy and reduction of disconnections at steps, so It is difficult to choose the correct thickness.

Figure 4c shows a width of about 2 μm that will become the gate electrode in the future.
Leaving the striped polycrystalline silicon film 36G and the polycrystalline silicon film 36C serving as interconnects between elements, the remaining source formation region S , drain formation region D , impurity diffusion layer, and a low layer with a metal silicide layer on the surface thereof are formed. This figure shows the state in which the polycrystalline silicon film in region A , which forms the two-layer structure of the resistor, has been removed using silicon nitride films 37G and 37C as an etching mask.

Figure 4d shows an n
The type impurity diffusion region 38 is formed by a silicon nitride film 34,
37G and polycrystalline silicon 36G which will serve as an electrode are used as masks to show a state formed using an ion implantation method or the like.

FIG. 4e shows the side surfaces of the polycrystalline silicon 36G, 36C and the shallow junction depth source region S and drain region using the second silicon nitride film 37 as a mask.
This shows the state in which oxide films 39G and 39C are deposited on the surface of D by thermal oxidation. This oxide film 39G needs to have a sufficient thickness to protect the shallow junction 38 when forming the two-layer impurity diffusion layer later.
The interface between 39G and 38 is located at a somewhat deeper position than before thermal oxidation. Note that silicon nitride films 34 and 3
7G and 37C are hardly oxidized, so 34 and 3
The interface with 1 and the interface between 36 and 37 do not move at all.

FIG. 4f shows silicon nitride films 34 and 37.
G and 67C are removed, and an n-type diffusion layer 40 that is connected to the shallow junction depth n-type diffusion layer 38 of the S and D regions and becomes an internal wiring formed in the region A is formed by thermal diffusion method or the like. Also shown is a state in which n-type impurities are simultaneously diffused into the polycrystalline silicon 36G that will become the gate electrode and the polycrystalline silicon 36C that will become the inter-element wiring. At this time, since the n-type impurity diffusion region 38 with a shallow microstructure is protected by the silicon oxide film 39G covering its surface, the n-type impurity is not additionally diffused and the shallow junction depth is maintained. obtain.

In addition, the layer resistance is not lowered by the n-type impurity layer 40 alone, but by the metal silicide layer covering the surface later, so the junction depth is smaller than the shallow junction with the source or drain electrode. There is no need to make the depth particularly deep compared to that of the n-type impurity diffusion layer 38, and the metal silicide layer does not penetrate through the junction when forming the metal silicide layer (42 in FIG. 4(O)) later. Therefore, the depth of the impurity diffusion layer 40 and the channel stopper 3 is sufficient.
2 can be reduced, resulting in the advantage of reduced junction capacitance.

Furthermore, similarly for polycrystalline silicon, the purpose of n-type impurity diffusion is not to lower the layer resistance, but rather to stabilize the interface between the gate electrode 36G and the gate insulating film 35, and to reduce the thickness of the polycrystalline silicon itself. When forming a metal silicide layer later, it is sufficient that the metal silicide layer does not affect the gate electrode structure at all, so it is usually necessary when only polycrystalline silicon is used for the gate electrode or interconnection between elements. The thickness can be reduced to about half (approximately 2500Å),
Surface steps can be significantly reduced, resulting in the advantage of lowering the probability of disconnection of high-order metal wiring.

Furthermore, the reduction in the thickness of the polycrystalline silicon makes it possible to suppress the amount of etching on the side surfaces during etching of the polycrystalline silicon, resulting in the advantage of improved processing dimensional accuracy.

FIG. 4g shows a thin metal film 41 deposited over the entire surface.

FIG. 4h shows the reaction between the metal thin film 41, the exposed surface of the polycrystalline silicon 36G serving as the gate electrode, the polycrystalline silicon 36C serving as the inter-element wiring, and the n-type impurity diffusion layer 40 serving as the internal wiring. After forming the metal silicide layer 42, the unreacted residual metal film covering the surface of the field oxide film 33 and the silicon oxide film 39G on the source or drain electrode is selectively removed using an appropriate etching solution. shows.

As is clear from the explanation of the manufacturing method above,
According to the present invention, until the step of diffusing n-type impurities immediately before depositing metal, the reduction in the thickness of the polycrystalline silicon film and the encroachment in the depth direction of the surface of the impurity diffusion layer, which will become the internal wiring of the device, can be prevented by silicon nitride. Since there is no thermal oxidation process after diffusion of n-type impurities, it is possible to obtain a structure with extremely small surface steps compared to those using normal processes, and the resistance of the parts used as wiring is also low. It is possible to suppress the value to a very small value, and furthermore, the processing accuracy of polycrystalline silicon improves due to the reduction in film thickness, so it is possible to reduce the thickness of polycrystalline silicon, making it possible to reduce the thickness of polycrystalline silicon.
High-performance semiconductor integration that coexists with a structure in which an impurity region with sufficiently low layer resistance and its surface is covered with a metal silicide, and a structure in which a thin polycrystalline silicon surface is covered with a thin metal silicide layer with sufficiently low layer resistance. It has the advantage that the circuit can be manufactured easily and with high precision.

The manufacturing method of the present invention is characterized by a device electrode composed of a second conductivity type impurity layer provided in the device region and having a shallow junction depth, and a second conductivity type impurity layer connected to the second conductivity type impurity layer provided in the active region and having a certain deep junction depth. A part of the first silicon nitride film, which has already been used in the selective oxidation of the field region, is used to form an internal wiring region consisting of a two-layer structure of a type impurity layer and a thin metal silicide covering its surface. The purpose is to separate the substances by allowing them to remain. Further, a second silicon nitride film having approximately the same thickness as the first silicon nitride film used in the selective oxidation method is formed to cover the polycrystalline silicon that forms the gate electrode and the inter-element wiring, The surfaces of the regions not covered with the first and second silicon nitride films and the field oxide film and the side surfaces of the polycrystalline silicon are covered with a somewhat thick oxide film,
Thereafter, the second conductivity type impurity layer having the shallow junction depth is coated with polycrystalline silicon and the intra-element wiring region in the active region having a certain deep junction depth, that is, the above-mentioned covered layer. At the same time, impurities of the second conductivity type are diffused into the surface portions exposed when the silicon nitride film formed in the overlying manner is removed, and then an even thinner metal silicide layer is selectively deposited on both of the exposed surfaces. There is a particular thing.

Therefore, according to the present invention, in a semiconductor integrated circuit that uses polycrystalline silicon as an element electrode, an inter-element wiring, or both, the thickness of polycrystalline silicon is about half that of polycrystalline silicon with a conventional structure. An inter-element interconnect with a first two-layer structure with a low-resistance metal silicide thin film covering it, and an impurity diffusion layer provided in the active region with a certain deep junction depth and a low-resistance metal silicide thin film covering it. A part of the conventional manufacturing method is changed without affecting the electrodes of a high-performance micro-device in which the second two-layer structure internal wiring is formed by a second conductivity type impurity layer with a shallow junction depth. It can be formed with relative ease, and as a result, the performance of the integrated circuit can be greatly improved.

In the present invention, since polycrystalline silicon is etched using a silicon nitride film as a mask, the process up to just before the formation of an impurity diffusion layer for internal wiring with a certain deep junction depth and the diffusion for adding impurities to polycrystalline silicon is also possible. For example, when forming an oxide film covering the surface of a device electrode with a shallow junction depth, there is no decrease in the thickness of polycrystalline silicon, so there is no need to thicken the polycrystalline silicon in advance to account for the decrease, and it is possible to make it thinner from the beginning. This has the advantage that etching accuracy can be improved and surface steps can be lowered. In addition, the position of the surface of the impurity diffusion layer that forms the internal wiring of the device remains exactly the same as the original silicon substrate surface until just before the impurity is diffused, as in the case of polycrystalline silicon, and there is no intrusion in the depth direction. Since there is no difference in surface level, it is possible to almost eliminate the difference in surface level. Such a reduction in the level difference significantly reduces the probability of disconnection of high-order metal wiring, resulting in a dramatic improvement in the yield of large-scale integrated circuits. In addition, since the surface of the impurity diffusion layer with a shallow junction depth will be covered with an oxide film of an appropriate thickness, it is necessary to simultaneously coat the impurity diffusion layer with a certain deep junction depth and polycrystalline silicon, which are connected to the internal wiring of the device. There is no influence at all during the impurity diffusion and the subsequent formation of the metal silicide, which is also performed at the same time, making it possible to realize a high-performance micro element.
Since it is possible to adjust the layer resistance to a sufficiently low value even with a very thin film thickness of about Å, the resistance of internal wiring and inter-element wiring can be made extremely low.
By combining these high-performance fine elements with low-resistance wiring, a high-performance semiconductor integrated circuit can be realized.

For example, if we consider the case where arsenic ions are implanted to obtain shallow source and drain junctions of about 0.3 μm, the layer resistance in this region is usually about several tens of Ω/□, and at the same time, the arsenic The layer resistance of polycrystalline silicon with a thickness of about 4000 Å that has been ion-implanted is also as high as several tens of Ω/□, and it is not uncommon for it to exceed 100 Ω/□. However, according to the present invention, the impurity layer with high layer resistance and shallow junction depth formed in the device region remains in an extremely narrow region that serves as the source or drain, and the active region and polycrystalline silicon that serve as other device interconnections are , 1 to 2 when coated with a metal silicide layer such as platinum silisand
It has the advantage that extremely low layer resistance of Ω/□ can be achieved with a thickness of about 1500 to 2000 Å.

[Brief explanation of the drawing]

FIG. 1a is a partial cross-sectional view schematically showing the basic configuration of a semiconductor integrated circuit that uses miniaturized polycrystalline silicon as element electrodes or inter-element interconnections with the conventional structure. b is a perspective partial cross-sectional view including the surrounding area. Figure 2 shows an improved structure commonly used to solve the drawbacks of the conventional structure shown in Figures 1a and b;
The figure shows a structure that is a further improvement of the structure shown in FIG. 2, and is a perspective partial sectional view for explaining the structure that was proposed prior to the present invention and is basically the object of the present invention. Figures 4a, b, c, d, e, f, g, and h are for explaining the manufacturing method proposed by the present invention to realize the improved structure whose basic configuration is shown in Figure 3. A typical example of the main steps is schematically and conceptually shown in FIG. Each symbol in the figure indicates the following. S :
A region that constitutes a source in an element region.
D : A region constituting a drain in the element region. A : A region in the active region where an impurity layer is formed to serve as wiring within the device. E 1 and E2 : Regions constituting device electrodes, typified by the source and drain of a field effect transistor. F : Feeding point connecting higher-order metal wiring and internal wiring of the element. G: Subscript meaning gate. C: Subscript meaning inter-element wiring. 11,3
1: a first conductivity type semiconductor substrate; 12, 32: a field doping region serving as a channel stopper;
13, 33: Field oxide film, 14, 35: Thin insulating film, 15, 36: Polycrystalline silicon, 16:
A conventional second conductivity type impurity layer having a shallow junction depth that serves as both an element electrode and an inter-element wiring with the same junction depth. 17: A second conductivity type impurity layer with a shallow junction depth dedicated to the device electrode according to an improved proposal. 18: A second conductivity type impurity layer dedicated to internal wiring according to an improved proposal. 19: Metal silicide layer covering the second conductivity type impurity layer and polycrystalline silicon, which is dedicated to internal wiring according to an improved proposal. 34: 1st
37: Second silicon nitride film newly formed by the method of the present invention; 38: Second conductivity type with shallow junction depth formed by the method of the present invention. Impurity layers 17 and 39: silicon oxide film newly formed by the method of the present invention; 40: second conductivity type impurity layer 18 and 41 formed by the method of the present invention; metal thin film; 4
2: Thin metal silicide layer with very low layer resistance formed by the method of the invention.

Claims (1)

[Claims] 1. A first silicon nitride film is formed on the surface of the first conductivity type semiconductor substrate in areas other than regions to be used as inter-element isolation regions, and a channel stopper and field oxide film are formed using this first silicon nitride film as a mask. The first silicon nitride of a part of the first silicon nitride film, that is, a region that will become a future device region, including a region that will become a source and a drain by forming a second conductivity type impurity layer with a shallow junction depth. After removing the film, a thin insulating film that will become a gate insulating film in the future is formed on the entire surface of this removed region, and a polycrystalline silicon layer is further applied to the region that will become a gate electrode and the interconnection between elements in the future. The second silicon nitride film is formed by patterning together with the second silicon nitride film, and the exposed thin insulating film is passed through the second silicon nitride film, the polycrystalline silicon layer, and the remaining portion of the first silicon nitride film as a mask. An impurity exhibiting a second conductivity type is shallowly introduced into the surface layer of the first conductivity type substrate to form a second conductivity type impurity layer having a shallow junction depth with the source and drain, and then the exposed thin insulating layer is formed. A silicon oxide film is formed on the film and the exposed surface layer of the polycrystalline silicon layer, the remaining first silicon nitride film and second silicon nitride film are removed, and an impurity exhibiting a second conductivity type is introduced from this removed region. A second conductivity type impurity layer having a deep junction depth connected to the second conductivity type impurity layer having a shallow junction depth is formed on the first conductivity type semiconductor substrate in the first silicon nitride film region to form an element. The polycrystalline silicon layer in the second silicon nitride film region is also used as an inter-element wiring of the second conductivity type, and furthermore, the second conductivity type impurity layer and the polycrystalline silicon layer at the deep junction depth. A method of manufacturing a semiconductor integrated circuit characterized by covering the surface with a thin metal silicide.