JPS6152482B2 - - Google Patents

Info

Publication number
JPS6152482B2
JPS6152482B2 JP17255979A JP17255979A JPS6152482B2 JP S6152482 B2 JPS6152482 B2 JP S6152482B2 JP 17255979 A JP17255979 A JP 17255979A JP 17255979 A JP17255979 A JP 17255979A JP S6152482 B2 JPS6152482 B2 JP S6152482B2
Authority
JP
Japan
Prior art keywords
signal
waveform storage
storage means
waveform
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP17255979A
Other languages
Japanese (ja)
Other versions
JPS5696303A (en
Inventor
Yasuhiro Goto
Masahiro Deguchi
Noboru Wakami
Mitsuro Morya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17255979A priority Critical patent/JPS5696303A/en
Publication of JPS5696303A publication Critical patent/JPS5696303A/en
Publication of JPS6152482B2 publication Critical patent/JPS6152482B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明はフイードバツク制御系の制御信号等の
周期的変化を有する信号波形の記憶装置に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device for signal waveforms having periodic changes such as control signals of a feedback control system.

例えば特願昭54−91868(特開昭56−16918)、
特願昭54−91870(特開昭56−16946)、特願昭54
−82238(特開昭56−7247)等には、磁気的ある
いは光学的記録再生装置における記録、消去、検
索(再生)時のデイスク状記録媒体着脱に伴い発
生する機械的偏心等の記録済情報トラツクのひず
み形状を補償する偏心補償方法が述べられてい
る。これらの偏心補償方法は、デイスク状記録媒
体着脱に伴う情報トラツクのひずみ(偏心により
発生するトラツクの曲り)を、このひずみ形状に
追従してトラツキング制御を行ない、ひずみ形状
に対応したトラツキング制御信号(情報トラツク
1周を再生するのに要する時間を基本周期とした
周期性信号)を得、このトラツキング制御信号を
波形記憶装置に記憶し、この波形記憶装置に記憶
された信号の読み出し信号により、前記トラツキ
ング制御系を励振して情報トラツクのひずみに対
応した偏心補償を行なうものである。
For example, Japanese Patent Application No. 54-91868 (Japanese Unexamined Patent Publication No. 56-16918),
Patent application 1987-91870 (Japanese Patent Application No. 1983-16946), Patent application 1983
-82238 (Japanese Unexamined Patent Publication No. 56-7247) etc., contains recorded information such as mechanical eccentricity that occurs when a disk-shaped recording medium is attached and detached during recording, erasing, and retrieval (reproduction) in magnetic or optical recording and reproducing devices. An eccentricity compensation method is described to compensate for the distorted shape of the track. These eccentricity compensation methods perform tracking control to follow the distortion shape of the information track distortion (track bending caused by eccentricity) caused by the insertion and removal of a disk-shaped recording medium, and generate a tracking control signal (corresponding to the distortion shape). A periodic signal whose basic period is the time required to reproduce one revolution of the information track is obtained, this tracking control signal is stored in a waveform storage device, and the readout signal of the signal stored in the waveform storage device is used to perform the above-mentioned tracking control signal. The tracking control system is excited to perform eccentricity compensation corresponding to the distortion of the information track.

本発明は、これら偏心補償等に用いる制御信号
の波形記憶装置の高精度化を目的とするものであ
る。
The present invention aims to improve the precision of a waveform storage device for control signals used for eccentricity compensation and the like.

先ず第1図において、静止画像を記録する光学
的記録再生装置における偏心補償方法の一例を説
明する。第1図において、光源1から光ビーム2
が発せられ、該光ビーム2は変調器3により適当
な強度にされた光ビーム2aとなり、ビームスプ
リツタ4、回転鏡5を介して集束対物レンズ6に
入り、微小スポツト径に絞られ、デイスク駆動モ
ータ7により回転駆動されるデイスク状記録媒体
8に照射される。このデイスク状記録媒体8は照
射光ビーム20の強度が強いとき媒体の物理的・
化学的変化によつて光学的性質が変わり、光学的
記録が行なえ、更に強くすると光学的消去が可能
な周知のアモルフアス材料の様なものを用いる。
この種の材料では照射光ビーム2aの強度が前記
記録時より弱いとき記録媒体の物理的・化学的変
化はなく、記録も消去も行なわれない。この弱め
られた光ビームを照射して情報トラツクの再生を
行なつている。また、デイスク状記録媒体8には
同心円状に1フレームの静止画像信号が1本の情
報トラツクに記録されており、前記デイスク駆動
モータ7は映像信号中のフレーム同期信号に同期
回転し、NTSC方式テレビジヨン信号の場合
1800RPM(毎秒30回転)、PALあるいはSECAM
方式テレビジヨン信号のとき1500RPM(毎秒25
回転)の回転速度で回転基準信号に同期して回転
している。デイスク状記録媒体8はデイスク駆動
モータ7により回転駆動され、その平面性の悪さ
に起因した面振れ等により前記対物レンズ6との
距離が変化して、充分な微少スポツトに絞られな
い光ビーム2aが照射される恐れがある。このた
め照射する光ビーム2aが最小径に絞られる集束
点上にデイスク状記録媒体8の信号記録面が位置
するように、集束用対物レンズ6を位置制御する
ための可動コイル9が設けられ、この可動コイル
9は既に周知の集点制御方法により制御されてい
る。また、集点制御を行なつた上に情報トラツク
のひずみに追従して光ビーム2aを走査させるト
ラツキング制御を行なつているが、このトラツキ
ング制御についても、既に多くの周知な方法が提
案されており、詳細な説明は略す。第1図では情
報トラツクに照射された光ビーム2aの反射光2
bを集束用対物レンズ6、回転鏡5を介してビー
ムスプリツタ4で反射させ、シリンドリカルレン
ズ10を介して光検出器11に照射する周知の光
学系が構成され、光検出器11から光ビーム2a
のトラツキングずれ量に対応して発生する情報ト
ラツクのひずみ形状に対応したトラツキング信号
S1が得られる。このトラツキング信号S1はトラツ
キング制御回路12に加えられ、信号処理された
トラツキング制御信号S2となる。このトラツキン
グ制御信号S2は波形記憶装置3に加えられ、トラ
ツク長手方向の位置に対応して情報トラツク1周
について記憶されるとともに、信号切換スイツチ
SWのB接点に該波形記憶装置13の読み出し信
号S3が加えられる。トラツキング制御時、信号切
換スイツチSWはA接点に接続され、回転鏡駆動
回路14にはトラツキング制御信号S2が供給さ
れ、回転鏡5を励振して情報トラツクのひずみ形
状に追従したフイードバツク制御ループを有する
トラツキング制御が行なわれている。
First, with reference to FIG. 1, an example of an eccentricity compensation method in an optical recording/reproducing apparatus for recording still images will be described. In FIG. 1, a light beam 2 is emitted from a light source 1.
is emitted, and the light beam 2 is made into a light beam 2a with an appropriate intensity by a modulator 3, enters a focusing objective lens 6 via a beam splitter 4 and a rotating mirror 5, is condensed to a minute spot diameter, and is focused on a disk. A disk-shaped recording medium 8 rotated by a drive motor 7 is irradiated with light. When the intensity of the irradiated light beam 20 is strong, the disk-shaped recording medium 8
A material such as a well-known amorphous material is used, which has optical properties that change through chemical changes, allows optical recording, and when strengthened, can be optically erased.
In this type of material, when the intensity of the irradiated light beam 2a is weaker than that during recording, there is no physical or chemical change in the recording medium, and neither recording nor erasing occurs. The information track is reproduced by irradiating this weakened light beam. Further, a still image signal of one frame is concentrically recorded on one information track on the disk-shaped recording medium 8, and the disk drive motor 7 rotates in synchronization with a frame synchronization signal in the video signal, and uses the NTSC system. For television signals
1800RPM (30 revolutions per second), PAL or SECAM
1500 RPM (25 rpm per second) for standard television signals
It is rotating in synchronization with the rotation reference signal at a rotation speed of (rotation). The disk-shaped recording medium 8 is rotationally driven by a disk drive motor 7, and the distance from the objective lens 6 changes due to surface wobbling caused by its poor flatness, resulting in the light beam 2a not being focused into a sufficiently small spot. may be irradiated. For this purpose, a movable coil 9 is provided to control the position of the focusing objective lens 6 so that the signal recording surface of the disk-shaped recording medium 8 is located on the focal point where the irradiated light beam 2a is focused to the minimum diameter. This moving coil 9 is already controlled by a well-known convergence control method. Furthermore, in addition to convergence control, tracking control is performed in which the light beam 2a is scanned by following the distortion of the information track, and many well-known methods have already been proposed for this tracking control. Therefore, detailed explanation will be omitted. In FIG. 1, reflected light 2 of a light beam 2a irradiated onto an information track is shown.
A well-known optical system is constructed in which the beam is reflected by a beam splitter 4 via a focusing objective lens 6 and a rotating mirror 5, and is irradiated onto a photodetector 11 via a cylindrical lens 10. 2a
A tracking signal corresponding to the distortion shape of the information track that occurs in response to the amount of tracking deviation of
S 1 is obtained. This tracking signal S 1 is applied to the tracking control circuit 12 and becomes a tracking control signal S 2 which undergoes signal processing. This tracking control signal S2 is applied to the waveform storage device 3, and is stored for one round of the information track in correspondence with the position in the longitudinal direction of the track.
The readout signal S3 of the waveform storage device 13 is applied to the B contact of SW. During tracking control, the signal changeover switch SW is connected to contact A, and the tracking control signal S2 is supplied to the rotating mirror drive circuit 14, which excites the rotating mirror 5 to create a feedback control loop that follows the distortion shape of the information track. Tracking control is being performed.

さて、トラツキング制御信号S2は前述したよう
に偏心等に起因して生ずる情報トラツクのひずみ
に対応した情報を持つた信号であり、情報トラツ
ク1周を再生する周期、つまりデイスク駆動モー
タ7の1回転に要する周期を基本周期とする周期
性信号である。この信号S2を回転鏡駆動回路14
に加えて回転鏡5を励振し、光ビーム2aが情報
トラツクのひずみ形状に追従してデイスク状記録
媒体8の信号記録面上を走査するトラツキング制
御系が構成されている。また、信号S2と、これを
記憶した波形記憶装置13の出力信号S3とは等価
なものであり、信号切換スイツチSWをB接点に
切り換え、信号S2の代りに信号S3を回動鏡駆動回
路14に加えて回動鏡5を励振しても、光ビーム
2aは情報トラツクのひずみ形状に追従してデイ
スク状記録媒体8の前記トラツキング制御を行つ
た情報トラツク上を走査し、前記デイスク状記録
媒体8の着脱に伴つて生ずる偏心等に起因した情
報トラツクのひずみ形状を補償する偏心補償が行
なわれる。
Now, as mentioned above, the tracking control signal S2 is a signal having information corresponding to the distortion of the information track caused by eccentricity, etc., and corresponds to the period for reproducing one revolution of the information track, that is, one It is a periodic signal whose basic period is the period required for rotation. This signal S2 is sent to the rotating mirror drive circuit 14.
In addition, a tracking control system is constructed in which the rotating mirror 5 is excited and the light beam 2a scans the signal recording surface of the disk-shaped recording medium 8 by following the distorted shape of the information track. Also, the signal S 2 and the output signal S 3 of the waveform storage device 13 that stores it are equivalent, so the signal changeover switch SW is switched to the B contact, and the signal S 3 is rotated instead of the signal S 2 . Even if the rotary mirror 5 is excited in addition to the mirror drive circuit 14, the light beam 2a scans the information track on the disk-shaped recording medium 8, which has been subjected to the tracking control, following the distorted shape of the information track. Eccentricity compensation is performed to compensate for the distorted shape of the information track due to eccentricity that occurs when the disk-shaped recording medium 8 is attached or removed.

この様なトラツキング制御信号を波形記憶し、
この記憶した信号によりトラツキング制御系を励
振して偏心補償を行う偏心補償方法において、そ
の補償精度は波形記憶装置の記憶精度に依存し、
精度の高い補償を行うためには、信号波形記憶装
置の記憶精度向上を計らねばならない。
The tracking control signal like this is stored in waveform,
In the eccentricity compensation method in which the tracking control system is excited by the stored signal to compensate for eccentricity, the compensation accuracy depends on the storage accuracy of the waveform storage device.
In order to perform highly accurate compensation, it is necessary to improve the storage accuracy of the signal waveform storage device.

さて、この波形記憶装置として用いられていた
もの、例えば特願昭54−91870(特開昭56−
16946)号の記載した波形記憶装置は、情報トラ
ツク1周(デイスク駆動モータの1回転に要する
期間)において、トラツキング制御信号を記憶す
る。あるいは何周かにわたつて平均化した記憶を
行う等の手段が講ぜられていた。しかし、これら
の方法では、波形記憶装置に使用するアナログ―
デイジタル変換器(以下ADCと略記)、半導体の
デイジタルメモリ(例えば周知のランダムアクセ
スメモリを用い、以下RAMと略記)、デイジタル
―アナログ変換器(以下DACと略記)等の分解
能に起因した量子化誤差、アナログ回路系
(ADC,DACを含む)に生ずるオフセツト電圧と
非線形ひずみ、被記憶信号と記憶信号間に振幅差
が生ずる利得誤差、この両信号間に位相差が生ず
る位相誤差等の波形記憶精度劣化要因が補正され
ることなく直接波形記憶誤差となり、記憶精度向
上を計るためには上記ADC,DAC,RAMの分解
能の向上対策、オフセツト電圧の調整、直線性の
良いアナログ回路の使用、利得の調整、RAMの
読み出しと書き込み時のタイミングをずらして読
し出し信号の位相調整を行つて位相誤差を少なく
する位相調整(この位相調整について特願昭54−
91870(特開昭56−16946)号に記載されている)
等が必要となつて一回路コストの上昇および調整
が複雑になる等の欠点を有していた。またこれら
の精度向上手段を講じても限界があつた。
Now, what was used as this waveform storage device, for example, Japanese Patent Application No. 54-91870 (Japanese Unexamined Patent Publication No. 56-56
The waveform storage device described in No. 16946 stores tracking control signals during one revolution of the information track (the period required for one revolution of the disk drive motor). Alternatively, measures were taken such as averaging the memorization over several laps. However, in these methods, the analog-
Quantization errors caused by the resolution of digital converters (hereinafter abbreviated as ADC), semiconductor digital memories (for example, using well-known random access memory, hereinafter abbreviated as RAM), digital-to-analog converters (hereinafter abbreviated as DAC), etc. , offset voltage and nonlinear distortion that occur in analog circuit systems (including ADCs and DACs), gain errors that occur when there is an amplitude difference between the stored signal and the stored signal, and phase errors that occur when there is a phase difference between these two signals, etc. Waveform storage accuracy The deterioration factors are not corrected and directly result in waveform memory errors. To improve memory accuracy, it is necessary to take measures to improve the resolution of the ADC, DAC, and RAM mentioned above, adjust the offset voltage, use analog circuits with good linearity, and increase the gain. Adjustment, phase adjustment that reduces the phase error by adjusting the phase of the read signal by shifting the timing of reading and writing to RAM
91870 (Japanese Patent Publication No. 56-16946))
etc., resulting in increased circuit cost and complicated adjustment. Moreover, even if these precision improvement measures were taken, there were limits.

本発明はかかる波形記憶装置の欠点に鑑み、2
つの記憶手段を設け、第1の記憶手段により波形
記憶した信号と被記憶信号との差(第1の記憶手
段の波形記憶誤差)を求め、この差信号を第2の
記憶手段により記憶して、第1の記憶手段の記憶
信号に第2の手段の記憶信号を混合し、第1の記
憶手段によつて生じる記憶誤差を補正した信号を
記憶として用いることにより、簡単な調整で安価
な回路部品(高精度でない回路部品)を用いなが
ら誤差の少ない波形記憶装置を提供するものであ
る。
In view of the drawbacks of such waveform storage devices, the present invention provides two
A difference signal between the signal whose waveform has been stored in the first storage means and the signal to be stored (waveform storage error of the first storage means) is obtained, and this difference signal is stored in the second storage means. By mixing the storage signal of the first storage means with the storage signal of the second means and using the signal corrected for the storage error caused by the first storage means as the storage, an inexpensive circuit with simple adjustment can be achieved. The present invention provides a waveform storage device that uses components (circuit components that are not highly accurate) and has fewer errors.

以下図面を用いて本発明の一実施例を図面に基
づいて説明する。第2図は例えば前記第1図の波
形記憶装置13に適用し得るブロツク図である。
第2図において、波形記憶装置13は第1の波形
記憶手段15、第2の波形記憶手段16、差動増
幅器17、制御回路19、混合増幅器18から成
つている。波形記憶手段15および16は、例え
ば前記特願昭54−91870(特開昭56−16946)号に
示したような波形記憶手段でもつて構成可能であ
り、それぞれ入力信号処理用の低域通過フイルタ
20,26、サンプルホールド回路21,27、
ADC22,28、RAM23,29、DAC24,
30、出力信号処理用の低域通過フイルタ25,
31より成つており、制御回路19により波形の
記憶や読み出しが制御される。
An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram that can be applied to the waveform storage device 13 of FIG. 1, for example.
In FIG. 2, the waveform storage device 13 includes a first waveform storage means 15, a second waveform storage means 16, a differential amplifier 17, a control circuit 19, and a mixing amplifier 18. The waveform storage means 15 and 16 can be constituted by waveform storage means as shown in the above-mentioned Japanese Patent Application No. 54-91870 (Japanese Unexamined Patent Publication No. 56-16946), and each includes a low-pass filter for input signal processing. 20, 26, sample and hold circuits 21, 27,
ADC22, 28, RAM23, 29, DAC24,
30, low-pass filter 25 for output signal processing,
31, and storage and reading of waveforms are controlled by a control circuit 19.

第2図において、第1の波形記憶手段15は第
3図の如くt1〜t2の期間(情報トラツク1周を読
み出すのに必要な期間)において入力信号である
周期性信号S2(情報トラツク1周を読み出すのに
要する時間を基本周期とする)の波形記憶を行
い、過渡時間t2〜t3を経てt3以降第1の読み出し
信号S5を得る。この信号S5は、混合増幅器18に
加えられるとともに差動増幅器17に加えられ、
前記信号S2と信号S5の差に対応した出力信号S6
得られる。信号S6と信号S2,S5の関係は次式(1)に
示す様な関係となる。
In FIG. 2, the first waveform storage means 15 receives a periodic signal S 2 (information The waveform is stored for a period of time (the time required to read out one track round as a basic period), and a first read signal S5 is obtained from t3 through a transition time t2 to t3 . This signal S 5 is applied to the mixing amplifier 18 and also to the differential amplifier 17,
An output signal S 6 corresponding to the difference between the signal S 2 and the signal S 5 is obtained. The relationship between the signal S 6 and the signals S 2 and S 5 is as shown in the following equation (1).

S6=S2−S5 ……(1) そして該信号S6は第2の波形記憶手段16に加え
られ、過渡期間t3〜t4を経た後t4〜t5の期間(情報
トラツク1周を読み出すのに要する期間)におい
て、信号S6の波形記憶を行い、過渡期間t5〜t6
経た後t6以降第2の読み出し信号S7を得ている。
この信号S7は読み出されると同時に混合増幅器1
8に加えられ、前記第1の読み出し信号S5と第2
の読み出し信号S7を混合した出力信号S3を得る。
該信号S3は波形記憶回路13の読み出し信号とな
る。
S 6 =S 2 −S 5 (1) Then, the signal S 6 is applied to the second waveform storage means 16, and after passing through the transition period t 3 to t 4 , it is stored in the period t 4 to t 5 (information track). The waveform of the signal S6 is stored during the period required to read out one round, and after a transition period from t5 to t6 , a second readout signal S7 is obtained from t6 onwards.
This signal S7 is simultaneously read out and sent to the mixing amplifier 1.
8, the first read signal S 5 and the second
An output signal S3 is obtained by mixing the readout signal S7 .
The signal S 3 becomes a read signal for the waveform storage circuit 13.

なお第2図において、差動増幅器17に加える
信号を第1の波形記憶手段15の出力信号S5と信
号S2ではなく、混合増幅器18の出力信号S3を信
号S2とともに加え、両者の差信号として信号S6
得てもよい。ただしこの場合混合増幅器18の信
号S7が加わる入力端子を少なくとも第3図のt3
t5に至る期間において基底電位(通常零電位)に
せねばならない。そして信号S6を第2の波形記憶
手段16により記憶した後に、この記憶された信
号を読み出し、信号S7として混合増幅器18に加
えて誤差補正を行なう。この方法を用いると、混
合増幅器18の入力信号S5に対する誤差の補正を
行える。
Note that in FIG. 2, the signal to be applied to the differential amplifier 17 is not the output signal S 5 of the first waveform storage means 15 and the signal S 2 , but the output signal S 3 of the mixing amplifier 18 is added together with the signal S 2 , and both The signal S6 may be obtained as a difference signal. However, in this case, the input terminal to which the signal S 7 of the mixing amplifier 18 is applied is connected at least to t 3 in FIG.
The base potential (usually zero potential) must be maintained during the period leading up to t5 . After the signal S 6 is stored in the second waveform storage means 16, this stored signal is read out and added to the mixing amplifier 18 as a signal S 7 for error correction. Using this method, errors in the input signal S5 of the mixing amplifier 18 can be corrected.

され、第2図に示した波形記憶装置13の波形
記憶誤差について述べる。被測定信号である周期
性信号S2のスペクトラムをそれぞれ直流成分
A20、基本波成分A21、n次高周波成分(基本波
に対するn次高周波成分)をA2oとし、これを記
憶した信号S5のスペクトラムをそれぞれ直流成分
A50、基本波成分A51、n次高周波成分A5oとする
となる。ただしδ10,δ11,δ1oは各スペクトラ
ムにおける第1の波形記憶手段15の有する記憶
誤差である。また(2)式の関係より信号S2と信号S5
の差である信号S6は、そのスペクトラム成分をそ
れぞれ直流成分A60、基本波成分A61、n次高周
波成分A6oとすると となる。この信号S6を第2の波形記憶手段16に
より記憶し読み出した信号S7のスペクトラムをそ
れぞれ直流成分A70、基本波成分A71、n次高周
波成分A7oとすると となる。ただしδ20,δ21,δ2oは各スペクトラ
ムにおける第2の波形記憶手段16の有する記憶
誤差である。また、波形記憶装置13の読み出し
信号S3は信号S2と信号を混合したものであり、
スペクトラムをそれぞれ直流成分A30、基本波成
分A31、n次高周波成分A3oとすると となり、各スペクトルにおける信号S2に対する信
号S3の記憶誤差は、第1の記憶手段15による記
憶誤差と第2の記憶手段16による記憶誤差(1
より小さい)を掛け合せたものとなり、非常に小
さな値にまで軽減できる。例えばδ1o,δ2oとも
に3%=0.03のときA3oの有する記憶誤差δ1o
δ2oは0.03×0.03=0.0009=0.09%となる。また
A30,A31についても同様である。
The waveform storage error of the waveform storage device 13 shown in FIG. 2 will be described. The spectrum of the periodic signal S2 , which is the signal under test, is divided into DC components.
A 20 , the fundamental wave component A 21 , and the n-th high frequency component (the n-th high frequency component with respect to the fundamental wave) are A 2o , and the spectrum of the signal S 5 in which these are stored is the DC component, respectively.
A 50 , fundamental wave component A 51 , n-th high frequency component A 5o becomes. However, δ 10 , δ 11 , and δ 1o are storage errors of the first waveform storage means 15 in each spectrum. Also, from the relationship in equation (2), signal S 2 and signal S 5
The signal S 6 , which is the difference between becomes. If this signal S 6 is stored in the second waveform storage means 16 and the spectra of the read signal S 7 are respectively designated as a DC component A 70 , a fundamental wave component A 71 , and an n-th high frequency component A 7o becomes. However, δ 20 , δ 21 , and δ 2o are storage errors of the second waveform storage means 16 in each spectrum. Further, the read signal S 3 of the waveform storage device 13 is a mixture of the signal S 2 and the signal 7 ,
If the spectra are respectively a DC component A 30 , a fundamental wave component A 31 , and an n-th high frequency component A 3o Therefore, the storage error of the signal S 3 with respect to the signal S 2 in each spectrum is the storage error of the first storage means 15 and the storage error of the second storage means 16 (1
), and can be reduced to a very small value. For example, when both δ 1o and δ 2o are 3%=0.03, the memory error δ 1o of A 3o is
δ 2o is 0.03×0.03=0.0009=0.09%. Also
The same applies to A 30 and A 31 .

例えば第1図に示した偏心補償に第2図に示し
た波形記憶装置13を用いる場合、最大偏心量を
±100μmとし、波形記憶装置13で生じる許容
誤差を±0.1μm以内とすると、波形記憶装置1
3の有する記憶誤差が±0.1%(=±1/1000)以
下の微少誤差の装置を用いなければならない。し
かし、誤差補正を行なわない波形記憶装置におい
ては、前記した分解能ひずみ、ドリフト振幅誤
差、位相誤差等を考慮したとき上記±0.1%以下
の誤差に抑制することは至難の業である。しかし
ながら、本発明を適用すれば第1,第2の波形記
憶手段各々が単独に有する誤差が大きくとも、第
1の波形記憶手段によつて発生する記憶誤差を第
2の記憶手段によつて補正するため、記憶装置の
最終的誤差は相乗効果により前記した各々の波形
記憶装置の有する誤差が3%程度であつても前記
許容値±0.1%を容易に達成できる。実際には差
動増幅器17および混合増幅器18においても誤
差が発生し、これが波形記憶装置13の記憶誤差
に加算される。しかし、これらは特別高精度で高
価な部品を使用せずとも市販されている汎用演算
増幅器を用いて0.1%以下の高精度なものが容易
に実現できる。
For example, when using the waveform storage device 13 shown in FIG. 2 for the eccentricity compensation shown in FIG. Device 1
3, a device with a very small memory error of ±0.1% (=±1/1000) or less must be used. However, in a waveform storage device that does not perform error correction, it is extremely difficult to suppress the error to ±0.1% or less when the above-mentioned resolution distortion, drift amplitude error, phase error, etc. are considered. However, if the present invention is applied, even if the error that each of the first and second waveform storage means individually has is large, the storage error generated by the first waveform storage means can be corrected by the second storage means. Therefore, due to the synergistic effect, the final error of the storage device can easily achieve the tolerance value of ±0.1% even if the error of each of the waveform storage devices described above is about 3%. In reality, errors also occur in the differential amplifier 17 and the mixing amplifier 18, and are added to the storage error in the waveform storage device 13. However, these can be easily achieved with a high precision of 0.1% or less using commercially available general-purpose operational amplifiers without using particularly high-precision and expensive parts.

また第2図において、信号S6は、S6=S2−S5
したとき信号S2あるいは信号S5と比較するため一
般に低レベルの信号となる。このため、第2の波
形記憶手段16のADC28が有する分解能を有
効活用すべく差動増幅器17に利得をもたせS6
Sα・(S2−S5)(αは1以上)とした信号S6を第
2の波形記憶手段16により記憶し、その読み出
した信号を混合増幅器18で混合する際、混合増
幅器18の有する信号S5の利得に対し、1/αの
利得で混合すれば、等価的に波形記憶装置13の
分解能を向上させることができる。例えばADC
22,28、DAC24,30、およびRAM2
3,29の分解能を8ビツトとし、前記差動増幅
器17の利得αをα=16にすれば、波形記憶装置
13の分解能として12ビツトのものが得られる。
この分解能を向上させる方法は差動増幅器17の
利得のみならず、入力信号処理用の低域通過フイ
ルタ26、サンプルホールド回路27、ADC2
8に至る系の利得により実現してもよく、読み出
し信号S7を1/αにする手段としては、DAC3
0や出力信号処理用の低域通過フイルタ31の利
得、あるい信号S7に対する混合増幅器18の利得
により実現可能である。
Further, in FIG. 2, the signal S 6 is generally a low level signal for comparison with the signal S 2 or the signal S 5 when S 6 =S 2 -S 5 . Therefore, in order to effectively utilize the resolution of the ADC 28 of the second waveform storage means 16, the differential amplifier 17 is provided with a gain so that S 6 =
When the signal S 6 of Sα·(S 2 −S 5 ) (α is 1 or more) is stored in the second waveform storage means 16 and the read signal is mixed by the mixing amplifier 18, the signal S 6 of the mixing amplifier 18 is By mixing the signals at a gain of 1/α with respect to the gain of the signal S 5 , the resolution of the waveform storage device 13 can be equivalently improved. For example ADC
22, 28, DAC24, 30, and RAM2
If the resolution of the waveform storage device 13 is set to 8 bits and the gain α of the differential amplifier 17 is set to α=16, the resolution of the waveform storage device 13 will be 12 bits.
The method for improving this resolution is not limited to the gain of the differential amplifier 17, but also the low-pass filter 26 for input signal processing, the sample hold circuit 27, and the ADC 2.
It may be realized by the gain of the system up to 8, and as a means to reduce the read signal S7 to 1/α, the DAC3
0, the gain of the low-pass filter 31 for output signal processing, or the gain of the mixing amplifier 18 for the signal S7 .

第2図においては、独立した波形記憶手段を2
個用いた例について説明したが、第4図に記す様
に入力信号処理用の低域通過フイルタ32(第2
図の30,26)、サンプルホールド回路33、
(第2図の21,27)、ADC34(第2図の2
2,28)、DAC36(第2図の24,30)、
出力信号処理用の低域通過フイルタ37(第2図
の25,31)を第1および第2の波形記憶手段
において共用し、回路の簡易化を計つてもよい。
In Figure 2, two independent waveform storage means are used.
Although we have described an example in which a low-pass filter 32 (second filter) for input signal processing is used, as shown in FIG.
30, 26) in the figure, sample and hold circuit 33,
(21, 27 in Figure 2), ADC34 (2 in Figure 2)
2, 28), DAC36 (24, 30 in Figure 2),
The low-pass filter 37 (25, 31 in FIG. 2) for output signal processing may be shared by the first and second waveform storage means to simplify the circuit.

この際例えば、第1の波形記憶手段は切換スイ
ツチSW2をC接点に接続し、該C接点から被記憶
信号S2(第2図同様の周期性信号)が入力される
時は、第1の波形記憶手段は入力信号処理用の低
域通過フイルタ32、サンプルホールド回路3
3、ADC34、RAM35、DAC36、出力信号
処理用の低域通過フイルタ37による構成とな
り、第1の波形記憶手段による波形記憶動作時、
RAM40と加算器41は動作しない。該構成の
第1の波形記憶手段により被記憶信号S2を記憶
し、読み出した信号S3を被記憶信号S2とともに差
動増幅器39に供給して両者の差に対応した信号
S3を得る。該信号S8が第1の波形記憶手段による
記憶誤差となる。次に、誤差記憶を行なうべく切
換スイツチSW2をD接点に接続し、信号S8を入力
する時は、入力信号処理用の低域通過フイルタ3
2、サンプルホールド回路33、ADC34を介
してデイジタル信号S9に変換し、信号S9の記憶を
行なわない)この変換した信号S9をRAM40に
記憶する第2の波形記憶手段が形成される。記憶
終了後RAM40およびRAM35のそれぞれに対
応したアドレスに記憶されている信号S′9および
S10を読み出して加算器41に加え、両者を加算
したデイジタル信号S11をRAM35に記憶する。
このときRAM35に記憶されている第1の波形
記憶手段による波形記憶信号は、第1および第2
の波形記憶手段の加算結果であるデイジタル信号
S11に書きかえられ、この書きかえ終了後のRAM
35の読し出し信号S10は信号S11と等しくなり、
第1および第2の波形記憶手段による波形記憶信
号を加算したものと等しくなる。加算および加算
結果のRAM35への記憶を全記憶データ(情報
トラツク1周相当のデータ)について行つた後、
RAM35に記憶された加算結果であるデイジタ
ル信号を読み出す。このRAM35の読み出し加
算信号S10はDAC36出力信号処理用の低域通過
フイルタ37を経て信号S3となる。また読み出し
加算信号S10は第1の波形記憶手段による記憶結
果と信号S8の記憶結果の加算されたものであり、
第1の波形記憶手段による記憶誤差を補正したも
のとなり、信号S3として誤差補正のなされた記憶
精度の良い信号が得られる。尚、制御回路38は
以上説明した第4図における各回路の制御を行つ
ている。
At this time, for example, the first waveform storage means connects the changeover switch SW 2 to the C contact, and when the memorized signal S 2 (periodic signal similar to FIG. 2) is input from the C contact, the first waveform storage means The waveform storage means includes a low-pass filter 32 for input signal processing and a sample hold circuit 3.
3. It is composed of ADC 34, RAM 35, DAC 36, and low-pass filter 37 for output signal processing, and when the first waveform storage means performs waveform storage operation,
RAM 40 and adder 41 do not operate. The first waveform storage means having the above structure stores the stored signal S 2 and supplies the read signal S 3 together with the stored signal S 2 to the differential amplifier 39 to generate a signal corresponding to the difference between the two.
Get S3 . The signal S8 becomes a storage error by the first waveform storage means. Next, connect the changeover switch SW 2 to the D contact to store the error, and when inputting the signal S 8 , use the low-pass filter 3 for input signal processing.
2. A second waveform storage means is formed which stores the converted signal S 9 in the RAM 40 (the signal S 9 is converted into a digital signal S 9 via the sample and hold circuit 33 and the ADC 34 and the signal S 9 is not stored). After the storage is completed, the signals S'9 and S'9 stored at the addresses corresponding to RAM40 and RAM35, respectively, are
S10 is read out and added to the adder 41, and a digital signal S11 obtained by adding the two is stored in the RAM 35.
At this time, the waveform storage signal stored in the RAM 35 by the first waveform storage means is stored in the first and second waveform storage means.
A digital signal that is the addition result of the waveform storage means of
Rewritten to S 11 , RAM after this rewriting is completed
The read signal S 10 of 35 is equal to the signal S 11 ,
It is equal to the sum of the waveform storage signals from the first and second waveform storage means. After adding and storing the addition results in the RAM 35 for all stored data (data equivalent to one revolution of the information track),
The digital signal which is the addition result stored in the RAM 35 is read out. The read addition signal S 10 from the RAM 35 passes through a low-pass filter 37 for processing the output signal of the DAC 36 and becomes a signal S 3 . Further, the read addition signal S10 is the sum of the storage result of the first waveform storage means and the storage result of the signal S8 ,
The memory error caused by the first waveform storage means is corrected, and a signal with good memory accuracy and error correction is obtained as the signal S3 . Note that the control circuit 38 controls each circuit in FIG. 4 described above.

また、第4図に示した実施例においても、第2
図同様、波形記憶回路13の分解能を上げるため
差動増幅器17の利得をα倍(αは1以上)にし
て信号S8をRAM40に記憶し、これを加算器4
1に加算する時点でRAM35の読み出し信号S10
に対しRAM40の読み出し信号S′9の桁を下げて
1/αにし加算してもよい加算器41においてデ
イジタル信号である信号S′9と信号S10の加算を行
うため前記αを2n(nは1以上の整数)に設定
する加算時の信号処理が簡単となる。この際、
RAM35、DAC36の有する分解能をADC3
4、RAM40より高くする必要がある。例えば
α=16(=24)としたときADC34およびRAM4
0の分解能を8ビツト、RAM35およびDAC3
6の分解能を12ビツトにし、加算器41において
信号S10の最上位桁に対して信号S′9の最上位桁を
4ビツトずらして(下げて)加算する。
Also, in the embodiment shown in FIG.
Similarly to the figure, in order to increase the resolution of the waveform storage circuit 13, the gain of the differential amplifier 17 is multiplied by α (α is 1 or more), and the signal S8 is stored in the RAM 40.
At the time of addition to 1, read signal S 10 of RAM35
In contrast, the digit of the read signal S' 9 of the RAM 40 may be lowered to 1/α and added. In order to add the signal S' 9 and the signal S 10 , which are digital signals, in the adder 41, the above α is 2 n ( (n is an integer greater than or equal to 1), signal processing during addition becomes easier. On this occasion,
The resolution of RAM35 and DAC36 is changed to ADC3
4. Must be higher than RAM40. For example, when α=16 (=2 4 ), ADC34 and RAM4
0 resolution 8 bits, RAM35 and DAC3
The resolution of the signal S'9 is set to 12 bits, and the adder 41 shifts (lowers) the most significant digit of the signal S'9 by 4 bits and adds it to the most significant digit of the signal S10 .

更に、信号S2は周期性の信号であるが、例えば
第1図に示したトラツキング制御信号S2の様な信
号の場合、情報トラツクのひずみを示す周期性の
信号成分の他に、装置の振動等により発生する非
周期性の信号成分も含まれる。この非周期性信号
成分の記憶は偏心補償を行うとき有害であり、こ
の非周期成分の記憶を防止すべく第2の波形記憶
手段により、複数回記憶を行い、この結果を平均
化して第1の波形記憶手段の記憶結果と混合し、
偏心補償に用いても良い。
Further, although the signal S 2 is a periodic signal, for example, in the case of a signal such as the tracking control signal S 2 shown in FIG. 1, in addition to the periodic signal component indicating the distortion of the information track, It also includes non-periodic signal components caused by vibrations and the like. Storing this non-periodic signal component is harmful when performing eccentricity compensation, so in order to prevent this non-periodic component from being stored, the second waveform storage means stores it multiple times, averages the results, and then mixed with the storage result of the waveform storage means,
It may also be used for eccentricity compensation.

また、第2図、第4図において、RAM23,
29およびRAM35,40は同一の集積回路内
の異なるアドレスのものを用いても良い。例えば
1024ポイントの記憶を行うとき2048番地の容量を
有するRAMを使用し、0〜1023番地にはRAM3
5に入るべき情報を記憶し、1024〜2047番地に
RAM40に入るべき情報を記憶しても良い。
In addition, in FIGS. 2 and 4, the RAM 23,
29 and RAMs 35 and 40 may be located at different addresses within the same integrated circuit. for example
When storing 1024 points, RAM with a capacity of 2048 addresses is used, and RAM 3 is used for addresses 0 to 1023.
Memorize the information that should be entered in 5 and enter addresses 1024-2047.
Information to be stored in the RAM 40 may be stored.

更に本発明の適用範囲としては、第2図、第4
図の様なアナログ―デイジタル変換を行つて得ら
れたデイジタル情報を半導体メモリに記憶し、こ
れをデイジタル―アナログ変換して、アナログ情
報として読み出しを行う波形記憶装置のみなら
ず、電荷転送素子の様なアナログメモリを用いた
波形記憶装置にも適用できる。そして、波形記憶
手段の数は少なくとも2個必要であり、2個以上
有するものについても本発明の基本思想である誤
差補正を行うものであれば、本発明の適用範囲に
入る。
Furthermore, the scope of application of the present invention is as follows:
As shown in the figure, digital information obtained by performing analog-to-digital conversion is stored in a semiconductor memory, and this is converted to digital-to-analog and read out as analog information.It is not only a waveform storage device, but also a charge transfer device. It can also be applied to waveform storage devices using analog memories. At least two waveform storage means are required, and devices having two or more waveform storage means fall within the scope of the present invention as long as they perform error correction, which is the basic concept of the present invention.

また、第4図に記したRAM40はレジスタで
も代用でき、信号S8をADC34でデイジタル変
換する毎にレジスタに蓄え、これを同時に加算器
41に加え、信号S10との加算結果をRAM35に
加えてもよい。
In addition, the RAM 40 shown in FIG. 4 can be replaced with a register, and each time the signal S 8 is digitally converted by the ADC 34, it is stored in the register, added to the adder 41 at the same time, and the result of addition with the signal S 10 is added to the RAM 35. It's okay.

第2図、第4図の第‘および第2の波形記憶手
段の有するサンプルプイント数(被記憶信号の1
周期中において、信号をサンプリングして記憶す
るサンプル数)が異つてもよい。更に第4図に示
したADC,DACを共用した波形記憶装置におい
て、第1の波形記憶手段の有するRAMと第2の
記憶手段の有するRAMの記憶結果を加算すると
き、その加算結果を別の第3のRAMに記憶し、
この第3のRAMの記憶結果をDACによりアナロ
グ信号に変換して誤差補正を行つた波形記憶信号
を得てもよい。この場合、独立した3つのRAM
を用いなくとも、前記3つのRAMの記憶容量の
和と等しいもしくはより大きな記憶容量を有する
1つのRAMによりこれらの記憶動作を行わせて
もよい。
2 and 4, and the number of samples possessed by the second waveform storage means (1
The number of samples for sampling and storing a signal may vary during the period. Furthermore, in the waveform storage device that shares the ADC and DAC shown in FIG. Stored in the third RAM,
The storage result of this third RAM may be converted into an analog signal by a DAC to obtain an error-corrected waveform storage signal. In this case, three independent RAM
These storage operations may be performed by one RAM having a storage capacity equal to or larger than the sum of the storage capacities of the three RAMs.

また、第1の波形記憶手段15、第2の波形記
憶手段16はそれぞれの有する波形記憶精度が最
良となるよう設定もしくは設計することが望まし
い。例えば第2図、第4図の実施例において、入
出力の信号処理用に使用する低域通過フイルタに
よる位相遅れに起因した位相誤差能は、RAMの
アドレス書き込み時よりも読み出し時においてよ
り進んだタイミングに設定すれば、位相誤差を軽
減でき、精度向上を計れる。このRAMのアドレ
ス書き込み時よりも読み出し時において進ませる
時間(RAMのR/Wのアドレスのタイミング)
は、入出力の信号処理に使用する低域通過フイル
タの位相特性に対応して定めねばならず、第1お
よび第2の波形記憶手段において、入出力の信号
処理用の低域通過フイルタに特性が異なる場合、
前記RAMのR/Wのアドレスのタイミングも
各々のフイルタの督性に合せて別々の値に設定す
る必要がある。
Further, it is desirable that the first waveform storage means 15 and the second waveform storage means 16 are set or designed so that the waveform storage accuracy of each of them is maximized. For example, in the embodiments shown in FIGS. 2 and 4, the phase error caused by the phase delay caused by the low-pass filter used for input/output signal processing is more advanced when reading RAM addresses than when writing them. By setting the timing, phase errors can be reduced and accuracy can be improved. The time to advance when reading this RAM address than when writing it (RAM R/W address timing)
must be determined in accordance with the phase characteristics of the low-pass filter used for input/output signal processing, and in the first and second waveform storage means, the characteristics of the low-pass filter for input/output signal processing must be determined. If they are different,
The timing of the R/W address of the RAM must also be set to different values depending on the performance of each filter.

尚、本発明のデイジタル信号処理動作をマイク
ロコンピユータと呼ばれる電子計算機システムに
より合わせてもよい。
Note that the digital signal processing operation of the present invention may be combined with an electronic computer system called a microcomputer.

また、本発明は1個のADCもしくは複数の
ADCを備え、複数の入力信号の波形記憶を行う
波形記憶装置にも適用可能である。
Additionally, the present invention provides a method for using one ADC or multiple ADCs.
It is also applicable to a waveform storage device that includes an ADC and stores waveforms of multiple input signals.

そして、本発明は偏心補償用の波形記憶装置以
外にも被記憶信号が既知の周期性を有するもので
あれば適用可能であり、偏心補償に用いる場合も
第1図の光学的デイスク以外の磁気的あるいは静
電容量的記録再生を行う記録あるいは再生媒体を
有する装置、デイスク以外のテープ、シート、ド
ラム状等の形状を有する記録もしくは再生媒体を
有する装置、同心円以外の記録軌跡をもつて情報
トラツクの記録が行われる装置、情報トラツクに
記録される情報あるいは記録時における記録情報
の種類、トラツキング制御手段等に関係なく適用
し得る。
The present invention can be applied to devices other than waveform storage devices for eccentricity compensation as long as the signals to be stored have known periodicity, and when used for eccentricity compensation, magnetic disks other than the optical disk shown in FIG. A device having a recording or reproducing medium that performs physical or capacitive recording and reproducing, a device having a recording or reproducing medium in the shape of a tape, sheet, drum, etc. other than a disk, and an information track with a recording trajectory other than concentric circles. The present invention can be applied regardless of the device in which recording is performed, the type of information recorded on the information track or the recorded information at the time of recording, the tracking control means, etc.

以上本発明によれば、安価な回路素子(高精度
を必要としない回路素子)を用い、かつ簡単な調
整で精度の高い波形記憶装置を提供できるもので
ある。
As described above, according to the present invention, it is possible to provide a highly accurate waveform storage device using inexpensive circuit elements (circuit elements that do not require high accuracy) and with simple adjustment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は記録媒体の偏心補償を行う波形記憶装
置の一例を示すブロツク図、第2図は本発明の一
実施例を示すブロツク図、第3図はその動作タイ
ミングを示すタイミング図、第4図は本発明の別
の実施例を示すブロツク図である。 8……記録媒体、12……トラツキング制御回
路、13……波形記憶装置、14……回転鏡駆動
回路、15,16……第1および第2の波形記憶
手段、17,39……差動増幅器、18……混合
増幅器、20,26,32……低域通過フイル
タ、21,27,33……サンプルホールド回
路、22,28,34……ADC、23,29,
35……RAM、24,30,36……DAC、2
5,31,37……低域通過フイルタ、40……
RAM、41……加算器。
FIG. 1 is a block diagram showing an example of a waveform storage device that compensates for eccentricity of a recording medium, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a timing diagram showing its operation timing, and FIG. The figure is a block diagram showing another embodiment of the invention. 8... Recording medium, 12... Tracking control circuit, 13... Waveform storage device, 14... Rotating mirror drive circuit, 15, 16... First and second waveform storage means, 17, 39... Differential Amplifier, 18... Mixing amplifier, 20, 26, 32... Low pass filter, 21, 27, 33... Sample hold circuit, 22, 28, 34... ADC, 23, 29,
35...RAM, 24, 30, 36...DAC, 2
5, 31, 37...Low pass filter, 40...
RAM, 41...Adder.

Claims (1)

【特許請求の範囲】 1 既知の周期を有する第1の信号を記憶し、読
み出し信号である第2の信号を得る第1の記憶手
段と、前記第1の信号と前記第2の信号の差に対
応した第3の信号を得る誤差検出手段と、該第3
の信号を記憶し、読み出し信号である第4の信号
を得る第2の記憶手段と、該第4の信号と前記第
2の信号を混合して題5の信号を得る混合手段と
を具備し、該第5の信号を波形記憶信号として用
いることを特徴とする信号波形記憶装置。 2 第3の信号を第1の信号の既知周期毎に平均
化して記憶する第2の記憶手段を具備したことを
特徴とする特許請求の範囲第1項記載の信号波形
記憶装置。 3 第1の記憶手段で第1の信号を記憶する記憶
利得より、第2の記憶手段で第3の信号を記憶す
る記憶利得をα倍(αは1以上)高めて記憶する
とともに混合手段において第1の信号に対する第
4の信号の混合比を1/αとしたことを特徴とする
特許請求の範囲第1項または第2項記載の信号波
形記憶装置。 4 αを2n(nは1以上の整数)としたことを
特徴とする特許請求の範囲第3項記載の信号波形
記憶装置。
[Claims] 1. A first storage means that stores a first signal having a known period and obtains a second signal that is a read signal, and a difference between the first signal and the second signal. error detection means for obtaining a third signal corresponding to the third signal;
and a mixing means for mixing the fourth signal and the second signal to obtain the signal of Problem 5. , a signal waveform storage device characterized in that the fifth signal is used as a waveform storage signal. 2. The signal waveform storage device according to claim 1, further comprising second storage means for averaging and storing the third signal for each known period of the first signal. 3. The storage gain for storing the third signal in the second storage means is increased by α times (α is 1 or more) than the storage gain for storing the first signal in the first storage means, and the storage gain is increased by α times (α is 1 or more), and the storage gain is increased in the mixing means. 3. The signal waveform storage device according to claim 1, wherein the mixing ratio of the fourth signal to the first signal is 1/α. 4. The signal waveform storage device according to claim 3, wherein α is 2 n (n is an integer of 1 or more).
JP17255979A 1979-12-28 1979-12-28 Signal waveform storage device Granted JPS5696303A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17255979A JPS5696303A (en) 1979-12-28 1979-12-28 Signal waveform storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17255979A JPS5696303A (en) 1979-12-28 1979-12-28 Signal waveform storage device

Publications (2)

Publication Number Publication Date
JPS5696303A JPS5696303A (en) 1981-08-04
JPS6152482B2 true JPS6152482B2 (en) 1986-11-13

Family

ID=15944092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17255979A Granted JPS5696303A (en) 1979-12-28 1979-12-28 Signal waveform storage device

Country Status (1)

Country Link
JP (1) JPS5696303A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4629393A (en) * 1984-05-21 1986-12-16 Hitachi, Ltd. Method of operating multistage hydraulic machinery
US7055752B2 (en) * 2000-05-22 2006-06-06 Matsushita Electric Industrial Co., Ltd. IC card

Also Published As

Publication number Publication date
JPS5696303A (en) 1981-08-04

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