JPS6152476B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a data selection device that selects one or more bits of data at a desired position from a plurality of bits of digital data. A circuit for selecting the lowest or highest single data having a signal "1" (active level) in multiple bits of parallel digital data is already known as a priority selection circuit. However, since the conventional priority selection circuit can only select the lowest or highest signal "1",
Its uses are limited. An object of the present invention is to provide a data selection device capable of selecting data at an arbitrary position (for example, an intermediate position) where the signal is "1" among a plurality of bits of digital data. Each bit position of the digital data of multiple bits is ordered according to the positional relationship. For example, the leftmost bit position is the lowest bit position, and the rightmost bit position is the highest bit position. According to this invention, at least two priority selection circuits or selection circuits are used in combination, and one priority selection circuit or selection circuit selects data from a certain bit position above (or below) among a plurality of bits of selected data. block all data (we call this "masking") and select other data. Another priority selection circuit or selection circuit blocks (masks) all data in the opposite direction (downward or upward) from a certain bit position of the data selected above, and masks the remaining data. Select. In this way, data at intermediate bit positions is selected by masking a plurality of bits of selected data in opposite directions by at least two priority selection circuits or selection circuits. Of course, it is also possible to select the highest or lowest data by shifting the mask position. Further, by using a combination of three or more priority selection circuits or selection circuits as described above, it is also possible to select data at one or more discrete bit positions. Further, according to the present invention, the first selection circuit blocks (masks) all data above (or below) a certain bit position among the data to be selected, and selects other data. Next, a priority circuit that selects the lowest or highest single data "1" of the signal selects the lowest (or highest) single data "1" among the selected data. In this way, a single data "1" at the intermediate bit position can be selected by the mask type selection circuit and the single priority circuit. Hereinafter, one embodiment of the present invention will be described in detail based on the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of a data selection device according to the present invention, in which two selection circuits 22 and 23 are connected in series. First selection circuit 2
Reference numeral 2 denotes a mask type selection circuit which blocks (masks) all data at bit positions above or below the bit position specified by externally supplied mask position information MS, and selects other data. When the signal on the upper selection control line 22H is "1", data below the bit position of the mask position information MS is masked and data above is selected.
When the signal on the lower selection control line 22L is "1", data above the bit position of the information MS is masked and data below is selected, contrary to the above. The direction of the leftmost bit K1 of _the selected data _K1 to _K8 (for example, 8 bits) input in parallel to the first selection circuit 22 is assumed to be downward, and the direction of the rightmost bit _K8 is assumed to be upward. do. Selected data K ₁ to _{K 8}
is in the state shown in _FIG . In the selection circuit 22, the second
Data is selected as shown in Figure b. The shaded areas indicate blocked or masked data portions. The second selection circuit 23 is a priority selection circuit that selects the single data whose signal is "1" by giving top priority or bottom priority, and the first selection circuit 23
The data selected in step 2 is input, and the input data is selected in the opposite direction to the first selection circuit 22. For example, the upper priority control line 23H is
The signal becomes "1" in accordance with the lower selection control line 22L of the selection circuit 22, and the second selection circuit 23 is placed in the uppermost data preferential selection state. Further, the lower priority control line 23L becomes a signal "1" in agreement with the upper selection control line 22H of the first selection circuit 22, and the second selection circuit 23 is placed in the lowermost data priority selection state. FIG. 2c shows a state in which the second selection circuit 23 performs the lowest priority selection operation and selects the lowest data whose signal is "1" among the data shown in FIG. 2b. The shaded area in FIG. 2c shows that all data above the single data "1" selected by the lowest priority selection is blocked (masked). In this way, among the selected data output lines _KS1 to _KS8 , a signal "1" is generated only on the line _KS5 corresponding to the input selected data _K5 , as shown in FIG. 2d. Therefore, the data at the intermediate position
This means that K ₅ has been selected. In the example of FIG. 1, the first and second selection circuits 2
Both of 2 and 23 can be controlled to switch the selection direction, but they may be fixed. Further, both the first and second selection circuits 22 and 23 may be mask type selection circuits. In this case, the contents of the mask position information given to both selection circuits are different. For example, if the first selection circuit masks the lower part from data _K3 and the second selection circuit masks the upper part from data _K6 , data _K5 at the intermediate position is selected as shown in FIG. 2e. I can do it. Note that the detailed configurations of the first selection circuit 22 and the second selection circuit 23 in FIG. 1 can be similar to the first priority circuit 44 and second priority circuit 45 described later. FIG. 3 shows an example in which the data selection device according to the present invention is applied to selection processing of pitch name data in an electronic musical instrument, in which the data selection device according to the present invention is incorporated inside the pitch name information processing device 11. ing. The internal configuration of this pitch name information processing device 11 is as follows.
As shown in the figure. First, the outline of FIG. 3 will be explained. In the automatic performance section 10, a single note name information processing device 11 is used in a time-sharing manner for two automatic performance functions, namely automatic bass chord performance and automatic arpeggio performance. Although the processing content in the note name information processing device 11 is different for automatic bass chord performance and automatic arpeggio performance, the circuit inside the processing device 11 is configured so that it can be used for either, and the control Processing is performed according to the content of the control information supplied via lines 14 and 15.
The automatic bass chord control device 12 sends control information to the control line 14 that makes the processing content in the note name information processing device 11 for automatic bass chord performance.
Supply via. Automatic arpeggio control device 13
supplies, via the control line 15, control information for controlling the processing content of the note name information processing device 11 for automatic arpeggio performance. Automatic bass chord control device 12 and automatic arpeggio control device 13
Time-division operation control signals T and T' are transmitted and received between the two. When the signal T is applied from the device 13 to the device 12, the automatic base code control device 12 is activated;
When the automatic arpeggio control device 13 is given to the device 13 from the above, the automatic arpeggio control device 13 becomes ready for operation. Devices 12 and 13
are designed so that they are not activated at the same time, so control information for automatic bass chords and control information for automatic arpeggio are given in a time-sharing manner via control lines 14 and 15, and note name information The processing device 11 is shared in time division between the two automatic performance functions. The pitch name information processing device 11 appropriately processes one or more pitch name information given for specifying a chord (chord) or root note, and generates pitch name information for automatic bass, automatic chord, or automatic arpeggio. , root note information, chord information, etc. In this embodiment, pitch name information is provided to the pitch name information processing device 11 by pressing keys on the lower keyboard or the pedal keyboard. In the automatic bass chord performance to be performed with this embodiment device, it is possible to select one of the following functions: ``finger chord function'', ``single finger function'', or ``custom function''. . These functions will not be particularly explained. Automatic bass chord function selector 16
is for selecting one of the above three functions, and depending on the player's selection, a finger chord function selection signal FC, a single finger function selection signal SF, or a custom function selection signal is sent.
CUS is generated. In addition, when none of the above three functions is selected, that is, when automatic bass chord performance is not selected, the normal signal NOM
is generated. These signals FC, SF, CUS, and NOM generated in response to selection operations in the automatic bass chord function selector 16 are used in the automatic performance section 10 or other circuits. The pitch of the bass note to be generated in automatic bass chord performance and its timing are determined by the bass pattern information BP generated from the automatic bass chord pattern generating section 17. The automatic bass chord pattern generation section 17 generates bass pattern information BP and chord sound generation timing signal CG using a sound generation timing pattern and pitch pattern corresponding to the rhythm selected by the rhythm selector 18. The bass pattern information BP has contents representing a certain pitch (for example, 1st, 3rd, 5th, 7th, etc.) at the timing at which the bass note is to be produced. Further, the chord tone generation timing signal CG becomes a signal "1" at the timing when the chord tone is to be generated. Base pattern information BP
A basic tempo clock pulse TEMPO is supplied from a tempo clock generator 19 for setting a basic tempo for generating a chord tone generation timing signal CG and an arpeggio tone generation timing signal APL to be described later. Automatic arpeggio performance involves sequentially producing one or more notes (note names) pressed on the lower keyboard, one note at a time interval, in a predetermined order, and repeating this sequential pronunciation over one to several octaves. This is a function that can be repeated repeatedly. In this embodiment, in addition to the general automatic arpeggio described above, a function called "chord arpeggio" can be selected. The "chord arpeggio function" means that you can press a single key corresponding to the root note on the lower keyboard.
A function that automatically creates notes that have a predetermined interval relationship to this root note (hereinafter referred to as subordinate notes), and performs automatic arpeggio performance by sequentially producing the root note and subordinate note one by one. It is. When automatic arpeggio performance is selected by operating the arpeggio selector 20, the automatic arpeggio selection signal is
ARP becomes "1", and the automatic arpeggio section 10 performs control and processing operations for automatic arpeggio performance. "Chord arpeggio function"
If an automatic arpeggio is selected at the arpeggio selector 20 while the "single finger function" is selected at the automatic bass chord function selector 16, the automatic arpeggio is selected instead of the normal automatic arpeggio performance. automatic arpeggio 1
An arpeggio sound generation timing signal APL representing the timing at which each note is generated is generated from the arpeggio sound generation timing control section 21. For example, the arpeggio sound timing control section 21 divides the basic tempo clock pulse TEMPO as appropriate to generate the arpeggio sound timing signal APL. The lower keyboard has keys spanning multiple octaves, but the lower keyboard circuit 31 commonly connects the key switches with the same note name in each octave to the line 34-1.
34-12, key depression information corresponding to the 12 note names C to B is output. The pedal keyboard has, for example, 13 keys of one octave and one note from _C1 to _C2 , and the pedal keyboard circuit 32 outputs key press information for each key. Figure 1 shows the pedal keyboard.
The outputs of the pedal keyboard circuit 32 corresponding to the 12 keys of _C1 to _B1 are labeled C to B, and the output of the key of _C2 , one octave above, is labeled C. The outputs of the 12 notes C to B of the pedal keyboard circuit 32 are supplied to lines 33-1 to 33-12, respectively. Further, the C note on the treble side of the B note, that is, the output of C' of the pedal keyboard circuit 32 is given to the line 33-13. Lines 33-1 to 33-13 and 34
The pitch name information given to -1 to 34-12 is input to the pitch name information processing device 11 as information representing the pitch name of the pressed key on the pedal keyboard or the lower keyboard. In Figure 4, lines 33-1 to 33-1
Note names of the pedal keyboard supplied via 3. C to B, C
Key press data and lines 34-1 to 34-12
The key depression data of the note names C to B on the lower keyboard are inputted to the data selector 47, respectively. The data of the line corresponding to the note name being pressed is “1”
, and the data of the line corresponding to the note whose key has been released is "0". In addition, all the signals on lines 33-1 to 33-13 are input to an OR circuit 39, and the output of the OR circuit 39 becomes a signal "1" when any key is pressed, which is a pedal keyboard key press detection signal. Used as PKM. Similarly,
Lower keyboard key press detection signal LKM is sent from the OR circuit 40 based on the data on lines 34-1 to 34-12.
is output. Various circuits inside the pitch name information processing device 11, especially the first priority circuit 44 and the second priority circuit 4
5. The data register 46 and the like are designed to perform multi-functional operations, and can switch their operating functions according to the content of control information given from others. When the pedal keyboard selection control line 47P of the data selector 47 is signal "1", the data of the pedal keyboard tone names C to B and C' on the lines 33-1 to 33-13 are selected by the data selector 47 and output to the output line N. ₁ to N ₁₂ and N ₁₃ . Line 34-
The data of the lower keyboard note names C to B of 1 to 34-12 are selected by the data selector 47 when the lower keyboard selection control line 47L of the data selector 47 is the signal "1".
is selected and led out to output lines _N1 to _N12 . The data selector 47 sends any one of three types of input data to the control lines 47L, 47P, 47.
The data register 46 is selected as the remaining input data.
The output is now added. When the selection control line 47D is a signal "1", data to be stored in the data register 46 is selected and led to output lines _N1 to _N12 . The data on the output lines N ₁ to _{N 12} of the data selector 47 is input to the first priority circuit 44 as data to be selected by the first priority circuit 44 . The first priority circuit 44 can appropriately select the 12 pieces of selected data N ₁ to _{N 12} with upper priority or lower priority, and when the upper priority control line 44H is the signal "1", the upper priority is selected. and the lower priority control line 44
When L is a signal "1", priority is given to the lower side. still,
The ordering of the selected data N ₁ to _{N 12} in the priority circuit 44 is such that N ₁ is the lowest order and N ₁₂ is the highest order.
In the case of upward priority, priority is given in the order of N ₁₂ , N ₁₁ , N ₁₀ ...N ₂ , N ₁ , and in the case of downward priority, N ₁ , N ₂ , N ₃ ...N ₁₁ ,
Priority shall be given in the order of N ₁₂ . C, C#…A
Each pitch name data of # and B is N ₁ , N ₂ ...N ₁₁ , N ₁₂ respectively
Since the selected data is , upper priority means giving priority to treble sounds, and lower priority means giving priority to bass sounds.
In addition, the first priority circuit 44 can switch the priority position based on priority information, and the priority information to be used is three types of information.
One of _N2 to _N13 , _A1 to _A12 , or _T1 to _T12 is selected and used by the priority information select gate 48. The priority information is information indicating which position of the selected data N ₁ to _{N 12} should be preferentially selected. Therefore, the first
By changing the contents of the priority information used in the priority circuit 44 and the priority direction (upward or downward), the contents of the preferential selection operation in the first priority circuit 44 are varied. Priority information N ₂ to _{N 13} are signals of data lines N ₂ to _{N 13} output from the data selector 47, and when the signal of the priority information selection control line 49N is “1”, the select gate 48 selects the first It is used in the priority circuit 44. Priority information _A1 to _A12 is data supplied from an arpeggio register 60, which will be described later, and is selected by the select gate 48 and used by the first priority circuit 44 when the signal on the priority information selection control line 49A is "1". Ru. Priority information T ₁ ~ T ₁₂
is the counter 12 in the automatic arpeggio control device 13
4 (FIG. 3), and is selected by the select gate 48 and used by the first priority circuit 44 when the selection control line 49T is "1". An example of the first priority circuit 44 is shown in FIG. Fifth
In the figure, data among selected data N ₁ to N ₁₃
Although the illustration of the circuit related to N ₄ to _{N 10} is omitted,
The circuit is constructed according to the illustrated circuit. Two AND circuits 50 for each selected data N ₁ to _{N 12}
-1 to 50-12 and 51-1 to 51-12
is provided, and the selected data is input to one input terminal.
_N1 to _N12 are each input. Each selected data N ₁ ~
12 OR circuits 52-1 to 52 corresponding to N ₁₂
-12, the outputs of the OR circuits 52-12 corresponding to the uppermost data (N ₁₂ ) are sequentially input to the lower OR circuits. Upper priority control line 4
The 4H signal is inverted by an inverter 53 and input to the uppermost OR circuit 52-12. In addition, 12 OR circuits 5 corresponding to each selected data N ₁ to _{N 12}
4-1 to 54-12, the outputs of the OR circuits 54-1 corresponding to the lowest data (N ₁ ) are sequentially input to the upper OR circuits. The signal on the lower priority control line 44L is sent to the inverter 55.
is inverted and input to the lowest OR circuit 54-1. The output of each OR circuit 52-1 to 52-12 is connected to an AND circuit 50-1 to 50-5 via an inverter.
0-12, and each OR circuit 54-1 to 54
The output of -12 is sent to AND circuit 5 via an inverter.
Joins 1-1 to 51-12. In addition, each OR circuit 52-1 to 52-12 and 54-1 to 54
-12, the priority information selected by the priority information selection gate 48 is input. Priority information _N2 to _N13 or _A1 selected by the signal on the priority information selection control line 49N, 49A, or 49T
Each bit of ~ _A12 or _T1 ~ _T12 corresponds to the position of the selected data _N1 ~ _N12 , respectively, and is connected to each of the OR circuits 52-1 through 56-12 via the OR circuits 56-1 through 56-12. 52-12, 54-1 to 54-1
2 respectively. In the case of upper priority, the signal on line 44H is "1" and the signal on line 44L is "0". Therefore, the outputs of the OR circuits 54-1 to 54-12 are all "1".
Then, the AND circuit 51-1 is connected via the inverter.
A signal "0" is applied to the signals 51-12. Therefore,
The AND circuits 50-1 to 50-12 are more operable. If the data at a certain position is "1" among the 12 pieces of priority information data given from the priority information select gate 48 via the OR circuits 56-1 to 56-12, the The outputs of the lower OR circuits (some of 52-1 to 52-12) all become "1". As a result, all the AND circuits (some of 50-1 to 50-12) below the priority position represented by the priority information become inoperable, and the data above (some of N ₁ to N ₁₂ ) ) is selected. In the case of downward priority, the signal on line 44H is "0" and the signal on line 44L is "1". Therefore, contrary to the above, the OR circuits 52-1 to 52-
All outputs of 12 become "1", and AND circuit 5
0-1 to 50-12 are all inactive. If the data at a certain position among the 12 pieces of priority information given through the OR circuits 56-1 to 56-12 is "1", the OR circuits above that position, including that position, (54-1 to 54
-12) all outputs are "1". As a result, the AND circuits (51-1 to 51-12) located above the priority position indicated by the priority information
) are all inactive, and data below that (some of N ₁ to N ₁₂ ) is selected. Note that the data is controlled by the signal on the control line 49N.
When N ₂ to _{N 13} are selected as priority information for selected data N ₁ to _{N 12} , the upper priority control line 44H becomes "1" and control is performed so that upper priority selection is performed. In this case, the first priority circuit 44 operates as an uppermost priority selection circuit that selects the uppermost single data among the data of the signal "1". Moreover, when data A ₁ to _{A 12} or T ₁ to _{T 12} are used as priority information, the first priority circuit 44
operates as a mask type selection circuit. In this case, the priority information acts as the mask position information described above. The data selected in the first priority circuit 44 is output via OR circuits 57-1 to 57-12. Selected data in the first priority circuit 44
_N1 ~ _N12 and priority information _N2 ~ _N13 , _A1 ~ _A12 , _T1 ~ _T12
The positional relationship is shown in Table 1.

[Table] In Table 1, for example, selection contents when data T ₆ of priority information T ₁ to _{T 12} is “1” are shown for downward priority and upward priority cases. In the case of downward priority, data N ₁ to _{N 5} below data N ₆ corresponding to the position of priority data T ₆ of “1” are selected. In the case of upper priority, data N ₇ to _{N 12} above data N ₆ corresponding to data T ₆ are selected.
Also, for example, when only the data _N3 and _N6 of the selected data _N1 to _N12 are "1" and the others are "0", the priority information _N2 to _N13 is used to prioritize stopping. In this case, the priority data N ₆ blocks the data from N ₁ to _{N 5 below the input selected data N 5 ,} and the selected data N ₆
Since ~ _N12 is selected, the uppermost data _N6 will be selected with priority. When canceling the priority selection function in the priority circuit 44, both the priority control lines 44H and 44L are set to "1", and the priority information selection control line 49 is set to "1".
Set N, 49A, and 49T to all “0”. In this way, the input data N ₁ to _{N 12} are directly transmitted to the AND circuits 50-1 to 51-12 and the OR circuit 5.
7-1 to 57-12. Also,
When blocking the data N ₁ to _{N 12} from passing through the priority circuit 44, both the control lines 44H and 44L are set to "0" and the AND circuits 50-1 to 51-
12 is made inoperable. The 12 data output from the first priority circuit 44 via the OR circuits 57-1 to 57-12 (FIG. 5) pass through the OR selection group 58 (FIG. 4) to the data lines _M1 to M. ₁₂ respectively. The OR circuit group 58 is provided for supplying to the follower sound data lines _M1 to _M12 generated from the code arpeggio follower data creation logic 59 in the case of the "chord arpeggio function". Output of the first priority circuit 44 and follower tone data creation logic 5 for chord arpeggio
The outputs of 9 are not applied to the OR circuit group 58 at the same time, and either one of the data groups is connected to the data line.
It is designed to be guided by M ₁ to M ₁₂ . The signals on data lines M ₁ -M ₁₂ are applied to the data inputs of the data register 46 and to the selected data inputs of the second priority circuit 45 . The data register 46 is a parallel input/parallel output type serially shiftable register having 12 storage locations D ₁ to D ₁₂ , and the shift direction control, data circulation control, etc. are performed according to control information. The shift clock pulse φ is, for example, a high-speed clock pulse with a period of about 1 μs. When the signal on the load control line 61 becomes "1", the signals on the data lines M ₁ -M ₁₂ are read into the respective storage locations D ₁ -D ₁₂ of the data register 46, respectively. At this time, the signal on the hold line 62 is also "1" and becomes "0" via the inverter, so that holding is prohibited. hold line 6
When the signal 2 is "0" (it is "0" unless a signal "1" is particularly given), the signal "1" is applied to the data register 46 via the inverter,
Data in each storage location _D1 - _D12 is held. When the signal on left shift control line 63 becomes "1", the contents of each storage location D ₁ -D ₁₂ of data register 46 are shifted to the left in accordance with clock pulse φ. Shifting to the left means shifting from storage position _D12 toward _D1 . Leftmost memory location
The output data of D ₁ (corresponding to input data M ₁ ) is input to the rightmost storage location D ₁₂ via the AND circuit 65 during left shift. AND circuit 6
5, the signal on the left shift circulation control line 66 is “1”
It becomes operational when , and the data register 46 becomes a circular shift register during left shift. When the signal on the right shift control line 64 goes to "1", the data register 46 is shifted right from storage location _D1 to _D12 . When shifting to the right, memory position D ₁₂
The output data of is sent to the storage location via circulation line 67.
_D1 , and the data register 46 always functions as a circular shift register. The data held in each storage location D ₁ to _{D 12} of the data register 46 is outputted in parallel, and is input to the code detection logic 68 as well as to the data selector 47. The chord detection logic 68 is for detecting a chord (chord) formed by one or more keys pressed on the lower keyboard. In the chord detection logic 68, chord detection is performed on the assumption that the data in the respective storage locations _D1 to _D12 of the data register 46 are in a semitone relationship. The pitch at the leftmost storage position _D1 is set to 1 degree, and the pitch increases by a semitone from _D2 to _D12 . Table 2 shows the correspondence between each storage location D ₁ to D ₁₂ of the data register 46 and the pitch.

[Table] Numbers 1, 2b, 2 written in the pitch column of Table 2
...7d, 7 is 1st, minor 2nd, major 2nd, ...minor 7th
They represent the intervals of degrees and major sevenths, respectively. The lower column of Table 2 shows conditions for detecting major chords, seventh chords, minor chords, and first-degree intervals in the chord detection logic 68. The mark ◯ indicates that there is a note of the corresponding pitch, that is, the data in the corresponding storage positions D ₁ to D ₁₂ is “1”. The x mark indicates that there is no sound of the corresponding pitch, that is, the data of the corresponding storage positions _D1 to _D12 is "0". Therefore, the code detection logic 6
8 is provided with an AND circuit that detects major, seventh, minor, and one degree intervals according to the following logical formula. Detection of major code 1, 2, 4, 5, 6
=D ₁・₃・₆・D ₈・₁₀ ……(1) Seventh chord detection 1・2・4・6・7 ^b
=D ₁・₃・₆・₁₀・D ₁₁ ...(2) Minor chord detection 3 ^b =D ₄ ...(3) Detection of 1st interval 1=D ₁ ...(4) Equation (1) above In equation (4), the number on the left side indicates the pitch, and the bar above the number indicates that the pitch does not exist. The code on the right side indicates the storage location of the data register 46, a bar above the code indicates that the data at that storage location is "0", and a symbol without a bar indicates that the data is "1". show. When the signal on the code detection control line 68C applied to the code detection logic 68 is "1", the code detection logic 68 uses an AND circuit (not shown) that checks the logic of equations (1) to (3) above. Enable operation and detect the presence or absence of major, seventh, or minor chords. When the signal on the single finger root note detection control line 68R is "1", the chord detection logic 68 enables an AND circuit (not shown) that checks the logic of equation (4),
Detect the data that should be the root note of the single finger function. Lines 68C and 68R are simultaneously
A signal is given so that it does not become "1". Also, the signal on the lowest sound detection control line 68L is “1”.
When this happens, the AND circuit based on the logic of equation (4) becomes operational and detects the data of the lowest note, that is, the interval of 1 degree. The output related to the above logical formula (1) is given to the major code detection line Mj, the output related to the logical formula (2) is given to the seventh chord detection line 7th, and the output related to the logical formula (3) is given to the minor code detection line min
given to. Further, the output related to logical formula (4) is given to the one-note detection line st. 1 sound detection line st,
The signals on the major chord detection line Mj and the seventh chord detection line 7th are applied to an OR circuit 69, and become a chord detection signal CH indicating that some chord (chord) has been detected. Further, the signals on the minor chord detection line min and the seventh chord detection line 7th are used as signals indicating the presence or absence of the minor chord and the seventh chord. That is, the signal "1" on the seventh chord detection line 7th is stored in the seventh code memory 71 via the OR circuit 70, and generates the seventh signal _CH7 indicating that the chord type is the seventh.
Also, the signal of the minor code detection line min is “1”
passes through the OR circuit 72 to the minor code memory 73
and generates a minor signal CHm indicating that the code type is minor. When the signal on the load control line 74 becomes "1", the seventh code memory 71 and the minor code memory 73
Control is such that the signals from the OR circuits 70 and 72 are read into the OR circuits 70 and 72. By the way, the code detection logic 68 can detect the logic of equations (1) to (3) above only in the case of the finger code function and custom function, but not in the case of the single finger function. . In the case of the single finger function, the chord type is specified by pressing a white or black key on the pedal keyboard, so each note name C to B, C' is stored in the pedal keyboard note name memory register 35. The output is applied to the single finger minor and seventh detection logic 75. The minor and seventh detection logic 75 corresponds to the white key C,
An OR circuit that inputs the note name data of D, E, F, G, A, B, C', and C#, D#, corresponding to the black key.
The output of the former OR circuit is supplied to the seventh detection line 75s, and the output of the latter OR circuit is supplied to the minor detection line 75m. It's becoming like that. The signals of the seventh detection line 75s and the minor detection line 75m are connected to AND circuits 76 and 77.
will be added to each. When the AND circuits 76 and 77 are enabled to operate by the signal on the control line 78 which becomes "1" when the single finger function is selected, the signals on the lines 75s and 75m become the seventh detection signal SF.
7 and is output as a minor detection signal SFm.
The signals _SF7 and SFm are connected to the OR circuits 70 and 7.
2 is stored in the seventh code memory 71 and the minor code memory 73. The second priority circuit 45 inputs the data of the data lines M ₁ to _{M 12} and also inputs the highest tone of the pedal keyboard.
Input the data of data line _N13 corresponding to C'. The order of the selected data M ₁ to _{M 12} and N ₁₃ is as follows: M ₁ is placed at the bottom (lowest note), M ₂ to M ₁₂ are placed sequentially upward (treble), and N ₁₃ is placed at the top (highest note). do. The reason why the data on the data line _N13 is not used in the path from the first priority circuit 44 to the chord detection logic 68 is that the processing in this path is unrelated to the pedal keyboard. In the second priority circuit 45, when the signal on the upper priority control line 45H is "1", the input data M ₁
Control is performed to select the uppermost "1" data among M ₁₂ and N ₁₃ . In addition, when the signal on the lower priority control line 45L is "1", the input data
Control is performed to select the lowest "1" data among M1 to _{M12 and N13} . Further, when the signal on the priority cancellation control line 45C is "1", the priority selection in the second priority circuit 45 is canceled and the input data M ₁ to M ₁₂ and N ₁₃ are output as they are. In the second priority circuit 45, input data M ₁ to M ₁₂ , N ₁₃
If all are "0", data of "1" will not be selected in the output order even if upper priority or lower priority is applied. In this case, a carry signal CA is generated. FIG. 6 is a detailed circuit diagram showing an example of the priority circuit 45 shown in FIG _.
Two NAND circuits are provided corresponding to ~ _M12 and _N13 , and the AND circuit group 80 also includes two AND circuits corresponding to each input data _M1 to _M12 and _N13 . is provided. Each input data M ₁
Two NAND circuits and two AND circuits for ~M ₁₂ and N ₁₃ are used depending on the upper priority and the lower priority. The OR circuit group 81 receives the upper data N ₁₃ ,
The OR circuits 82 are sequentially connected in cascade downward from _M12 , and the OR circuit group 82 is sequentially cascaded upward from data _M1 at the bottom. The outputs of the OR circuits of the OR circuit group 81 are respectively input to the NAND circuits corresponding to sequentially lower order data in the NAND circuit group 79. The outputs of the OR circuits in the OR circuit group 82 are respectively input to NAND circuits corresponding to sequentially higher-order data in the NAND circuit group 79. In case of upper priority, upper priority control line 45H
The signal “1” is inverted by the inverter 83, and the signal “0” is applied to the highest OR circuit of the OR circuit group 81. At this time, the signal on the lower priority control line 45L is "0", and the signal "1" inverted by the inverter 84 is applied to the OR circuit group 82. Therefore, all the outputs of the OR circuit group 82 become "1", and all the outputs of the NAND circuits corresponding to the downward priority among the NAND circuit group 79 become "0". A signal “1” is output from the OR circuit in the OR circuit group 81 corresponding to the uppermost data (for example, M ₃ ) having a signal “1” among the input data M ₁ to M ₁₂ and N ₁₃ ; The output of the NAND circuit in the NAND circuit group 79 corresponding to the data below it (for example, M ₁ , M ₂ ) is forcibly set to "0". Therefore, all the AND circuits in the AND circuit group 80 corresponding to the data below the uppermost data "1" (eg, M ₃ ) (eg, M ₁ , M ₂ ) become inactive. In this way, the uppermost data "1" is selected. In the case of downward priority,
This is the opposite of the above. To cancel the priority, use the priority cancellation control line 45.
The signal of C becomes "1", and the signal "0" is applied to all the NAND circuits of the NAND circuit group 79 via the inverter 85. Therefore, all the AND circuits 80 become operational, and the input data M ₁ to _{M 12} , N ₁₃
are led out to output lines L ₁ to L ₁₃ via an AND circuit group 80 and an OR circuit group 86. To prevent data from passing, all signals on lines 45H and 45C are set to "0", and all AND circuits 80 are rendered inactive. Note that unless a signal "1" is particularly given, the signals on lines 45H, 45L, and 45C are normally "0". The carry signal CA is output from the NOR circuit 87. When the upper priority or the lower priority is given, the AND circuit 88 or 89 is enabled by the signal "1" on the line 45H or 45L. AND circuits 88 and 89 have OR circuit groups 82 and 81.
If any of the input data M ₁ to _{M 12} is “1”, the AND circuit 88 or 89 outputs a signal “1”. The outputs of the AND circuits 88 and 89 and data _N13 are input to the NOR circuit 87, and when any of these inputs is "1", the output of the NOR circuit 87 is "0".
Therefore, carry signal CA is not generated. When all three inputs are "0", the output of the NOR circuit 87 is "1", and a carry signal CA is generated. The data on the output lines L ₁ to _{L 12} of the second priority circuit 45 correspond to note names C to B, and the data on the output lines L ₁₃
The data corresponds to the highest note C on the pedal keyboard. The output lines L ₁ to _{L 12} of the second priority circuit 45 are connected to the input ends of the arpeggio register 60 , the coincidence detection circuit 90 , and the code register 91 .
The arpeggio register 60 is a parallel input/parallel output type register with 12 memory locations, and when the signal on the load control line 92 is "1", data on lines _L1 to _L12 is read into each memory location, When the signal 92 is "0", the read data is held. Each storage position of the arpeggio register 60 that stores data for lines _L1 to _L12 is C to
Each corresponds to the 12 note names of B. The output data A ₁ to _{A 12} at each storage location of the arpeggio register 60 is used as priority information for the first priority circuit 44 and is also supplied to the arpeggio sound source section 93 (FIG. 3). As described below, arpeggio register 6
0 stores data corresponding to one note name to be sounded as an arpeggio sound, so the arpeggio sound source section 93 generates an arpeggio sound based on the output data A ₁ to _{A 12} of the arpeggio register 60. The code register 91 is a parallel input/parallel output type register with 13 memory locations, and when the signal on the load control line 94 is "1", the input lines L ₁ -
Read the data of L ₁₂ and L ₁₃ into each storage location. The read data is held when the signal on the load control line 94 is "0". Data line L ₁ ~
Each storage position of the code register 91 corresponding to _L12 corresponds to the note name of C to B, respectively, and the data line _L13
The memory location corresponding to corresponds to the note name of C′. The code register 91 is connected to the code detection logic 68.
It stores the name of the note corresponding to the root note of the chord (chord) detected. Output data from memory locations corresponding to note names C to B of the chord register 91
_R1 to _R12 are added to the single finger gate 95. When the single finger function is selected, the gate control line 96 becomes a signal “1”, data R ₁ to R ₁₂ are selected, and the output line R′ ₁
〜R′ ₁₂ . This output line R′ ₁ ~ R′ ₁₂
The data is for single finger chord sound source section 9.
7 (Figure 3). In addition, the output data R ₁ to _{R 12} of the code register 91 and the pedal keyboard
Output data _R13 corresponding to the C' note name is supplied to the bass sound source section 98 (FIG. 3). The coincidence detection circuit 90 uses the output of the second priority circuit 45.
L ₁ to L ₁₂ and memory output of code register 91 R ₁ to _{R 12}
When the two match, the match detection signal COIN becomes "1". This match detection signal
COIN is used to detect changes in chords caused by pressing different keys on the lower keyboard. The automatic bass chord control device 12 and the automatic arpeggio control device 13 sequentially generate control information according to preprogrammed contents and supply it to the note name information processing device 11. In this embodiment, there are 10 control states that the automatic base code control device 12 can take, and these will be named states S0 to S9. State S0 is a standby state. State control logic 99 within automatic base code controller 12 functions to advance the state to a predetermined state when surrounding (external) signal conditions satisfy predetermined conditions. The contents of state counter 100 represent the current state and are transferred from state control logic 99 to state counter 10.
By giving count data to 0, it advances to a predetermined state. Control information generation logic 101
generates predetermined control information in response to the current state and the processing status of the processing device 11. In addition, in this embodiment, the automatic arpeggio control device 13 can have seven control states, which are classified into states ST ₀ to
We will name it ST ₆ . State ST ₀ is a waiting state. The state control logic 102, state counter 103, and control information generation logic 104 inside the automatic arpeggio control device 13 function in the same manner as described above. When the state of the automatic arpeggio control device 13 is state ST ₀ , that is, the standby state, the time division operation control signal T' is given from the device 13 to the automatic bass chord control device 12, so that the automatic bass chord control device 12 can operate. becomes. The automatic base chord control device 12 advances the states sequentially, generates necessary control information for each state, and outputs the note name information processing device 1.
1 under one's control. During this time, the note name information processing device 11 exclusively performs processing for automatic bass chord performance. In the automatic base code control device 12, from the standby state S0 to the final state (for example, S
When the series of controls up to step 9) is completed, the time division operation control signal T is supplied from the device 12 to the automatic arpeggio control device 13 in the final state. In the automatic arpeggio control device 13, when the time division operation control signal T is applied when the arpeggio sound generation timing signal APL is applied, the automatic arpeggio control device ₁₃ advances from the standby state ST0 to the next state. If the arpeggio sound generation timing signal APL is not applied, the automatic arpeggio control device 13 does not operate even if the time division operation control signal T is applied, and remains in the standby state _ST0 . In this case, since the time division operation control signal T' continues to be output from the automatic arpeggio control device 13, the automatic base chord control device 12 continues to operate. That is, normally, the automatic bass chord control device 12 operates, and when the arpeggio sound generation timing signal APL is given, it waits for the series of control operations of the automatic bass chord control device 12 to end (wait for the generation of signal T), and then next time. The automatic arpeggio control device 13 operates. Therefore, the automatic arpeggio control device 13 operates only when the arpeggio sound generation timing signal APL is applied. By the way, the arpeggio sound timing signal
The APL is generated regardless of the state progression of the automatic base code controller 12 (independent of the generation timing of the signal T). Therefore, actually the signal
The timing at which APL occurs and the timing at which signal T occurs do not necessarily coincide. Therefore, inside the automatic arpeggio control device 13, the arpeggio sound generation timing signal APL is stored in the memory 122, and on the condition that this storage is done, the automatic bass chord control device 12 receives a time division operation control signal. It is devised to move the state for automatic arpeggio control when T is given. When the automatic arpeggio control state reaches the final state, the storage APLM of the arpeggio sound generation timing signal APL is cleared. The timing of state switching in the automatic base chord control device 12 and the automatic arpeggio control device 13 is controlled by a state control pulse Sy. As shown in FIG. 7, the state control pulse Sy has a period 12 times that of the shift clock pulse φ of the data register 46, and a pulse width corresponding to one period of the pulse φ. The data selection device according to the present invention is configured by the combination of the first priority circuit 44 and the second priority circuit 45, and when both circuits 44 and 45 perform selection operation, the original data selection device according to the invention function is demonstrated. In this embodiment, such a function is provided when the pitch name information processing device 11 performs processing operations under the control of the automatic arpeggio control device 13. This point will be explained below. In the following description, the state control logic 102 within the automatic arpeggio controller 13
Details of the state counter 103 and control information generation logic 104 are not shown. Instead,
Each of the above logics 102 and 104 for each state
Let us show the logic executed in a logical formula. The logical expression state control logic 102 for switching states is built in, and the logic for generating control information is built in the control information generation logic 104. FIG. 8 is a flowchart showing the flow of state changes in the automatic arpeggio control device 13. Following this flow, automatic arpeggio control device 1
3 generates control information, and the pitch name information processing device 1
1 is performed. Processing in state ST ₀ : In standby state ST ₀ , the time-division operation control signal T' is always generated to exclusively enable the automatic base code control device 12 to operate. In this waiting state ST ₀ , if the AND condition ST ₀・T・APLM・ARP (→ST ₁ ) is satisfied, the next state
Data for transitioning to ST ₁ is given from the state control logic 102 to the state counter 103, and after one bit time, the state counter 103 has contents representing state ST ₁ . As long as the above conditions are not satisfied, the waiting state ST ₀ continues. In the above conditional expression, the arpeggio sound generation timing storage signal APLM becomes "1" when the memory 122 is set by the arpeggio sound generation timing signal APL. Further, the arpeggio selection signal ARP is a signal given from the arpeggio selector 20, and is "1" when automatic arpeggio performance is selected. Therefore, only if the arpeggio sound timing memory 122 is set when the time division operation control signal T is supplied from the automatic base code control device 12 (APLM=1), the state is moved to state _ST1 . Processing in state ST ₁ : In this state ST ₁ , it is checked whether or not a key is pressed on the lower keyboard for automatic arpeggio performance. When a key is pressed on the lower keyboard, the lower keyboard key press detection signal LKM is "1". Therefore,
When the logical condition ST ₁ , Sy, LKM (→ST ₂ ) is established at the timing of state control pulse Sy, the next state ST ₂
will be moved to If the key is not pressed, the key press detection signal LKM is "0". In this case, the condition ST ₁・Sy・(→ST ₀ ) is satisfied, and the state is returned to the waiting state ST ₀ . It is designed to advance to the next state ST ₂ only if a key is pressed on the lower keyboard. Processing in state ST ₂ : In this state ST ₂ , it is determined whether the arpeggio is a "chord arpeggio" or a normal "automatic arpeggio" (this will be referred to as a normal arpeggio). "Chord arpeggio" is an automatic arpeggio performance that is performed when the single finger function is selected as an automatic bass chord performance. A plurality of automatic arpeggio sounds are created using the root note data and information representing chord types stored in a seventh chord memory 71 and a minor chord memory 73, and each sound is sequentially sounded in an arpeggio format. "Normal Arpeggio" performs an arpeggio using only the note name information currently pressed on the lower keyboard. In the case of chord arpeggio, the single finger function selection signal SF is “1”,
When the state control pulse Sy is generated, the condition ST ₂ · Sy · SF (→ST ₃ ) is satisfied, and the state is moved to state ST ₃ .
At the same time, the control information generation logic 104 (Fig. 3)
to the data register 46 of the pitch name information processing device 11
control lines 61 and 62 and control line 12 of chord arpeggio follower tone data creation logic 59
A signal “1” is supplied to the signal “1”. The chord arpeggio follower data creation logic 59 receives the seventh signal CH 7 and the minor signal supplied from the seventh chord memory ₇₁ and the minor chord memory 73.
It generates follower pitch data according to CHm, and when a signal "1" is given to the control line 123, it outputs the follower pitch data, and the OR circuit group 5
8 to the data register 46. At this time, the code control line 6 of the data register 46
1 and the hold control line 62 become signal "1", the hold of the data register 46 is released, and the subordinate tone interval data given from the chord arpeggio subordinate tone data creation logic 59 is newly read into the data register 46. The correspondence between each storage location D ₁ to _{D 12} of the data register 46 and the pitch is shown in Table 2 above. The intervals of the follower note data generated from the code arpeggio follower note data creation logic 59 are as follows. First, if both the seventh signal CH ₇ and the minor signal CHm are "0", it means a "major chord", so subordinate tone data corresponding to the three intervals of 1st, major 3rd, and perfect 5th are generated respectively. Then, a signal "1" is read into storage locations D ₁ , D ₅ , and D ₈ of the data register 46, respectively. If the seventh signal _CH7 is "1" and the minor signal CHm is "0", it means a "seventh chord", so it corresponds to the four intervals of 1st, major 3rd, perfect 5th, and minor 7th. Generate follower sound data and store data at storage locations D ₁ , D ₅ ,
Signals "1" are read into D ₈ and D ₁₁ , respectively. If the seventh signal CH ₇ is "1" and the minor signal CHm is also "1", it means a "minor seventh chord", so the four intervals of 1st, minor 3rd, perfect 5th, minor 7th, respectively. Generates corresponding follower sound data and stores data at storage locations D ₁ , D 4 , D ₄ ,
Signals "1" are read into D ₈ and D ₁₁ , respectively. If the seventh signal CH ₇ is "0" and the minor signal CHm is "1", it means a "minor chord", so the follower tone data corresponds to the three intervals of 1st, minor 3rd, and perfect 5th. is generated and the storage locations D ₁ , D ₄ and D 4 of the data register 46 are
A signal “1” is read into _{each D8} . If the conditions ST ₂ , Sy, and SF are satisfied, the above-mentioned processing is performed, and the priority information T ₁ to _{T 12 is}
The counter 124 (FIG. 3) for generating . In the case of normal arpeggio, the single finger function selection signal SF is "0", and the condition ST ₂ ·Sy · (→ST ₅ ) is satisfied when the state control pulse Sy is generated, and the state is moved to state ST ₅ . Processing of state ST ₃ ; This state ST ₃ and the next state ST ₄ are executed in the case of "chord arpeggio". In states ST ₃ and ST ₄ , the subordinate interval data read into the data register 46 in the state ST ₂ is shifted to the right, and the position of the root note (1st interval) data is stored in the code register 91. Performs processing to match the position of the note name of the root note. The contents of the state counter 103 are state ST ₃
, the control information generation logic 104 outputs the control line 4 of the data selector
7D, a signal "1" is supplied to the control line 49T of the priority information select gate 48, the upper priority control line 44H of the first priority circuit 44, and the lower priority control line 45L of the second priority circuit 45, respectively.
As a result, the data selector 47 selects the data in each storage location D ₁ to _{D 12} of the data register 46 and inputs the selected data to the first priority circuit 44 via the lines N ₁ to N ₁₂ . Using T ₁ ~ _{T 12} as priority information, input data by upward priority
Select _N1 to _N12 . The data selected by the upward priority is passed through the OR circuit group 58 to the data line.
The data is led to M ₁ to M ₁₂ and becomes input data to the second priority circuit 45 . In the second priority circuit 45, the control line 4
A single data "1" is selected by the signal "1" of 5L with downward priority, and the selected data is input to the coincidence detection circuit 90 via lines _L1 to _L12 . Coincidence detection circuit 90 compares the data on lines L ₁ to L ₁₂ and the contents of code register 91 . still,
The chord register 91 stores root note pitch name data detected during automatic bass chord processing. In the upward priority in the first priority circuit 44, all data higher than priority information _T1 to _T12 are selected. Further, in the lower priority in the second priority circuit 45, only one lowermost data "1" is selected. Therefore, in state ST ₃ , among the data in each storage location D ₁ to _{D 12} of the data register 46, the lowest data “1” is the data above the priority information T ₁ to _{T 12} . Only one is selected. The first priority circuit 44 cancels the lower data, the second priority circuit 45 cancels the upper data, and only one data between them is selected. Such a first priority circuit 44
Intermediate data selection using both the first priority circuit 45 and the second priority circuit 45 will be referred to as masking priority selection. If the data selected by the above-described masking priority selection and applied to lines L ₁ to L ₁₂ match the data stored in the code register 91, a match detection signal COIN is generated. This means that the position of a single data “1” derived on lines L ₁ to _{L 12} by masking priority selection is located in the code register 9.
This means that it matches the note name position of the root note stored in 1. In this case, the condition _ST3・Sy・COIN (→ _ST5 ) is satisfied at the timing of the state control pulse Sy, and the state is moved to _ST5 . If the data selected by the above masking priority selection does not match the root note name, the match detection signal COIN is "0" and the state control pulse Sy
At the timing of , the condition ST ₃・Sy・(→ST ₄ ) is satisfied, and it is moved to 7th ST ₄ . Processing of state ST ₄ ; In this state ST ₄ , when the condition ST ₄ ·Sy is satisfied at the timing of the state control pulse Sy, the counter 124 (see FIG. 3) for generating priority information T ₁ to _{T 12} is ) and advances the contents of the data register 46 by one count.
A signal "1" is supplied to the right shift control line 64 and the hold control line 62 of. The counter 124 is a ring counter and sequentially sets bits T1 to T12 to "1" in response to count values of ₁ to ₁₂ . As a result, the hold of the data register 46 is released, the state is shifted to the right, and the state control pulse
One clock pulse φ at the same timing as Sy
is given, the content of data register 46 is 1
The position is shifted to the right. That is, position D ₁ ~
The data at D ₁₁ is transferred to locations D ₂ -D ₁₂ and the data at location D ₁₂ is transferred via circulation line 67 to location D ₁ . Further, when the condition ST ₄ ·Sy (→ST ₃ ) is satisfied, the state control logic 102 performs control to return the state to ST ₃ . In state _ST3 , the same processing as described above is performed. However, the data applied from the data register 46 to the data lines N ₁ to N ₁₂ via the data collector 47 is shifted one bit to the right (upward) from the data in the previous state ST ₃ processing, and the first The contents of the priority information _T1 to _T12 used in the priority circuit 44 are also incremented by one. In this way, states _ST4 and _ST3 are repeated until the coincidence detection signal COIN is generated from the coincidence detection circuit 90 in state _ST3 , and when the coincidence detection signal COIN is generated, the process moves to state _ST5 . In state _ST2 , the priority information generation counter 124 has been reset. Therefore,
In the first state _ST3 , priority information _T1 to _T12 are all "0". Next, in state ST ₄ , when the counter 124 is incremented by 1, the data of bit T ₁ of the priority information T ₁ to T ₁₂ becomes “1”, and in the second state ST ₃ , the priority information T ₁ to Only bit T ₁ of the contents of T ₁₂ is “1”
It is becoming. Thereafter, each time state ST ₄ is repeated, priority information T ₁ used in state ST ₃
The contents of ~ _T12 change sequentially (that is, data "1" sequentially shifts in the order of bit _T1 → _T2 → _T3 → ... → _T12 ). For example, FIG. 9 shows an example in which follower note data representing a minor seventh chord is read into the data register 46 from the code arpeggio follower note data creation logic 59, and according to this example, state ST ₃ is read.
and ST ₄ processing will be explained. first state
In ST ₃ , 1st, minor 3rd, 5th, and minor 7th
Signals "1" are stored in storage locations D ₁ , D ₄ , D ₈ , and D ₁₁ of the data register 46, which correspond to the pitches of degrees. At this time, the priority information T ₁ -T ₁₂ are all "0", so the first priority circuit 44 (see FIG. 5) selects all data on the data lines N ₁ -N ₁₂ . Second priority circuit 4 with downward priority
5, the memory location D ₁ is the lowest data “1”
Select data. Here, code register 9
It is assumed that the signal "1" is stored in the storage position corresponding to the F sound. Since the note name in memory location _D1 corresponds to C note, the output of the match detection circuit 90
COIN is a signal “0” indicating mismatch. Therefore, we move to state ST ₄ , and the state control pulse Sy
At the timing of , the data register 46 is shifted to the right by one bit position, and the bits of priority information T ₁ to _{T 12} are
T ₁ becomes “1”. As a result, in the second state _ST3 , a signal "1" is stored in each of the storage locations _D2 , _D5 , _D9 , and _D12 . When the priority information T ₁ becomes "1", the lowest input data N ₁ corresponding to bit T ₁ is blocked in the first priority circuit 44 (see FIG. 5), which is in the upper priority state, and the data is Data _N2 to _N12 above _N1 are selected. 2nd priority circuit 4
5 has downward priority, so the data line
Among the data in storage positions _D2 to _D12 given from _N2 to _N12 via _M2 to _M12 , the lowest "1" data is selected preferentially. Since the data “1” corresponding to the 1st interval (root note) has been shifted to the storage position D ₂ , the data “1” in this storage position D ₂ is selected and the output line L of the second priority circuit 45 is ₁ ～ _L12
Of these, a signal "1" is supplied only to line L ₂ (see FIG. 6) corresponding to the C# tone. If the match detection signal COIN is not generated, the state returns to
ST ₄ , the contents of the data register 46 are shifted to the right by one bit position, and the priority information bit T ₂ is shifted to the right.
becomes the signal “1”. Therefore, in the third seventh ST ₃ , the signal "1" is stored in storage positions D ₃ , D ₆ , D ₁₀ and D ₁ of the data register 46, respectively. Figure 4, 1st
In the priority circuit 44, the priority information _T2 signal is “1”
and the OR circuit 52 via the OR circuit 56-2.
-2 and 52-1 are supplied with the signal "1", and AND circuits 50-1 and 50-2 become inactive. Therefore, data _{N2 and N1} below data N2 corresponding to bit _T8 are blocked. Since bits T ₃ -T ₁₂ are "0", all data N ₃ -N ₁₂ above bit T ₂ of the priority information are selected. Therefore,
The data at storage locations D ₃ , D ₆ , and D ₁₀ are selected and stored in the second
The data is input to the priority circuit 45, and only the data corresponding to the storage location _D3 is selected by the circuit 45 due to downward priority. In the third state _ST3 , data "1" corresponding to one degree interval has been shifted to the storage position _D3 . Thereafter, each time the state _ST4 is repeated, the contents of the priority information _T1 to _T12 change sequentially toward _T12 , and the contents of the data register 46 are also shifted to the right one bit at a time. In FIG. 9, the lower part of the priority information T ₁ , T ₂ . As is clear from FIG. 9, the values of the priority information T ₁ to T ₁₂ change sequentially each time states ST ₃ and ST ₄ are repeated, and the contents of the data register 46 are also shifted to the right accordingly. It will be done. Therefore, the single data "1" selected as a result of the masking priority selection using the first priority circuit 44 and the second priority circuit 45 always corresponds to a one-degree interval (root note). The note name corresponding to the 1 degree interval data is shifted to the treble side sequentially in the order of C→C#→D→... as the pitch is shifted to the right. Leftmost storage location D ₁ when first state ST ₃
When data "1" corresponding to the first degree interval is entered into the storage position _D6 by the fifth right shift, the first degree interval corresponds to the note name F. As mentioned above, the data corresponding to note name F is recorded in the chord register 91 as the root note, so in the case of FIG.
Coincidence detection signal COIN in the second state ST ₃
is generated. Then, the state moves to ST ₅ . In addition, the right shift is performed 12 times and the priority information T ₁ ~
If the coincidence detection signal COIN is still not generated even when the most significant bit _T12 of _T12 becomes "1", it means that the root note data has not been stored on the code register 91 side. Therefore, in this case, if the condition ST ₃ ·Sy ·T ₁₂ · (→ST ₀ ) is satisfied at the generation timing of the state control pulse Sy, control is performed to return to the waiting state ST ₀ . Processing in state ST ₅ ; In state ST ₅ , a single note to be produced as an arpeggio note is selected and its note name data is read into the arpeggio register 60. In this case, the selection of a single tone is performed by masking-type priority selection using the first priority circuit 44 and the second priority circuit. For chord arpeggio, data register 46
The note name data stored in is used as an arpeggio note, and one of the notes is selected. By repeating the processing in states ST ₃ and ST ₄ , in the last state ST ₃ before moving to state ST ₅ , each storage location D ₁ of the data register 46 is
~D ₁₂ corresponds to the pitch names C to B. In other words, when the subordinate tone data having a predetermined interval relationship is shifted to the right while maintaining the interval relationship, and the position of the one-degree interval data matches the pitch name position of the root note stored in the code register 91, the state is This is because it moves from ST ₃ to ST ₅ . In the example of FIG. 9, in the last state ST ₃ , the data "1" corresponding to the first degree interval is located in the memory location D ₆ corresponding to the root note name F, and the data corresponding to the minor third interval is in the note name. Data corresponding to G# is located in memory location _D9 , data corresponding to perfect fifth interval is located in memory location _D1 corresponding to pitch name C, and data corresponding to minor seventh interval is located in pitch name D#. It is located in memory location _D4 . Therefore,
The data register 46 contains note names F, G#, C, D.
The note name data of the "F minor seventh chord" consisting of # is stored respectively. Since the signal on the hold control line 62 is "0", the storage of pitch name data in the data register 46 is self-held. In the case of chord arpeggio, the single finger function selection signal SF is “1” and the state
When the condition _ST5・SF is satisfied in _ST5 , the data selector 47 (fourth
A signal "1" is applied to the control line 47D in FIG. As a result, the data register 47 selects data from each storage location D ₁ to _{D 12} of the data register 46 and supplies it to the first priority circuit 44 via the data lines N ₁ to N ₁₂ . In the case of a normal arpeggio, the notes actually pressed on the lower keyboard are sounded in an arpeggio format. In this case, the single finger function selection signal SF
is "0" and in state _ST5 , if the condition _ST5 . is satisfied, a signal "1" is applied to the control line 47L of the data selector 47. As a result, the output line 34-1 of the lower keyboard circuit 31
The pressed key note name data from 34-12 is selected by the data selector 47, and the data lines _N1 to _N12 are selected by the data selector 47.
After that, the data becomes the selected data of the first priority circuit 44. The order in which the note name data stored in the data register 46 or the lower keyboard note name memory register 36 is selected corresponds to the order in which the arpeggio tones are produced. There are two types of sounding order in automatic arpeggio performance. One is to sound the notes in order starting from the lowest note, and this is referred to as an up state. The other way is to pronounce the notes in order starting from the high pitch side, and this is called the down state. Controlling whether the sounding order is in an up state or a down state is controlled by an up-down control section (not shown) provided inside the automatic arpeggio control device 13. In the case of an up state, an up signal US (not shown) is given to the control information generation logic 104 from the up down control section. In the case of a down state, a down signal DS (not shown) is given from the up-down control section. In the UP state, the note name data stored in the data register 46 or the lower keyboard note name memory register 36 is selected in order from the low note side, and in the DOWN state, the note name data is selected in order from the treble note side. However, selection of one note name is performed only when one arpeggio sound generation timing signal APL is applied. Therefore, only a single note name is selected within one cycle of states ST ₀ to _{ST 6} for automatic arpeggio, and the selected note name is stored in the arpeggio register 60. In the arpeggio register 60, the signal "1" is held only at the storage location corresponding to the single selected note name, and the signal "1" is transmitted to the corresponding output line (any one of _A1 to _A12) . 1) to the arpeggio sound source section 93 (FIG. 3). The arpeggio sound source section 93 generates a sound source signal corresponding to a single note name stored in the arpeggio register 60, adds a percussion-type amplitude envelope to the sound source signal, and outputs the resultant sound source signal. Therefore, the note name data stored in the arpeggio register 60 when the state switches from ST ₃ to ST ₅ represents the note produced at the previous arpeggio sound production timing. In order to sequentially raise or lower the pitch of the generated note according to the up or down state, it is necessary to select a note name that is higher or lower than the note name of the previously generated note stored in this arpeggio register 60. There is. Therefore, in state _ST5 , a signal "1" is applied to the control line 49A of the priority information select gate 48.
data representing the memory contents of the arpeggio register 60 (data representing the note name of the previously generated note)
A ₁ to _{A 12} are selected and used as priority information for the first priority circuit 44. Also, in the masking type priority selection using the first priority circuit 44 and the second priority circuit 45, control is performed according to the up state or down state. When the up-down control section (not shown) instructs the up state, the up signal US is "1", and when the condition _ST5.US is satisfied in state _ST5 , the first priority is A signal “1” is supplied to the upper priority control line 44H of the circuit 44 and the lower priority control line 45L of the second priority circuit 45, respectively. Therefore, the 11th priority circuit 44 performs an upward priority selection operation, and selects input data (some of N ₁ to N ₁₂ ) corresponding to pitch names higher than the pitch names represented by priority information A ₁ to _{A 12} . Select all.
The selected data is led to data lines M ₁ to M ₁₂ via OR circuit group 58 and input to second priority circuit 45 . The second priority circuit 45 selects the lowest note data "1" from among the note name data selected by the first priority circuit 44. An example of masking-type priority selection in this up state is shown in the column of state _ST5 in FIG. 1st
Among the data input lines N ₁ to _{N 12} of the priority circuit 44
Assume that the data of N ₁ , N ₄ , N ₆ , and N ₉ are “1”. At this time, the arpeggio register 60 has D.
#Assume that the sound data is stored.
Therefore, in the priority information _A1 to _A12 , bit _A4 corresponding to the D# tone is "1", and the first priority circuit 44 transfers data N from bit _A4 downward, that is, from the D# tone to the bass side. ₁ to _N4 are blocked, and data _N5 to higher than bit _A4 , that is, higher than D# note.
N ₁₂ is selected. This selected data N ₅ ~
The data of the signal "1" among _N12 is the data corresponding to _N6 and _N9 . Therefore, in the second priority circuit 45, the signal is "1" on the lowest tone side. Select data " ₁ " of input line M6 corresponding to _N6 . In the case of Figure 9, the note names used as arpeggio notes are C, D#, F, corresponding to data N ₁ , N ₄ , N ₆ , N ₉ ,
and G#, and the previous generated sound was D#. Therefore, data (N ₆ ) corresponding to the F note, which is the note above the D# note, was selected. In the case of the down state, the down storage location DS is "1" and the condition ST ₅ DS is satisfied when the state is ST ₅ . Based on this, the first
A signal "1" is applied to the lower priority control line 44L of the priority circuit 44 and the upper priority control line 45H of the second priority circuit 45, so that the first priority circuit 44 performs lower priority selection, and the second priority circuit 45 performs upper priority selection. Make a priority selection. Therefore, priority information A ₁ ~
Data with a pitch name lower than the pitch name of the previously generated sound represented by A ₁₂ (any of N ₁ to N ₁₂ ) is sent to the first priority circuit 4.
4, and the second priority circuit 45 selects the pitch name data of the highest note among the selected pitch name data. Therefore, among the arpeggio constituent tones, a note with a pitch lower than the previously generated note is selected. For example, as shown in state ST ₅ in FIG. 9, data N, N ₄ , N ₆ , N ₉
It is assumed that the signal is "1" (data corresponding to the arpeggio constituent notes). At this time, it is assumed that the previously generated sound was the F sound and that bit _A6 of the priority information _A1 to _A12 is "1". The first priority circuit 44 selects data N ₁ and N ₄ corresponding to C and D#, which are lower than the previous tone F, and the second priority circuit 45 selects D#, which is the highest note among C and D#. Select the data (N ₄ ) corresponding to . Therefore, note D# below previous note F is selected. In the up state, if the previously generated note is the highest note of the arpeggio constituent notes (in the example of FIG. 9, it is the G# note corresponding to data N ₉ ), the first priority circuit 44 gives priority to the highest note as priority information and gives upward priority. Since selection is performed, all note name data from the highest note to the lower note side, including the highest note, is blocked. Therefore, the input lines M ₁ to _{M 12} of the second priority circuit 45 are not given the data of the signal “1”. Also, in the down state,
If the previously generated note is the lowest note of the arpeggio constituent notes (in the example in Figure 9, it is the C note corresponding to data N ₁ ),
The first priority circuit 44 operates to select pitch name data lower than the lowest pitch using the lowest pitch as priority information, and blocks all pitch name data from the lowest pitch to the higher pitch. Therefore, as described above, the data on the input lines _M1 to _M12 of the second priority circuit 45 are all "0". In such a case, the second priority circuit 4
The output of the NOR circuit 87 (FIG. 6) of No. 5 becomes "1", and the carry signal CA is generated. If carry signal CA is generated, state control pulse
At the timing of Sy, the condition ST ₅・Sy・CA (→ST ₆ ) is established, and the state becomes ST _5.
to ST ₆ . If the previously generated note is not the highest or lowest note, the carry signal CA is not generated, and single note name data is selected for the input lines _M1 to _M12 of the second priority circuit 45. in this case,
The condition _ST5・Sy・(→ _ST0 ) is established at the timing of the state control pulse Sy, and the signal “1” is supplied to the load control line 92 of the arpeggio register 60, and the state _ST5 is changed from the waiting state ST. Moved to ₀ . Therefore, the arpeggio register 60 releases its self-holding state, erases the memory of the note name data of the previously generated note, and reads and stores a single new note name data given from lines _L1 to _L12 . The arpeggio sound source section 93 generates a sound source signal for the note name newly stored in the arpeggio register 60. In this way, the arpeggio tones are sounded one by one in pitch order at predetermined time intervals. Processing in state ST ₆ ; State ST ₆ is a process that is executed only when the carry signal CA is output in state ST ₅ , and no particular explanation will be given here. this state
When the processing in ST ₆ is completed, the state is returned to the waiting state ST ₀ . As explained above, according to the present invention, it is possible to select data "1" at any bit position from among multiple bits of digital data, so it is possible to select data "1" at any bit position from among multiple bits of digital data. It can be used for data selection processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one implementation of the data selection device according to the present invention, FIG. 2 is a diagram explaining the selection operation of the device shown in FIG. 1, and FIG. 3 is an electronic data selection device to which the data selection device of the invention is applied. A block diagram schematically showing an example of a musical instrument, FIG. 4 is a block diagram showing details of the note name information processing device shown in FIG. 3, and FIG. 5 is a circuit diagram showing a detailed example of the first priority circuit shown in FIG. 4. , Figure 6 is the fourth
A circuit diagram showing a detailed example of the second priority circuit shown in FIG.
FIG. 8 is a flowchart showing state transitions when the note name information processing device performs processing operations based on control by the automatic arpeggio control device shown in FIG. 3; FIG. is the state ST ₃ shown in Figure 8,
This is an explanatory diagram showing a specific example of the processing operation of the note name information processing device in ST ₄ and ST ₅ , and shows the state of data at positions corresponding to 12 note names (or number of note degrees) and the state of masking type priority selection. It is something. 22...first selection circuit, 23...second selection circuit, 1
0... Automatic performance section, 11... Pitch name information processing device, 12
...Automatic bass chord control device, 13...Automatic arpeggio control device, 44...First priority circuit, 45...Second
Priority circuit, 46...data register, 47...data selector.

Claims (1)

[Scope of Claims] 1. A first gate means for selectively outputting a plurality of ranked input data separately; and a first gate means for selectively outputting a plurality of ranked input data; gate control means for sending a gate control signal for prohibiting output and selecting other data to the first gate means; and setting the predetermined order and transmitting the set order to the gate control means. a second gate means for selecting one of the lowest or highest data among the data selected and output by the first gate means. 2. A first gate means that selectively outputs a plurality of ranked input gates, and prohibits the output of data corresponding to a rank higher or lower than the first predetermined rank among the input data. a first gate control means for sending a first gate control signal for selecting other data to the first gate means; and setting the first predetermined order, and setting the first predetermined order, a first instruction means for instructing the first gate control means to output the output data of the first gate means; a second gate means for selectively outputting the output data of the first gate means; and an output of the first gate means. A second gate control signal for inhibiting the output of data corresponding to a lower or higher rank than a second predetermined rank among the data and selecting other data is sent to the second gate means. a second gate control means for setting the second predetermined order, and a second instruction means for instructing the second gate control means of the set order. Device.