JPS6148238A - Squelch device - Google Patents

Squelch device

Info

Publication number
JPS6148238A
JPS6148238A JP17065284A JP17065284A JPS6148238A JP S6148238 A JPS6148238 A JP S6148238A JP 17065284 A JP17065284 A JP 17065284A JP 17065284 A JP17065284 A JP 17065284A JP S6148238 A JPS6148238 A JP S6148238A
Authority
JP
Japan
Prior art keywords
circuit
squelch
voltage
output
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17065284A
Other languages
Japanese (ja)
Other versions
JPS6355253B2 (en
Inventor
Satoshi Shimizu
智 清水
Jun Yamada
純 山田
Shogo Iizuka
飯塚 捷吾
Tetsuaki Nakanishi
徹明 中西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17065284A priority Critical patent/JPS6148238A/en
Publication of JPS6148238A publication Critical patent/JPS6148238A/en
Publication of JPS6355253B2 publication Critical patent/JPS6355253B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To attain output of voice even within a prescribed range of a reception input during digital squelch operation by providing a comparator circuit among a squelch voltage varied by a potentiometer, a noise voltage and a digital squelch operating voltage. CONSTITUTION:A radio signal having a digitized voice is extracted by a receiver 2, demodulated by a demodulation circuit 3 to transmit a digital signal (a) and a synchronizing signal (b). The signals a, b are inputted to a decoding circuit 4 and a digital squelch circuit 10, which gives a l level output when the signal is coincident with a prescribed digital signal system and gives a 0 level output when dissident. A noiselevel of the signal (a) subject to detection 8 through an HPF7 is inputted to a comparator 11 of a noise controller 9. The controller 11 uses resistors 15, 16 12 and a squelch variable resistor 13 to set a voltage corresponding to a criterion input voltage of the circuit 10 and a voltage Vse within the noise squelch range, and they are fed respectively to comparators 14, 11. In setting them as Vse>V0, the controller 9 connects/disconnects the amplifier 5 depending on the discrimination of the circuit 10 and the comparator 11.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、デジタル変調方式の移動無線用受信機等に使
用するスケルチ装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a squelch device used in a digital modulation mobile radio receiver or the like.

2 ・ 従来例の構成とその問題点 従来、デジタル変調方式の移動無線用受信機では、復調
信号のノイズ成分を検出して音声出力を接、断するノイ
ズスケルチ回路と、復調信号が所定のデジタル信号方式
になっているかどうかを検出して、音声出力を接、断す
るデジタルスケルチ回路とが内蔵されている。そして、
このデジタルスケルチ回路で妨害波の復号を防止してい
た。
2. Conventional configuration and its problems Traditionally, digital modulation mobile radio receivers have a noise squelch circuit that detects the noise component of the demodulated signal and connects or disconnects audio output, and a noise squelch circuit that connects or disconnects the audio output by detecting the noise component of the demodulated signal. It has a built-in digital squelch circuit that detects whether the signal format is selected and connects or disconnects the audio output. and,
This digital squelch circuit prevented decoding of interference waves.

しかしながら、この従来例では第1図のように、ノイズ
スケルチが動作可能となる無線機の受信入力電圧レベル
に比べ、デンタルスケルチが動作可能となる無線機の受
信入力電圧レベルが高いので、たとえば受信人力QdB
μVで通話中に急に一4dBμVに下がった場合、実際
は聞き取れる範囲内なのにデジタルスケルチ回路が動作
して音声出力が断となる問題点があった。
However, in this conventional example, as shown in Figure 1, the reception input voltage level of the radio that enables the dental squelch is higher than the reception input voltage level of the radio that enables the noise squelch. Human power QdB
If the μV suddenly drops to -4 dBμV during a call, the digital squelch circuit will operate and the audio output will be cut off, even though it is actually within the audible range.

発明の目的 本発明は、−に記従来例の問題点を除去するものであり
、デジタルスケルチ回路が動作する受信入力であっても
、ノイズスケルチ範囲内のときは音3 ヘ一/ 声量力が接続される優れた雑音制御装置を提出すること
を目的とする。
OBJECTS OF THE INVENTION The present invention eliminates the problems of the prior art as described in (-).Even if the receiving input is operated by a digital squelch circuit, when the noise is within the squelch range, the sound volume is reduced to 3. The purpose is to present an excellent noise control device that can be connected.

発明の構成 本発明は、上記目的を達成するために、スケルチボリュ
ームの設定がデジタルスケルチの判定限界以下のときは
ノイズスケルチ回路のみの判定で増幅器の接、断を行な
い、スケルチボリュームの設定がデジタルスケルチの判
定限界以上のときはノイズスケルチ回路の判定とデジタ
ルスケルチ回路の判定の双方の判定で増幅器の接、断を
行なうよう構成したものであり、デジタルスケルチ回路
が動作する受信入力であっても、ノイズスケルチ範囲内
のときは音声出力が接続されるという利点を有する。
SUMMARY OF THE INVENTION In order to achieve the above object, the present invention connects or disconnects an amplifier based only on the judgment of the noise squelch circuit when the squelch volume setting is below the judgment limit of the digital squelch. When the squelch judgment limit is exceeded, the amplifier is connected or disconnected based on both the noise squelch circuit judgment and the digital squelch circuit judgment, and even if the receiving input is the one where the digital squelch circuit operates , it has the advantage that the audio output is connected when it is within the noise squelch range.

実施例の説明 以下に本発明の一実施例の構成について、図面とともに
説明する。第2図は本発明の一実施例による雑音制御装
置を含むデジタル無線の受信装置である。
DESCRIPTION OF EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows a digital radio receiving device including a noise control device according to an embodiment of the present invention.

第2図において、1はアンテナ、2は希望の無線周波数
を抽出する受信器、3はデジタルの復調信号aと同期信
号l〕を出力する復調回路である。
In FIG. 2, 1 is an antenna, 2 is a receiver that extracts a desired radio frequency, and 3 is a demodulation circuit that outputs a digital demodulation signal a and a synchronization signal l].

4はデジタル復調信号aと同期信号すを入力して、アナ
ログの復号信号Cを出力する復号回路、5は復号信号C
を入力して増幅する増幅器、6は出力端子である。この
増巾器5は制御信号dにより出力端子6への出力を接、
断できるものである。7は復調信号aを入力して高域成
分のみ抽出する高域フィルタ、8は高域フィルタ7の出
力を検波する検波回路、9は本実施例の雑音制御装置、
10は復調信号aおよび同期信号すを入力して所定の信
号方式かどうかを判定するデジタルスケルチ回路である
。このデジタルスケルチ回路10は復調信号に含まれる
ノイズ成分の多少で第1図のようにアンテナ1の受信入
力が一3dBμ■以上のときから、所定の信号方式かど
うかを判定開始するものである。11は検波回路8の信
号を入力し、VsQの電圧と比較する比較回路、12.
13は十電源とアース間に直列に接続された抵抗であり
、抵抗13は抵抗値が可変である。14はV8Qの電圧
と、5ベ−ノ 抵抗15および抵抗16の分割電圧で作られる、voの
電圧を比較する比較器である。17は比較器14とデジ
タルスケルチ回路10の信号を入力するアクティブロー
のOR,回路、18はこのOR回路17の信号と比較器
11の信号を入力するアクティブローのAND回路であ
り、このAND回路18の信号は増幅器5の出力端子6
への接、断を制御するものである。
4 is a decoding circuit that inputs the digital demodulated signal a and the synchronization signal S and outputs an analog decoded signal C; 5 is a decoded signal C
An amplifier inputs and amplifies the signal, and 6 is an output terminal. This amplifier 5 connects the output to the output terminal 6 by the control signal d,
It is something that can be cut off. 7 is a high-pass filter that inputs the demodulated signal a and extracts only high-frequency components; 8 is a detection circuit that detects the output of the high-pass filter 7; 9 is a noise control device of this embodiment;
Reference numeral 10 denotes a digital squelch circuit which inputs the demodulated signal a and the synchronizing signal S and determines whether the signal format is a predetermined one. This digital squelch circuit 10 starts determining whether or not a predetermined signal format is used when the receiving input of the antenna 1 is 13 dBμ or more as shown in FIG. 1, depending on the amount of noise components contained in the demodulated signal. 11 is a comparison circuit which inputs the signal of the detection circuit 8 and compares it with the voltage of VsQ; 12.
Reference numeral 13 denotes a resistor connected in series between the power source and the ground, and the resistance value of the resistor 13 is variable. A comparator 14 compares the voltage of V8Q with the voltage of vo, which is created by the voltage divided by the five-vane resistor 15 and resistor 16. 17 is an active low OR circuit that inputs the signals of the comparator 14 and the digital squelch circuit 10; 18 is an active low AND circuit that inputs the signal of the OR circuit 17 and the signal of the comparator 11; 18 is the output terminal 6 of the amplifier 5.
It controls connection and disconnection to

次に、上記実施例の動作について説明する。第2図にお
いて、音声がデジタル化された無線信号がアンテナ1に
到来すると受信器2で所望の無線周波数のみを抽出し、
復調回路3で復調する。復調回路3はデジタルの復調信
号aと所定の論理で作られた同期信号すとを送出する。
Next, the operation of the above embodiment will be explained. In FIG. 2, when a radio signal containing digitized audio arrives at antenna 1, receiver 2 extracts only the desired radio frequency.
The demodulation circuit 3 demodulates the signal. The demodulation circuit 3 sends out a digital demodulation signal a and a synchronization signal S created using predetermined logic.

デジタルスケルチ回路10はこの復調信号aと同期信号
すとから所定のデジタル信号方式かどうかを判定し、合
致していれば「1」、不一致の場合は「0」を出力する
。一方、復調信号aの高域成分を高域フィルタ7で抽出
して、検波回路8で検波する。この検波回路8の出力電
圧は高域成分が多いほど、すなわち弱電界の入力電圧で
あればあるほど大きくなる。
The digital squelch circuit 10 determines whether the demodulated signal a and the synchronization signal are a predetermined digital signal system, and outputs "1" if they match, and "0" if they do not match. On the other hand, a high-frequency component of the demodulated signal a is extracted by a high-pass filter 7 and detected by a detection circuit 8. The output voltage of the detection circuit 8 increases as the number of high-frequency components increases, that is, as the input voltage of the weaker electric field increases.

雑音制御装置9はV。をデジタルスケルチ回路10の判
定限界の入力電圧(−3dBμV)に対応する検波回路
9の電圧に設定されている。また■8Qの電圧値は、可
変抵抗(スケルチボリューム)13の抵抗値により定め
られ、第1図のノイズスケルチの範囲、−1QdBμ■
〜]QdBμVまでに対応する検波回路9の電圧変化に
なるよう設定されている。
The noise control device 9 is set to V. is set to the voltage of the detection circuit 9 corresponding to the judgment limit input voltage (-3 dBμV) of the digital squelch circuit 10. Also, the voltage value of ■8Q is determined by the resistance value of the variable resistor (squelch volume) 13, and the noise squelch range in Figure 1 is -1QdBμ■
~]QdBμV is set so that the voltage change of the detection circuit 9 corresponds to up to QdBμV.

(1)  Vo > V6Qの場合 すなわち、スケルチボリー−ム13がデジタルスケルチ
回路100判定限界より小さく(]QdBμV〜−3d
BμV)設定されていると、比較器14の出力は常に「
0」であり、OR回路17の出力も常に「0」となる。
(1) When Vo > V6Q, that is, the squelch volume 13 is smaller than the judgment limit of the digital squelch circuit 100 (]QdBμV~-3d
BμV), the output of the comparator 14 is always “
0", and the output of the OR circuit 17 is also always "0".

すなわち、OR回路17はデジタルスケルチ回路10の
出力には無関係になる。
That is, the OR circuit 17 becomes unrelated to the output of the digital squelch circuit 10.

ここで、受信入力電圧がVsQより大きく、従って検波
回路8の出力電圧がVSOより大きいときは比較器11
の出力は「1」となり、A、 N D回路18も出力が
「1」で増幅器5の出力電圧を断にする。
Here, when the received input voltage is higher than VsQ and therefore the output voltage of the detection circuit 8 is higher than VSO, the comparator 11
The output of the amplifier 5 becomes "1", and the output of the A, ND circuit 18 is also "1" and the output voltage of the amplifier 5 is cut off.

7′\−7 また、受信入力電圧がvlIQより小さく、従って検波
回路8の出力電圧がV B Qより小さいときは、比較
器11の出力は「0」となり、A、 N D回路18の
出力は「0」となって、増幅器5の出力電圧を接にする
7'\-7 Also, when the received input voltage is smaller than vlIQ and therefore the output voltage of the detection circuit 8 is smaller than VBQ, the output of the comparator 11 becomes "0", and the output of the A, N D circuit 18 becomes "0", making the output voltage of the amplifier 5 a contact.

このように、スケルチボリー−ムの電圧(vSQ)をデ
ジタルスケルチの設定電圧より小さくしておくと、デジ
タルスケルチ回路の判定に関係々くなり、ノイズスケル
チのみの判定で増幅器5の出力が接、断される。
In this way, if the squelch volume voltage (vSQ) is made smaller than the digital squelch setting voltage, it will be unrelated to the judgment of the digital squelch circuit, and if only the noise squelch is judged, the output of the amplifier 5 will be connected. Cut off.

(2)  Vo > VSQの場合 すなわち、スケルチボリューム13がデジタルスケルチ
回路の判定限界より太き(’(−3dBμV〜QdBμ
V)設定されていると、比較器14の出力は常にIll
であり、OR回路17の出力はデジタルスケルチ回路1
0の出力に左右される。所定のデジタル信号方式になっ
ていると、デジタルスケルチ回路10は「1」なので、
OR回路17の出力も「1」となり、所定のデジタル信
号方式になっていないとデジタルスケルチ回路10はr
OJなので、OR回路17の出力も「0」となる。
(2) When Vo > VSQ, that is, the squelch volume 13 is thicker than the judgment limit of the digital squelch circuit ('(-3dBμV~QdBμ
V) If set, the output of comparator 14 will always be Ill
The output of the OR circuit 17 is the output of the digital squelch circuit 1.
It depends on the output of 0. If the specified digital signal system is used, the digital squelch circuit 10 is "1", so
The output of the OR circuit 17 also becomes "1", and if the predetermined digital signal system is not used, the digital squelch circuit 10 will
Since it is OJ, the output of the OR circuit 17 is also "0".

ここで、受信入力電圧がvSQより大きく、従って検波
回路8の出力電圧がVsQより大きいときは、比較器1
1の出力は「】」となり、OR回路17の出力に関係な
(、AND回路]8の出力が「1」となり、増幅器5の
出力電圧を断にする。
Here, when the received input voltage is larger than vSQ and therefore the output voltage of the detection circuit 8 is larger than VsQ, the comparator 1
The output of 1 becomes "]", and the output of the AND circuit 8, which is related to the output of the OR circuit 17, becomes "1", and the output voltage of the amplifier 5 is turned off.

まだ、受信入力電圧がv、Qより小さく、従って検波回
路8の出力電圧が■、Qより小さいときは、比較器11
の出力は[0−1となる。A、 N D回路18の11
−1カはOR1回路17の出力に左右されるデジタルス
ケルチ回路10の出力が「0」のときは、増幅器5の出
力電圧を接とし、デジタルスケルチ回路10の出力が「
1」のときは増幅器5の出力電圧を断とする。
When the receiving input voltage is still smaller than v, Q, and therefore the output voltage of the detection circuit 8 is smaller than ■, Q, the comparator 11
The output of becomes [0-1. A, 11 of ND circuit 18
-1 is influenced by the output of the OR1 circuit 17. When the output of the digital squelch circuit 10 is "0", the output voltage of the amplifier 5 is connected, and the output of the digital squelch circuit 10 is "0".
1, the output voltage of the amplifier 5 is cut off.

このように、スケルチボリュームの電圧(V、Q)をデ
ジタルスケルチの設定電圧より大きくしておくと、デジ
タルスケルチ回路の判定およびノイズスケルチの判定の
双方の判定が良いとき、増幅器5の出力が接となる。
In this way, if the squelch volume voltage (V, Q) is set higher than the digital squelch setting voltage, the output of the amplifier 5 will be connected when both the digital squelch circuit judgment and the noise squelch judgment are good. becomes.

発明の効果 9 ・、−7 本発明は、上記実施例から明らかなように、ス)1 ル
チホIJ、−ムの設定がデジタルスヶルチノ判定限界以
下のときは、ノイズスケルチ回路のみの判定で増幅器の
接、断を行ない、スケルチボIJ。
Effects of the Invention 9 ・, -7 As is clear from the above embodiments, the present invention has the following advantages: (1) When the setting of the luciphon IJ, - is below the digital squelch noise judgment limit, only the noise squelch circuit can be used for judgment. Connect/disconnect the amplifier and squelchivo IJ.

−ムの設定がデジタルスケルチの判定限界以上のときは
、ノイズスケルチ回路の判定とデジタルスケルチ回路の
判定の双方の判定で増幅器の接、断を行なうよう構成し
だので、デジタルスケルチ回路が動作する受信入力であ
ってもノイズスケルチ範囲内のときは音声出力が接続さ
れるという効果を有する。
- When the system setting exceeds the digital squelch judgment limit, the amplifier is connected or disconnected based on both the noise squelch circuit judgment and the digital squelch circuit judgment, so the digital squelch circuit operates. This has the effect that even if the reception input is within the noise squelch range, the audio output is connected.

【図面の簡単な説明】[Brief explanation of the drawing]

復調回路、5・・・増幅器、7・・・高域フィルタ、8
・・検波回路、9・・雑音制御装置、10・デジタルス
ケルチ回路、11・・・比較器、12,15.16・抵
抗、13・・・スケルチボリー−ム、14・・比較器、
17・・・OR回路、18−・A N D回路。
Demodulation circuit, 5... Amplifier, 7... High-pass filter, 8
...Detection circuit, 9.Noise control device, 10.Digital squelch circuit, 11.Comparator, 12, 15.16.Resistor, 13.Squelch volume, 14.Comparator,
17-OR circuit, 18-AAND circuit.

Claims (1)

【特許請求の範囲】[Claims] スケルチボリュームにより電圧が可変するスケルチ電圧
およびノイズの量により出力電圧が変化するノイズ電圧
の電圧の大小を比較する第1の比較器と、上記スケルチ
ボリュームにより電圧が可変する上記スケルチ電圧およ
び所定の電圧とを比較する第2の比較器と、この第2の
比較器の出力および、復調信号が所定のデジタル信号方
式になっているかを判定するデジタルスケルチ回路の出
力とを入力するOR回路と、このOR回路の出力および
、上記第1の比較器の出力とを入力するAND回路とを
具備し、このAND回路の出力で増幅器の出力を接、断
するスケルチ装置。
a first comparator that compares the magnitude of a squelch voltage whose voltage is varied by a squelch volume and a noise voltage whose output voltage changes depending on the amount of noise; and the squelch voltage whose voltage is varied by the squelch volume and a predetermined voltage. an OR circuit that inputs the output of the second comparator and the output of a digital squelch circuit that determines whether the demodulated signal is in a predetermined digital signal format; A squelch device comprising an AND circuit inputting the output of the OR circuit and the output of the first comparator, the output of the AND circuit connecting or disconnecting the output of the amplifier.
JP17065284A 1984-08-16 1984-08-16 Squelch device Granted JPS6148238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17065284A JPS6148238A (en) 1984-08-16 1984-08-16 Squelch device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17065284A JPS6148238A (en) 1984-08-16 1984-08-16 Squelch device

Publications (2)

Publication Number Publication Date
JPS6148238A true JPS6148238A (en) 1986-03-08
JPS6355253B2 JPS6355253B2 (en) 1988-11-01

Family

ID=15908847

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17065284A Granted JPS6148238A (en) 1984-08-16 1984-08-16 Squelch device

Country Status (1)

Country Link
JP (1) JPS6148238A (en)

Also Published As

Publication number Publication date
JPS6355253B2 (en) 1988-11-01

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