JPS6147045B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a protective relay system for polyphase AC transmission lines having inherent redundancy that is reliable and provides its own "backup" protection.

PRIOR TECHNOLOGY A phase comparison type carrier protection relay device is used to protect power transmission lines in trunk systems, but this relay device transmits the polarity of the current at its own end and the other end through power line carriers or microwave circuits. This is used to determine whether a fault is within the protected section or not, and is usually installed for each phase. If so, the polarities of the currents at both terminal stations will be in the same phase or close to it, and the phase comparison relay will operate unnecessarily. In addition, in systems with large power transmission power, there is always a large power flow, and even if a fault occurs within the protected section, if it is a so-called micro-ground fault with high grounding resistance, each phase current at both terminal stations will be affected by the power flow. It may be difficult to detect internal failures.

DISCLOSURE OF THE INVENTION The present invention provides a protection relay device that eliminates the disadvantages of the conventional phase comparison type transport protection relay device as described above and has redundancy.

That is, in order to protect the multiphase AC power transmission line, the present invention provides an OR circuit having an output terminal connected to all of the circuits and disconnectors provided for each phase conductor of the multiphase AC power transmission line. a circuit breaker actuation network for simultaneously activating said circuit breaker and disconnectors; and an output conductor individually connected to each input terminal of said OR circuit in said circuit breaker actuation network. and a circuit and disconnection control network for each phase and zero phase connected to each phase conductor individually or to all phase conductors, and the circuit for each phase The disconnection control circuit network includes a fault detector that detects a fault based on a change in phase current supplied from both terminal stations of the multiphase AC transmission line to each phase conductor, and a fault detector that is connected to the fault detector and detects a previous fault. A transceiver transmits a warning signal to the other end when no failure is detected and receives the alarm signal from the other end, and compares the phase of the positive half wave of the current at its own end and the current at the other end from the transceiver. a first AND circuit that compares the phase of the negative half wave of the current at its own end and the current at the other end, and a second AND circuit that is connected to these AND circuits via an OR circuit, and a third AND circuit connected to the transceiver and the transceiver, which is locked and does not operate when the fault is not detected and therefore receiving the warning signal from the other end, but when the fault is detected. a phase comparison determiner which is activated when the warning signal is not received from the other end, thereby supplying a signal from the third AND circuit to the output conductor for activating the circuit switch or disconnector; including;
The zero-phase circuit and breaker control network detects a grounding current exceeding a set value as a fault current.
connected to _{the L} overcurrent circuit and this I _L overcurrent circuit,
a transceiver that transmits a warning signal to the other end and receives the alarm signal from the other end when the fault current is not detected; a first AND circuit for comparing phases, a second AND circuit for comparing phases of negative half waves of the self-end current and the opposite-end current, and a second AND circuit connected to these AND circuits via an OR circuit; It has an I _L overcurrent circuit and a third AND circuit connected to the transceiver, and is locked and does not operate when the fault current is not detected and therefore the warning signal is being received from the other end. , is activated when said fault current is detected and therefore does not receive said warning signal from said counterpart, thereby providing a signal from said third AND circuit to said output conductor for activating said circuit disconnector. A protective relay device comprising: a phase comparison determiner;

Purpose of the Invention Therefore, the present invention relates to a phase comparison type carrier protection relay device that compares the polarity of the amount of electricity between both ends of a power system to determine whether a system failure is within the protected system. The phase comparison type carrier protection relay device for each phase has the disadvantage that it cannot detect ground faults where the fault current is small compared to the power flow when applied to a system with a large power flow. Focusing on zero-sequence currents that occur independently, phase comparison using zero-sequence currents is performed using a conventional phase comparison type carrier protection relay device [This device is a phase comparison type carrier protection relay device for each phase]. This device is used for each phase (phase A, B, C) of the power transmission line.
The current phase at both ends of the transmission line is compared at each time to distinguish between internal and external failures. Therefore, it is necessary to reduce the detection sensitivity so as not to malfunction due to the charging current, and there is a limit that it cannot detect minute fault currents (microground fault currents). Additionally, in the event of a failure under heavy tidal currents, the tidal current would flow out, making it impossible to operate. ] In addition to the conventional circuit network that trips circuits and breakers by comparing the phases of each phase, the present invention provides a circuit network that trips circuits and breakers for all three phases by the operation of a zero-phase phase comparison circuit. It is composed of When applying the conventional method of tripping the circuit or disconnection for each phase in the phase comparison of each phase,
Because the zero-phase phase comparison causes a time-limited trip (in addition to being able to trip by the zero-phase phase comparison when a slight ground fault occurs), even if each phase phase comparison circuit is defective and cannot operate in a normal failure case, the zero-phase phase comparison Since it can respond to failures in any phase, it is possible to back up failures in phase comparison of each phase and trip circuits or breakers. ], it is an object of the present invention to provide a highly reliable protective relay device that eliminates the above-mentioned inconveniences and has a back-up protection function. The electrical quantity handled by the zero-phase phase comparison is the zero-sequence current, which becomes zero for three-phase balanced inputs such as tidal currents and charging currents, and is derived only for ground fault currents. It is quantity. Therefore, it is possible to detect a ground fault with high sensitivity without being affected by the above-mentioned problems of phase comparison of each phase. In other words, it is effective against slight ground faults.

EMBODIMENTS OF THE INVENTION The invention will become more easily apparent from the following illustrative description with reference to the accompanying drawings, in which: FIG.

Overall protective relay device (FIG. 1) In FIG. 1, phase buses 1, 2 and 3 of a three-phase power supply system are suitably energized from a power source (not shown). The phase conductors 4, 5, 6 of the three-phase transmission line are connected from the phase buses 1, 2, 3 to the low-pass filter 7, respectively.
8, 9 and circuit breakers 10, 11, 12. Low pass filters 7, 8 and 9
presents virtually no impedance to the transmission current at the transmission power frequency, but to the current at the power line carrier frequency transmitted through the phase conductors 4, 5 and 6 between the ends of the protected transmission line section. Exhibits high impedance.

Current transformers 13, 14, 15 are combined with phase conductors 4, 5, 6, respectively, and phase conductors 4, 5, 6
provides an output quantity that is directly related to the current flowing through the
The outputs of current transformers 13, 14 and 15 are applied in the usual manner to the primary windings of isolation current transformers 16, 17, 18 and 19. That is, isolation current transformer 1
The output quantities of 6, 17, and 18 are the phase conductors 4 and 18, respectively.
5, 6 and represents the current flowing through the isolating current transformer 1
The output amount of 9 is a measure of the residual current, that is, the ground current. 2 of each isolation current transformer 16, 17, 18, 19
Each secondary winding is connected to individually energize a load resistor. This is so that the output quantities supplied to the phase current responsive relay networks 20, 21 and 22 and the ground current responsive relay network 23 are voltage signals. The relay networks or circuit disconnection control networks 20, 21, 22, 23 are provided with output conductors 25, 26, 27, 28, respectively. These output conductors provide a logic zero signal that is normally deenergized, but can be energized in response to activation of a fault detector or I _L overcurrent circuit, as discussed in more detail below with respect to FIG. When this occurs, a logical value 1 signal is output. A further output conductor 29 is provided in the ground current responsive relay network 23 . This output conductor 29 normally provides a logic zero signal, but is always a logic zero signal whenever the magnitude of the ground current is greater than a predetermined minimum value, regardless of the relative behavior of the ground current at the other end of the protected transmission line section. Gives a value 1 signal.

The circuit breaker trip circuit network, that is, the circuit breaker activation circuit network 24 includes a plurality of OR circuits 34,
36 and 38, an AND circuit 40, and a timer circuit 42. The OR circuit 34 has four input terminals connected to the output conductors 25, 26, 27, 28, respectively.
, and its only output terminal is connected to one input terminal of a two-input OR circuit 36. The AND circuit 40 has its three input terminals connected to the output conductors 25, 26, and 27, respectively, and its only output terminal connected to one input terminal of the two-input OR circuit 38. Timing circuit 42 provides a time delay between the activation of its input terminal by output conductor 29 and the activation of its output terminal (connected to the other input terminal of OR circuit 38). Timing circuit 42 may have a time delay of, for example, 0.2 to 2.0 seconds. This time interval is significantly longer than any time interval required for relay networks 20-23 to trip a circuit or disconnect in response to activation of a fault detector or I _L overcurrent circuit. The logical value 1 signal is one of the OR circuits 34
When supplied to one input terminal or two or more input terminals, the OR circuit 34 outputs a logic 1 signal to the OR circuit 3.
6, and then this OR circuit 36 outputs a logic value of 1.
The trip signal is connected to all circuits and disconnectors 10 to 12.
supply to Similarly, OR circuit 36, when supplied with a logic one signal from AND circuit 40 or timer circuit 42, may provide a logic one signal to trip circuit disconnectors 10-12.

Relay networks 20, 21, 22 and 23 are coupled to phase conductors 4, 5 and 6 via output conductors 44, 45, 46 and 47 and coupling capacitors 48, 49 and 50. Relay circuit network 20~
23 each transmit and receive information signals at the power line carrier frequency with a relay network (similar to relay networks 20-23) located at and coupled to the other end of the protected power line section. FIG. 1 shows only the relay networks 20 to 23 at their own ends of the protected transmission line section.

Although the transmission of information between the other end and the own end is described in this invention as occurring on a power line carrier frequency, other means such as microwave lines or dedicated telephone lines may be used to send the information. The particular form of transmission is not important as long as the appropriate information is sent.

Relay Network (FIG. 2) To simplify the drawing, only one relay network 52 is shown in FIG. This relay network 52 can be used for the phase current responsive relay networks 20-22, and also for the ground current responsive relay network 23. When used as a phase current responsive relay network, switch SW1 is placed in the position shown and uses its arming signal to activate phase comparison determiner 56 with fault detector 58 detecting changes in current. It is connected to input terminal 54. When used as a ground current responsive relay network, switch SW1 is placed in another position since it cannot be expected to act as a fault detector to detect changes in current.

The relay network 52 is supplied with a current derivation signal through an isolation current transformer 61 . The isolation current transformer 61 is
Isolating current transformer 16, 17, 18 or 19 of FIG.
corresponds to The isolation current transformer 61 is provided with a load resistance, and the output buses 62 and 63 pass the voltage signal to the _IH overcurrent circuit 64, the _IL overcurrent circuit 60, the fault detector 58, and the frequency verifier. 6
5. Supplies to circuit breaker open circuit detector 66 and square wave generator 67. The square wave generator 67 is provided with three output terminals 68, 69, 70 for receiving square wave signals I _SWP , I _SWN , I _SW of the same frequency as that supplied by the output buses 62 and 63. Send each. The rectangular wave signal I _SW is an output signal having a positive rectangular wave portion, as will be described later. The positive square wave portion is in phase with the voltage signal input to the square wave generator 67 and has a length or pulse width substantially equal to a positive half cycle of the voltage signal. The rectangular wave signal I _SW is supplied to the input terminal 71 of the transmission signal control circuit 72, and pulsates into a logic 1 signal and a logic 0 signal in synchronization with the rectangular wave signal I _SW , as will be explained in detail below. Output terminal 73 with signal
to support. This pulsating signal is supplied to the input terminal 73A of the transmitter frequency controller 76.

In a normal, no-fault condition, a logical 1 signal is provided from the output terminal 74 of the transmit signal control circuit 72 to the input terminal 74A of the transmitter frequency controller 76, as will be explained in detail below. As shown in Figure 8,
The transmitter frequency controller 76 includes two AND circuits 7
5 and 75A. The input terminal 74A is connected to the inverting input terminal of two AND circuits, that is, the not input terminal, and the output terminal 77, whereas the input terminal 73A is connected to the other inverting input terminal of the AND circuit 75, and the non-inverting input terminal of the AND circuit 75A, that is, the output terminal 77. Connected to normal input terminal. The output side of AND circuit 75 is connected to output terminal 79, while the output side of AND circuit 75A is connected to output terminal 80.

The transmitting section of the transceiver 78 determines which of the three input terminals 77A, 79A or 80A has a logic value of 1.
It can be of any type that transmits a signal at one of three frequencies depending on whether it is energized with a signal. As can be seen from FIGS. 8 and 2, whenever input terminal 74A of transmitter frequency controller 76 is energized with a logic 1 signal, output terminal 77 and
The transceiver input terminal 77A connected to 7 is also energized with a logic 1 signal. However, output terminal 7
9 and 80 and input terminals 79A and 80A
The AND circuits 75 and 75 are activated regardless of whether the input terminal 73A is energized with a logical 1 signal or a 0 signal.
Since A remains closed, it will be energized with a logic zero signal. Under normal, no-fault conditions, the logical value is 1.
Signals are present at output terminal 74, input terminal 74A, output terminal 77, and input terminal 77A, and the transmitting section of transceiver 78 transmits a logic 1 alarm signal to the other end. This warning signal is generated by the phase comparison determiner 5 unless due to a large overcurrent, such as that detected by the _IH overcurrent circuit, as will be explained in detail below.
Prevent 6 from tripping. Fault detector 58
When a fault occurs as indicated by , that is, when the fault detector 58 generates a logic 1 signal, and if the circuit breaker open circuit detector 66 outputs a logic 1 signal. , output terminal 74 is energized with a logic zero signal. When this occurs, the rectangular waveform signal I _SW is output to input/output terminal sets 79-79A and 80-
80A and outputs a logic value 1 signal and a logic value 0 signal alternately, resulting in a trip plus (i.e. positive)
Frequency and trip minus (ie negative) frequency and supply.

Preferably, the frequency of the warning signal is outside the range of the trip signal frequencies, and also desirably lower than any of the trip signal frequencies. Further, the warning signal and the trip signal may be coded signals of one or more frequencies. What is important is to provide appropriate information to the receiving station so that the transmitted and received frequency or coded signals are determined by the conditions at the transmitting station. The variations in the trip-plus and trip-minus frequencies provide the receiver at the other end with an accurate indication of the voltage signal applied to the output buses 62 and 63. Similarly, when a failure occurs in the fault detector at the other end, the transmitting section at the other end sends a signal RI _SW to the transceiver 78 at the other end, instructing the current to energize the relay network at the other end. . This signal RI _SW is supplied from the receiving section of the transceiver 78 and applied to the input terminal 82 of the phase comparison determiner 56 through a conductor 81 . As shown in FIG. 3, the signal RI _SW applied to the input terminal 82 is applied to the non-inverting input terminal of the AND circuit 82A and the inverting input terminal of the AND circuit 82B. As will be explained in more detail below, the signal RI _SW is transmitted from the square wave generator 67 through the delay timer 84 to the input terminals 85, 86 of the phase comparison determiner 56 and to the AND circuit 82A, respectively.
It is compared with the rectangular wave signals I _SWP and I _SWN supplied to the non-inverting input terminal of 82B. The output terminals of AND circuits 82A and 82B are connected to input terminal 87 of AND circuit 110 via OR circuit 86A.

The delay timer 84 delays the rectangular wave signal supplied from the rectangular wave generator 67 for a time equal to the time required for the transmission amount from the opposite end to be received by the transceiver 78 at the own end. If the signal RI _SW and the square wave signals I _SWP and I _SWN are connected to AND circuits 82A and 8
As a result of the comparison in 2B, if it is found that the currents at the other end and the own end flow into or out of the protected transmission line section at the same time, the phase comparison is determined. Vessel 5
6 is the output terminal 88 (full arming of the AND circuit 110 as explained later).
arming) to start delay circuit 90 having a delay time of 4 milliseconds. After this delay time has elapsed, the delay circuit 90 energizes the input terminal 92 of the trip board 94.

When this input terminal 92 is energized, the I _L overcurrent circuit 60
is a logical value of 1 to the input terminal 95 of the trip board 94.
If the signal is being supplied, trip board 9
4 energizes its output terminals 96 and 97. Output terminal 96 energizes one output conductor 25, 26, 27 or 28, depending on whether relay network 52 is phase current responsive or ground current responsive. As previously mentioned, when one input circuit to the circuit disconnector trip network 24 is energized in this manner, in the configuration shown in FIG. 12 will be tripped. However, if the phase relationship between the signal RI _SW and the square wave signals I _SWP and I _SWN indicates that there is no fault within the protected transmission line section between the own end and the other end, but there is an external fault. , the phase comparator 56 does not energize the output terminal 88, and therefore the circuitry and disconnect trip circuitry, even during the presence of its full arming amount.

When a warning signal is received at the receiving portion of transceiver 78, a logic one signal is provided by conductor 105 to input terminal 103 of phase comparison determiner 56 and input terminal 104 of channel monitor 106. Third
As shown in more detail in the figure, input terminal 103 energizes the inverting input terminal 108 of the safety circuit, which can take the form of an AND circuit 110 when energized with a logic 1 signal, to apply an arming signal. is removed and the output terminal 88 and circuit break trip network 24 are not energized.

Output terminal 96 of trip board 94 may be energized by a logic 1 signal from I _H overcurrent circuit 64 applied to input terminal 99, independent of phase comparison determiner 56. When input terminal 99 is energized with a logic 1 signal, OR circuit 112 supplies a logic 1 signal to AND circuit 114, as shown in FIG. In the assumed current state, the _IH overcurrent circuit 64 supplies the logic 1 signal to the input terminal 95 and thus the other input terminal of the AND circuit 114 at a current value smaller than the current value that supplies the logic 1 signal. The I _L overcurrent circuit 60 is set. When so energized, the AND circuit 114 provides a logical 1 signal to the delay circuit 116 to provide an appropriate delay (this includes an initial delay of 0.1 ms when activated and 20 ms when deactivated).
(indicated as a reset time in milliseconds)
Post-delay circuit 116 energizes output terminals 96 and 97. As mentioned above, this will trip the circuit disconnectors 10-12 and send a logic value of 1 to the input terminal 118 of the transmit signal control circuit 72.
It will supply the signal. This logic 1 signal, after a 10 millisecond delay, causes the transmit signal control circuit 72 to energize its output terminal 73 with a logic 1 signal and its output terminal 74 with a logic 0 signal. Transmitter frequency controller 76 causes transceiver 78 to transmit an information signal (indicative of the magnitude of square wave signal I _SW ) to the other end.

If excessive noise is present in the receiving section of transceiver 78, this excessive noise will energize conductor 119, which in turn energizes input terminal 120 of channel monitor 106 (detailed in FIG. 10). , either virtually instantaneously depending on the position of switch SW ₂ or after a delay provided by delay circuit 122.
A logical value 1 signal is supplied to 21. Delay circuit 122
has a time limit of 500 milliseconds and is reset virtually instantly. Output terminal 121 of channel monitor 106 provides a logic one signal to input terminal 123 of phase comparison determiner 56 when energized. Third
As shown in the figure, the input terminal 123, when energized, energizes the inverting input terminal 124 with a logical 1 signal, and removes the arming signal from the AND circuit 110, and the AND circuit 110 outputs the Do not energize terminal 88.

In case of transmission channel failure, the transceiver 7
The receiver at 8 is unable to maintain a logic 1 signal on conductor 125 and instead provides a logic 0 signal. Conductor 1
25 is connected to the input terminal 126 of the phase comparison determiner 56 and thus to the non-inverting input terminal 127 of the AND circuit 110, so that the arming signal is connected to the AND circuit 11.
0 and the phase comparison determiner cannot trip the circuit or disconnect.

The combined operation of channel monitor 106 and channel fault board 140 allows for localized tripping during the initial time of a channel fault. For this purpose, conductor 125 is also connected to an input terminal 128 of channel monitor 106, which in turn is connected to the inverting input terminal of OR circuit 132 and to one input terminal of AND circuit 129. Therefore, as soon as conductor 125 receives a logic 0 signal, OR circuit 132 sends a logic 1 signal to timing circuit 13.
4, and this timer circuit 134 starts a timer operation. The operating time of this timer circuit 134 may be 150 milliseconds. The logic value 0 signal at the input terminal 128 is passed through the AND circuit 129 to the AND circuit 1.
A logic 0 signal is supplied to the inverting input terminal of 30. This does not have any immediate effect, but in combination with the logic 1 signal that is provided later when the timer circuit 134 times out, the AND circuit 1
30 causes a logic one signal to be provided to the non-inverting input terminal of OR circuit 132 and causes OR circuit 132 to maintain timer circuit 134 in its timed out state.

The output terminal 135 of the channel monitor 106 is
As shown in FIG. 12, the input terminal 138 of a channel fault board or channel fault unblocking circuit 140 is connected to the inverting input terminal of an OR circuit 142. Normal channel operation and 10th
Before the timing circuit 134 of the figure times out, the logic 0 signal applied to the input terminal 138 is output to the OR circuit 134.
2 and the first arming signal to the AND circuit 146
be supplied to The second arming signal is an I _L overcurrent circuit 60 that supplies a logical 1 signal when a failure occurs.
is applied to the input terminal 153 and therefore the AND circuit 146.

The third arming signal is the warning signal supply conductor 1
05 to the AND circuit 14 through the input terminal 152.
It is supplied to the inverting input terminal of 6. Prior to loss of channel or loss of signal, it remains in a logic one state and AND circuit 146 is not armed. Channel loss and conductor 1
05 receives a logic 0 signal, a third arming signal is provided to the inverting input terminal of AND circuit 146, and AND circuit 146
8 to input terminal 145. This state ends when the time limit circuit 13
4 times out and a resultant logic 1 signal is provided to the inverting input terminal of OR circuit 142 to remove the previously provided first arming signal to AND circuit 146. The circuit break at its own end can then be tripped only by operation of the relay network 52 and thus the _IH overcurrent circuit 64.

When AND circuit 146 is fully armed and a fault occurs, a logic one signal from fault detector 58 causes AND circuit 146 to begin timing circuit 141 . When a timeout occurs, the timer circuit 141 energizes the output terminal 147 with a logic 1 signal. The output terminal 147 is connected to the trip board 94
is connected to an input terminal 148 of the OR circuit 112 and thus to one input terminal of the OR circuit 112. Therefore, the timer circuit 141
If it times out, it will trip the circuits and disconnectors 10-12 in the manner described above.

Channel monitor 106 is reset by conductors 105 and 12, respectively, from transceiver 78.
5 when a logic 1 signal is applied to the input terminals 104, 128. The logical value 1 signal applied to both input terminals of the AND circuit 129 causes the AND circuit 130 to remove the logical value 1 signal from the non-inverting input terminal of the OR circuit 132.
The logic value 1 signal to the inverting input terminal of is OR circuit 13
2 to logic 1 signal output and causes timer circuit 134 to time out at a 30 millisecond reset time interval. If normal transmission is maintained during this period, a logic zero signal will be present at output terminal 135 and input terminals 136 and 138. This reapplies to AND circuits 110 and 146 the arming signal that was removed due to the transmission channel failure.

The apparatus described above is particularly suitable for power line carrier channel transmission, where the channels can more easily fail during power line faults than with separate transmission channels such as microwave lines or dedicated telephone lines. Therefore, in some cases it may be desirable to omit channel failure board 140. As a result, it is clear that only the output signal from the channel fault board 140 is applied to the input terminal 148 of the trip board 94. The OR circuit 112 in the trip board 94 connects the input terminal 9
2 of the phase comparison determiner 56 and remains under the control of the I _H overcurrent circuit 64 at input terminal 99.

Under normal operating conditions, the circuits and disconnectors associated with the protected power line sections at both ends are closed and current flows through the protected power line sections. When there is no failure, each transmitter/receiver at the own end and the opposite end sends warning signals to the transmitter/receiver at the opposite end and the own end, respectively.
The transceiver at the other end responds to a fault signal from its associated fault detector and disables its associated phase comparison determiner. If a circuit or disconnector at one end is opened, a circuit or disconnector at the other end is closed, and a phase conductor fails, the fault detector in the relay network 52 at the other end determines the phase comparison. A logic value 1 signal is supplied to the AND circuit 110, but the input terminal 108 of the AND circuit 110 is energized by the logic value 1 alarm signal sent from its own end. As mentioned above, this
This is because the circuit or disconnector is open, so the own end cannot "see" the fault, that is, cannot detect the fault. The AND circuit 110 at the other end cannot energize its output terminal 88 in this condition, and if the fault current is not large enough to activate the I _H overcurrent circuit 64 in the relay network 52 at the other end. If the circuit at the other end is not opened, the fault current cannot be cut off. In short, the fault current is
When a current value that should not be exceeded, which will be described later, is exceeded, the _IH overcurrent circuit 64 is activated regardless of the phase comparison determiner 56.
This is good because the fault current can be tripped, but if the fault current is smaller than the current value that should not be exceeded, it cannot be tripped unless the phase comparison determiner 56 operates. If the own end does not detect a fault and therefore continues to send out a logical 1 warning signal, the phase comparison determiner at the other end will not operate and will therefore be unable to trip, which is a problem.

A circuit breaker open circuit detector 66 is provided in the relay network 52 to remove the warning signal and open the circuit breaker at the other end. This circuit break open circuit detector 66 detects a normal logic value of 1 at its output conductor 173 when the circuit break at its own end is opened.
The signal is removed and a logic zero signal is provided in its place. This logic 0 signal is supplied to the input terminal 174 of the transmit signal control circuit 72. As can be seen in FIG. 7, this logic 0 signal at the non-inverting input terminal of AND circuit 176 unarms AND circuit 176 and is normally applied from output terminal 74 to input terminal 74A of transmitter frequency controller 76. Logic 1 signals that are present are removed. As previously mentioned,
When the logical value 1 signal to the input terminal 74A is removed, the logical value 1 signal to the output terminal 77 is removed, and the AND circuits 75 and 75A alternately output the logical value 1 signal to the output terminals 79 and 80, respectively. Apply it.

Therefore, when the circuit or breaker at the own end opens, the warning signal to the other end is immediately cut off, and the insulating current transformer 6 at the own end
Since no current flows to energize 1, only AND circuit 75 acts to drive transceiver 78, and the trip-minus signal is continuously transmitted to relay network 52 at the other end. The trip minus signal at the other end is connected to the AND circuit 8 for phase comparison.
2A is opened, and in response to a fault signal from the fault detector 58 at the other end, the AND circuit 110 at the other end is opened.
open.

When the open circuit or disconnector is closed, the logic 1 signal is again supplied to the transmit signal control circuit 72 through the output conductor 173 and again to the AND circuit 176.
arm and establish retransmission of the warning signal. Output conductor 173 is also connected to input terminal 149 of channel fault board 140 and begins to apply a logic one signal to the input terminal of timer circuit 150 and the non-inverting input terminal of AND circuit 144. During 150 ms timed operation of timed circuit 150, timed circuit 1
50 supplies a logical value 0 signal to the inverting input terminal of the AND circuit 144. Therefore, for a period of 150 milliseconds after the start of closing the circuit breakers, the AND circuit 144 supplies a logical 1 signal to the OR circuit 142, thereby matching the signal supplied from the channel monitor 106 to the input terminal 138. arm the AND circuit 146 regardless. Therefore, channel failure board 140
is responsive to fault detector 58 and detects the absence of a signal provided by transceiver 78 and input terminal 13 from channel monitor 106 when the power line fails.
The presence of a logic 1 signal to 8 causes the trip board 94 to
A logical value 1 signal is supplied to the Note that due to loss of channel no alarm signal is received and a logic zero signal is provided to input terminal 138 to provide a third arming signal to the inverting input terminal of AND circuit 146.

A preferred form of square wave generator 67 is shown in FIG. 5 and has input terminals 154 and 155 connected to output buses 62 and 63, respectively.
These input terminals are connected to input terminals of a first operational amplifier 156, the output terminal of the first operational amplifier 156 is connected to energize a second operational amplifier 158, and the output terminal of the second operational amplifier 158 is connected to a transistor. 159 to terminal 160 to supply a square wave signal. This square wave signal is
Its length is substantially equal to and in phase with the negative half cycle of the voltage signal applied to input terminals 154 and 155. Terminal 160 is a 1-input OR circuit 161
, and its output side is connected to the output terminal 70. The conduction or non-conduction of the transistor 159 is determined by the OR circuit 161 and the output terminal 70.
are alternately energized with a logic 1 signal and a 0 signal (these drive the transmit signal control circuit 72), so that the logic 1 signal and 0 signal are alternately applied to the input of the transmitter frequency controller 76. The signal is now supplied to the terminal 73A. A second operational amplifier 158 drives transistor 159 at a much lower value than the voltage signal on output buses 62 and 63, so that logic 1 and 0 signals are approximately equal to the period of a half cycle of this voltage signal. Make it.

The first operational amplifier 156 is connected to drive a pair of transistors 159A and 159B, and alternately turns on these transistors in response to voltage changes in its output signal. Transistor 159A provides logical 0 and 1 signals to OR circuit 161A, which in turn causes output terminal 68 to provide logical 1 and 0 signals, which become the square wave signal I _SWP . transistor 159c
is transistor 1 by transistor 159B.
59A and is made conductive and non-conductive in the opposite phase, and drives the OR circuit 161B to output a logical value of 1 to the output terminal 69.
signal and 0 signal, which becomes a square wave signal I _SWN . OR circuit 161A and 161B
The length of the logical 1 signal is the length of the output bus 62 and 6
The duration may be slightly less than the positive and negative half cycles of the voltage signal at 3, but preferably no less than 87 DEG of the voltage across the output buses 62-63 at 60 hertz and 0.2 volts rms.

An open circuit break detector 66, shown in detail in FIG. 6, is actuated by a signal developed at terminal 160 of a square wave generator 67. For this purpose, the terminal 160 is connected by a conductor 162 to an input terminal 163 of the circuit breaker open circuit detector 66 . The circuit breaker open circuit detector 66 is connected to the terminal 160
Compare the time intervals between the logic 1 signal and the logic 0 signal. A logic 1 signal at terminal 160 occurs during the absence of positive potential pulses on output buses 62 and 63, and a logic 0 signal occurs during intervals between positive potential pulses. When energized at 60 hertz, the pulses are slightly longer than 8 milliseconds. If the positive pulse interval is significantly longer than 8 ms, e.g.
For 20 milliseconds, it can be assumed that the circuit breakers are opened and the isolation current transformers are deenergized. At 60 Hertz AC voltage, the timer circuit can be set to time out in 6 milliseconds. Therefore, as long as the 60 hertz voltage signal is maintained (which indicates that the circuit or disconnect is closed), each positive half cycle will time out the timed circuit and have a 20 ms timeout period. output conductor 17
3 to maintain a logic 1 signal. However, if the circuit or disconnect is open, the positive pulse will not time out at 6 milliseconds, the 20 millisecond timer will time out and a logic zero signal will be provided to output conductor 173.

More specifically, the circuit breaker open circuit detector 66 is a resistor-capacitor time limit circuit 1 as shown in FIG.
64 included. The timer circuit 164 is energized to timeout a sublimit interval of 6 milliseconds when transistor 165 is nonconducting and there is a logic one signal at terminal 160;
is reset virtually instantaneously when it is rendered conductive by a logic zero signal to input terminal 163. At the end of a predetermined time period, the capacitor in time circuit 164 is charged enough to break over Zener diode 166 and base current flows into transistor 167, causing it to conduct. Transistor 167 conducts, causing capacitor 168 to discharge through resistor 169, resulting in a timeout interval of 20 milliseconds. At the end of the 20 millisecond time interval, the potential of capacitor 168 will be less than the breakover voltage of Zener diode 170 and no base current will flow to transistor 171. When transistor 171 becomes nonconductive, the potential at output terminal 172 goes from virtually zero volts to 15 volts, providing a logic zero circuit or disconnection open signal. When the circuit or disconnect is closed, the capacitor 168 is periodically charged and maintained at a potential higher than that required to break over the Zener diode 170, so that the transistor 171 is closed or disconnected. Continues to conduct as long as it is closed.

The frequency detector blocking circuit 192 does not arm the AND circuit 110 and acts to prevent circuit breakers from tripping due to high frequency transient currents flowing through the current transformer. Frequency detector 65 filters the low frequency offset in the output of the current transformer and supplies the superimposed AC signal to frequency detector blocking circuit 192. For this,
The frequency detector 65 includes a high-pass filter consisting of a first operational amplifier 186 and a second operational amplifier 187, as shown in FIG. The output of the second operational amplifier 187 is connected to control the conductivity of a first transistor 188, which in turn controls a second transistor 189. Frequency detector 65
The middle high-pass filter filters out any low frequency offset or DC offset that may be present in the output of the isolation current transformer 61 and provides an output signal at the output terminal 190 each time the filtered signal goes positive. do. It will be appreciated that this output signal is substantially synchronous with the filtered signal to be a substantially square wave, and whether it is in phase or out of phase is of no practical importance. During normal operation, severe DC or low frequency offsets and high frequency transients are usually not present, but they can occur, for example, when a fault occurs or after a circuit or disconnection is re-energized. An output terminal 190 of the frequency detector 65 is connected to an input terminal 191 of a frequency detector blocking circuit 192 as shown in FIG. is made conductive, and conversely, a logic value 0 signal makes it non-conductive. Each time transistor 193 changes its conduction state, one input terminal of AND circuit 194 is momentarily placed in a logic 0 state, and the inverting output terminal of AND circuit 194 momentarily flip-flops a logic 1 signal. 196, one input terminal 197 of an AND circuit 198, and an inverting input terminal of a timer 200.
Each time a logical 1 signal is applied to the S input terminal of flip-flop 196, flip-flop 196
changes state and provides a logic 1 signal to the other input terminal 204 of AND circuit 198 through a 20 microsecond timer 202. This is AND circuit 19
8 output terminal 205 to flip-flop 206
A logic value 1 signal is supplied to the S input terminal of the terminal. This causes flip-flop 206 to change state so that flip-flop 206 provides a logic one signal to its one output terminal and thus to the input terminal of timer 208. Immediately after the change of state of transistor 193, logic 1 signals are again present at both input terminals of AND circuit 194. When this occurs, the inverting output terminal of AND circuit 194 provides a logic 0 signal to the inverting input terminal 199 of timer 200, which is activated 5 milliseconds after the logic 0 signal is applied to its inverting input terminal 199. Start timing out the desired timed period, which can be . timer 200
provides a logic 1 signal at its output terminal when it times out. This output terminal is connected to the R input terminals of flip-flops 196 and 206. If this occurs before the next zero crossing reset of the AC voltage signals on output buses 62 and 63, the logic 1 signal from timer 200 resets flip-flop 196. In this state, successive zero crossings merely cause flip-flop 196 to change state without activating flip-flop 206. It is AND circuit 1
98 always sends a logic 0 signal to the flip-flop 20
This is because flip-flop 206 continuously maintains a logic zero signal to timer 208. Then timer 20
8 times out and is left providing a logic zero signal to output terminal 210. This output terminal 210 is connected by a conductor 211 to an input terminal 212 of the phase comparison determiner 56 . As can be seen from FIG. 3, this input terminal 212 is connected to the inverting input terminal 213 of the AND circuit 110. Therefore, as long as timer 208 remains timed out and continues to provide a logic zero signal, the arming signal will remain at inverting input terminal 213.

However, if a second state change occurs before the time interval of timer 200 indicating a higher frequency, AND circuit 194 momentarily connects inverting input terminal 199 of timer 200 to input terminal 197 of AND circuit 198. Applying a logic value 1 signal,
Flip-flop 196 is still set and provides a logic one signal to input terminal 204 of AND circuit 198. This is AND circuit 198
causes a logic one signal to be provided to the S input terminal of flip-flop 206, causing flip-flop 206 to change state and provide a logic one signal to timer 208. This timer 208 does not have any timeout period, so a logical 1 signal immediately appears at the input terminal 210, so that the arming signal that was being applied to the inverting input terminal 213 of the AND circuit 110 is removed and the This prevents the phase comparison determiner 56 from tripping the circuit or disconnect. This logical 1 signal is the timer 2
until a low frequency signal with a frequency equal to or greater than the delay setting of 00 appears again.
continue. When set to 5 milliseconds, this threshold frequency is approximately 100 hertz.

Timer 200 is instantaneously reset by a logic one signal applied to its inverting input terminal. When a logic zero signal is again applied to the inverting input terminal, timer 200 restarts its 6 millisecond time interval. 20 microsecond timer 202
is the operating time of flip-flop 196, and
Logic value 1 due to state change of transistor 193
A delay is provided during the transmission of the logical 1 signal from AND circuit 194 that is longer than the time interval at which the signal is provided from AND circuit 194 . Therefore, if timer 200 were not able to reset flip-flop 196, the instantaneous logic 1 signal of AND circuit 194 would cause AND circuit 198 to be disabled.

A preferred form of fault detector 58 is shown in block diagram form in FIG. This fault detector 58 detects sudden discontinuities in the AC waveform and is described in detail in U.S. Pat. No. 3,654,516. Basically, the fault detector 58 comprises a differentiator and an integrator. The integrator integrates ω ²
(so ω is equal to 2πf). As described in the above patent specification, the weighted integral quantity is added to the differential quantity. When the waveform suddenly changes due to a sudden change in the applied alternating current, the weighted integral and derivative quantities are no longer equal, and the adder supplies the output quantity to the transient detector, which then A logic 1 signal is supplied to delay circuit 58A.

A variation of the fault detector 290 is shown in FIG. 19 and may be replaced by the current varying fault detector 58 under conditions where the current value is of primary importance. Fault detector 290 is used in rare cases where power lines are very long or have high source impedance that can vary wildly (the first few of a multi-unit remote power plant).
It is particularly desirable to allow sensitive overcurrent arming (such as during 2000), where arming can occur at different current levels. In the case of relatively low-level fault currents where the fault current does not need to be immediately disconnected as in the case of high-level fault currents, the low-level fault current section of the fault detector is A delay is provided to trip at such a low level only after it has existed for a time interval. As shown in FIG. 19, the fault detector 290 has three fault detection circuits, each of which is connected to a potentiometer 294, 294A, 294B connected between an input bus 291 and a common negative DC bus 292.
or resistors, respectively. Each fault detection circuit is
Transistors 293, 293A, 2 connected between the direct current bus 294 and the common negative DC bus 292
93B respectively. The base of transistor 293 is connected to the movable arm of potentiometer 294 via Zener diode 295. This movable arm is adjusted to determine the amount of input that causes Zener diode 295 to break over and transistor 293 to conduct. Similarly, potentiometers 294A and 294B control the amount of input that causes Zener diodes 295A and 295B to break over and transistors 293A and 293B to conduct, respectively.

The fault detector 290 has a plurality of input terminals 29
8,299 and 300 and one output terminal 3
includes an OR circuit 297 having a value of 01; The voltages generated across the emitter resistors of transistors 293, 293A, and 293B are applied to input terminals 298, 299, and 300, respectively. A delay is associated with a connection to each input terminal 298,299. As shown, the delay circuits include AND circuits 302 and 302A whose output terminals are directly and individually connected to input terminals 298 and 299, respectively, of an OR circuit 297.
including. Each of these AND circuits has a non-inverting input terminal and an inverting input terminal. The inverting input terminals of the AND circuits 302 and 302A are connected to the transistor 2 via delay circuits 303 and 303A, respectively.
Connected to the emitter of 93,293A. The non-inverting input terminals of AND circuits 302 and 302A are also connected to the emitters of transistors 293 and 293A, respectively. When the transistors 293 and 293A are conductive, the logic value 1 signal is output to the AND circuit 302,
A delayed logic 1 signal applied to the non-inverting input terminal of 302A (the delay duration of which is determined by delay circuits 303, 303A) is applied to the inverting input terminal of the AND circuit. delay circuit
As soon as the 200 millisecond time interval times out, the logic 1 signal output of the AND circuit disappears. If the phase comparison signal does not indicate an internal fault during the delay period, the arming signal due to conduction of transistors 293, 293A disappears, and as with the 10 ms reset time interval of delay circuits 303, 303A. It will reappear if the input quantity becomes smaller and does not render transistors 293, 293A non-conductive. When transistor 293B conducts, input terminal 300 remains at a logic value of 1 because there is no delay circuit, and output terminal 301 receives a logic value of 1 as long as the current level is high enough to maintain transistor 293B in a conductive state. Maintain arming signal.

A suitable delay timer 84 is shown in block diagram form in FIG. The delay timer 84 includes a pair of shift registers 430 and 430A, which may be, for example, 100 bit registers. Variable frequency clock circuit 432 and clock driver 4
34 provides the φ ₁ and φ ₂ signals for driving the shift register. Square wave generator 67
The square wave signal I _SWP from the output terminal 68 of is input to the input terminal of shift register 430, while the square wave signal I _SWN is input to the input terminal of shift register 430A. The shift register samples its input at the clock frequency, and each time a new sample is taken by the shift register, the previous sample is shifted toward the output terminal. The square wave signal outputs I _SWPD and I _SWND are replicas of the square wave signal inputs I _SWP and I _SWN , respectively, but the sampling is performed by a shift register, respectively.
It is delayed by the time interval required to be shifted 100 bits. The shift register may be similar to, for example, a dual 100-bit shift register TMS3003LR manufactured by Texas Instruments.

The clock frequency is the square wave signal I _SWPD , I _SWND
should always be at a high frequency with respect to the square wave signals I _SWP and I _SWN in order to maintain them as delayed signals of the square wave signals I _SWP and I _SWN , respectively. The clock frequency is variable to provide the required delay as described above.

A suitable overcurrent circuit 450 for use as I _L overcurrent circuit 60 and I _H overcurrent circuit 64 is shown in FIG. The overcurrent circuit 450 has a pair of input terminals 451 and 452 energized by voltage signals on output buses 62 and 63, which input terminals are connected via conventional circuitry to a first
It is connected to the input terminal of operational amplifier 454. The output of this first operational amplifier 454 is transmitted to the second operational amplifier 4.
56. The output of the second operational amplifier 456 is supplied to one input terminal of a polyphase rectifier 460, a third operational amplifier 462, and a fourth operational amplifier 463. These third operational amplifier 462 and fourth operational amplifier 463 have input terminals 464 and 46, respectively.
5. The phase shift output amount is supplied to 5. The input circuit of the third operational amplifier 462 causes the third operational amplifier to shift the input voltage by 60° so that its output voltage lags its input voltage by 120°. Insert voltage. The input circuit includes a second operational amplifier 456 and a third operational amplifier 456.
A fourth operational amplifier 463 is controlled to add the output voltages of the operational amplifier 462, and this fourth operational amplifier inserts this added sum voltage. Therefore, the output voltage of the fourth operational amplifier is the same as that of the second operational amplifier 462.
The phase is shifted to advance the input voltage at the output side by 120°.

The rectified output of polyphase rectifier 460 is applied across a series circuit consisting of potentiometer 466 connected to the positive output terminal and resistor 476 connected to the negative output terminal. A movable arm of potentiometer 466 is connected to the base of transistor 468;
Its emitter is connected via an emitter resistor 469 to a common connection between resistor 476 and the negative output terminal.
Diode 470 isolates the negative output terminal of polyphase rectifier 460 from ground bus 471 .

A voltage divider circuit consisting of resistors 469 and 471 is connected between the +15 volt DC bus and the 0 volt DC bus to maintain the emitter potential of the transistor at a desired potential higher than the potential of ground bus 471. A transistor 46 such that the potential of the movable arm of the potentiometer 466 is determined by the voltage divider circuit.
When the preset value at the emitter of 8 is exceeded, transistor 468 conducts. This causes transistor 472 to conduct and also maintains transistor 468 conductive through variable resistor 474 even as the output voltage of polyphase rectifier 460 drops slightly. The resistance value of variable resistor 474 determines the drop in output voltage required to return transistor 468 to a non-conducting state.

As can be seen from the above description, potentiometer 466 can be adjusted to determine the magnitude of the input quantity at input terminals 451 and 452, which causes transistor 468 to conduct and output a logic one signal. signal 476.
The I _L overcurrent circuit 60 for the phase current responsive relay networks 20-22 is connected to the input terminal 18 of the phase comparison determiner 56.
2 Therefore, the non-inverting input terminal 18 of the AND circuit 110
3 to provide a logic 1 signal with a phase current value slightly greater than the charging current value. The I _L overcurrent circuit for ground current responsive relay network 23 may be set to the desired ground fault current value at which the circuit or disconnect is to be opened. The I _L overcurrent circuit 64 is set to provide a logic one signal at a current value that should not be exceeded and is greater than any power line current that the power line is designed to carry. I _L overcurrent circuit 60 is always connected to _IH overcurrent circuit 64
Since the trip board 94 is set to provide a logic one signal at a current value smaller than
AND circuit 114 is armed and therefore I _H
A logic 1 signal from overcurrent circuit 64 is always routed to trip board 94 and disconnected by trip network 2.
4 and trips at least one circuit disconnector 10, 11, 12.

Under normal operating conditions, AND circuit 110 in phase comparison determiner 56 has its input terminals 213, 127, 124, 137 and 183 armed as described above. The input terminal 108 is not armed because the other end is transmitting a warning signal of a logic 1 signal. During a no-fault current condition, fault detector 58 provides a logic 0 signal to input terminal 54 and thus input terminal 54A of AND circuit 110, and a logic 0 signal is provided to input terminal 82, so that AND circuit 82B has one input terminal open. The square wave signals I _SWP and I _SWN are the square wave generator 67
are supplied to input terminals 85 and 86 through a delay timer 84, respectively. AND GATE 82B
is opened for each negative half cycle of the voltage signals on output buses 62 and 63 and periodically supplies a logical 1 signal to input terminal 87 of AND circuit 110. AND circuit 110 receives a logic value of 1 from fault detector 58.
Since there is no signal and no arming signal at input terminal 108, its output terminal 88 is not energized.

If there is enough fault current to cause one or more I _H overcurrent circuits to issue a logic 1 signal, the trip board 94 will route the logic 1 signal to the disconnect trip circuit 24. The circuits and circuit breakers 10-12 are tripped as described above. If a phase fault current that is less than the full load current flows, the fault detector 58 will have a logic value of 1.
The signal is supplied to AND circuit 110. In the case of a ground current responsive relay network, switch SW1 transmits this logic 1 signal to I in the ground current responsive relay network 23.
It is supplied from _{the L} overcurrent circuit 60. This logical value 1
The signal is also input to the input terminal 98 of the transmit signal control circuit 72.
supplied to Prior to a fault, a logic 1 signal is provided from the open circuit disconnector detector 66 to the input terminal 174 (which indicates that the circuit disconnector is closed) and a logic 0 signal is transmitted. No. control circuit 7
Since the logic 0 signal from the fault detector 58 is supplied to one non-inverting input terminal of the AND circuit 176 in the output terminal 77 of the transmitter frequency controller 76
The transmitter of the transceiver therefore transmitted a warning signal. If a failure occurs and the logic value 1 signal is output to the inverting input terminal 9 of the transmission signal control circuit 72
8, one enabling signal of AND circuit 176 is removed and the logic value 0
The signal is input to the input terminal 74A of the transmitter frequency controller 76.
was supplied to. Therefore, the warning signal is no longer transmitted and the signal RI _SW begins. it is,
This is because the logic value 1 signal of the rectangular wave signal is supplied from the output terminal 70 of the rectangular wave generator 67 to the input terminal 73A of the transmitter frequency controller 76 through the OR circuit in the transmission signal control circuit 72 and the output terminal 73. be.

The protective relay device at the other end of the protected transmission line section was activated to end transmitting its warning signal and begin transmitting a square wave signal I _SW . When the alarm signal from the other end is terminated, the transceiver 78 at the other end causes the logic 1 signal to be removed from the conductor 105, thereby arming the inverting input terminal 108 of the AND circuit 110. When the rectangular wave signal I _SW is transmitted from the other end, the transmitter/receiver 78 at the other end transmits the signal to the conductor 81.
RI _SW is activated, and this signal is supplied to AND circuits 82A and 82B. Each of these AND circuits has a delay timer 84 from the square wave generator 67.
Delayed square wave signals I _SWPD and I _SWND obtained through
has already been supplied as mentioned above. If a fault occurs within the protected transmission line section, the relative phase of the delayed square wave signals I _SWPD , I _SWND with respect to the signal RI _SW will be at least 4 mm in delay circuit 90 with both AND circuits 82A and 82B open. Such as providing an arming signal to input terminal 87 of AND circuit 110 for a timed interval of seconds. Therefore, since a logic 1 signal is provided to input terminal 54A, the AND circuit is in a state to provide a logic 1 signal to its output terminal to initiate the 4 millisecond time interval of delay circuit 90. be done. At the end of this 4 millisecond timed interval, a logic 1 signal is output to the trip board 94.
is transmitted to the input terminal 92 of. This signal activates OR circuit 112 and opens AND circuit 114,
In order to trip the circuit breakers 10 to 12, a logical value of 1 is sent to the circuit break trip network 24.
supply the signal.

If the fault occurs outside the protected transmission line section, the delayed square wave signals I _SWPD and I _SWND signals RI _SW
The phases of the respective AND circuits 82A and 8
2B is not armed and therefore does not provide an arming signal to output terminal 88 long enough to time out delay circuit 90. Each time a logic one signal is removed from the input terminal of delay circuit 90, delay circuit 90 always requires a continuous logic signal for its entire 4 millisecond time interval to have a logic one signal output. Reset virtually instantly. Therefore, in the event of an external failure, the circuit or disconnector 10~
12 is not tripped.

If the transceiver 78 is unable to properly energize its output terminal due to a fault in the transmission channel, for example, conductor 105 is energized with a logic zero signal, and the inverting input terminal 108 of the AND circuit 110 indicates that the protected transmission line section is free of faults. Armed despite the condition. This is an undesirable operating condition and can result in a spurious signal to input terminal 54 and thus 54A causing a circuit or disconnect to be erroneously opened. The phase comparison determiner remains valid for tripping by the fault detector signal during the 150 millisecond time period of timer circuit 134 in channel monitor 106 as described above. After that, the relay network 52
As described in detail above, the I _L overcurrent circuit 60
The circuit cannot be tripped except by a logic 1 signal.

As described above with respect to the frequency detector 65 and the frequency detector blocking circuit 192, false operation due to high frequency transients in the phase conductors is prevented by not arming the inverting input terminal 213 of the AND circuit 110. As described above, if the AND circuit 176 of the transmit signal control circuit 72 is not armed, a logic value 0 signal is supplied to the input terminal 74A, and the alarm signal is output as described above for the circuit and disconnector open circuit detector 66. However, the operation of the circuit or disconnector at the other end is not prevented by the warning signal transmitted from the own end. Transmission of this warning signal is interrupted by not arming the AND circuit 176 when a logic zero signal is provided by the open circuit disconnector detector 66.

FIG. 16 shows a modified circuit disconnector trip network 24' in which circuit disconnectors 10, 11 and 12 may be selectively opened depending on the type of fault.
The circuit breaker trip network 24' utilizes the logic signal at the output terminal 54B of the phase comparison determiner 56. The arming signal is applied by output conductors 25a, 26a and 27a shown in FIGS. 1 and 16. Each of these arming signals is connected to output conductor 25, 26, 27, respectively.
are applied to AND circuits 234, 236, 238 along with each trip output signal appearing at , and then applied to circuit breakers 10, 11, 12 through OR circuits 235, 237, 239.

Output conductors 25, 26 and 2 for fault signal energization
7 is also connected to the input terminal of the OR circuit 240,
The output terminal of this OR circuit 240 is the AND circuit 24
It is connected to the non-inverting input terminal 241 of No. 2. Similarly, output conductors 25a, 26a, and 27a are connected to input terminals of an OR circuit 244, and the output terminal of this OR circuit 244 is connected to an inverting input terminal 245 of an AND circuit 242. An output terminal of AND circuit 242 is connected to one input terminal of OR circuit 243. The output terminal of OR circuit 243 is connected to one input terminal of each OR circuit 235, 237, 239. Depending on which relay network 20, 21 or 22 is activated or for some reason the trip board 94 supplies a logic 1 signal to the output conductor 25, 26 or 27 and If a 0 signal is present on output conductor 25a, 26a, or 27a, AND circuit 234, 236, 238
cannot operate the individual circuits and disconnectors 10, 11, 12, but the OR circuits 240 and 2
44 opens AND circuit 242. As a result, the logic value 1 signal from the AND circuit 242 is output to the OR circuit 242.
3 and OR circuits 235, 237 and 239 to trip all circuit breakers 10, 11 and 12.

The fault signal output conductor 28 from the ground current responsive relay network 23 is connected to one input terminal 248 of the OR circuit 243 via a timing circuit 247. The output terminal of the two-input response (ANY-2) OR circuit 249 is connected to one input terminal 251 of the OR circuit 243. Three input terminals of the two-input response OR circuit 249 are connected to output terminals of AND circuits 234, 236, and 238, respectively. 2 input response OR circuit 24
9 is shown in detail in FIG. Two-input responsive OR circuit 249 is a circuit that provides a logic one signal whenever a logic one signal appears on two or three of its input terminals. If at least two arming signals are present, AND circuits 234, 236, and 238 and two-input responsive OR circuit 249 set OR circuit 243 to a logic value of 1.
A signal is output to all OR circuits 235, 237, and 239, thereby tripping all circuit breakers 10, 11, and 12. Also, if for some reason a ground fault current flows, which circuit or disconnector 10
-12 is not tripped by AND circuits 234-238, and if this condition even persists, during the timeout period of timer circuit 247, timer circuit 247 energizes OR circuit 243 and shuts off all circuits. tripping devices 10-12 and interrupting the ground fault current.

The phase comparison determiner 56 as shown in FIG.
by fault detector 58 in the case of phase current responsive relay networks 20-22 or by ground current responsive relay network 2.
3, it is partially armed by the I _L overcurrent circuit 60. Modified phase comparison determiner 5
6' is the input terminal 10 as shown in FIG.
No warning signal is supplied to input terminal 3' and input terminal 8
If there is a signal RI _SW from the other end supplied to 2', it can be armed by the signal from the own end or the other end. AND circuits 216' and 218' are AND circuits 82A and 82A, respectively, in phase comparison determiner 56.
82B, but each inverting input terminal 25
The difference is that 3' and 254' are provided. Input terminal 10
3' is the inverting input terminal 10 of the AND circuit 110'
8', the above-mentioned two inverting input terminals 253' and 254' and the AND circuit 25
6' is connected to the inverting input terminal 255'. Therefore, whenever there is a warning signal, AND circuit 2
16' and 218' do not provide logic one signals. Such a signal is necessary to provide an arming signal to input terminal 222' of AND circuit 110', which arming signal is necessary to provide an output at output terminal 88' as described above with respect to phase comparison determiner 56. It is.

When the alarm signal is present at the input terminal 103', the signal RI _SW is not present at the input terminal 82', so that the logic 0 signal is sent to the input terminal 258' of the OR circuit 259' and the inverting input terminal 26 of the AND circuit 256'.
0'. Since the alarm signal with a logic value of 1 is present at the inverting input terminal 255', the inverting input terminal 26
A logic 0 signal at 0' prevents a logic 1 signal from appearing at input terminal 261' of OR circuit 259'. The output terminal of OR circuit 259' is connected to one input terminal 264' of OR circuit 265' via timer circuit 263'. The other input terminal 266' of the OR circuit 265' is connected to the input terminal 54'. Therefore,
If a logic one signal is present at either or both input terminals 264', 266', a logic one signal is provided at output terminal 54B'.

Two-input response OR circuit 267' has three input terminals 268', 269' and 270' and one output terminal 271'. The input terminal 54' is connected to the input terminal 268', the output terminal of the AND circuit 216' is connected to the input terminal 269' via the timer circuits 273' and 274', and the output terminal of the AND circuit 218' is connected to the timer circuit 275'. ' and 276' to input terminal 270'. The two-input responsive OR circuit 267' may be any circuit that requires two logic 1 signal inputs to produce a logic 1 signal output. An example is shown in FIG.

When a fault occurs, the warning signal at input terminal 103' is removed and the logic 0 signal is output to AND circuit 25.
6' inverting input terminal 255' and AND circuit 21
6', 218', respectively, inverting input terminals 253',
254'. At the same time as the warning signal is removed, the signal RI _SW is supplied to the input terminal 82';
Logic value 1 signals and 0 signals are alternately supplied to non-inverting input terminals 215 and inverting input terminals 217 of AND circuits 216' and 218', respectively. Input terminal 8
5' and 86' respectively have delayed rectangular wave signals I _{SWPD and 86} '.
Since I _SWND is supplied, AND circuits 216' and 218' provide a logic one signal for at least 5 milliseconds for internal faults, but not as described above for phase comparison determiner 56. Similarly, such a logical 1 signal cannot be provided continuously for 5 milliseconds in response to an external fault. Timing circuits 274' and 276' provide a virtually instantaneous logic 1 signal output in response to an applied logic 1 signal, but have a 12 millisecond reset time period that eliminates the logic 1 signal input. The logic value 1 signal output is maintained for 12 milliseconds even after the As long as the internal fault is connected, the AND circuits 216' and 218' are each operated as a time limit circuit 27.
3' and 274', 275' and 276' to maintain a logic one signal at input terminals 269' and 270', so that output terminal 271' outputs a logic one arming signal to the input of AND circuit 110'. terminal 2
22'.

The input terminal of the AND circuit 110' corresponding to the input terminal 54A of the AND circuit 110 may be omitted as shown, or if provided, a logic 1 signal is continuously supplied thereto. Arming input terminal 21
3', 127', 123', 137' and 184'
are the input terminals 213, 127, and
123, 137 and 184 are armed as described above. Thus, in the event of an internal failure, output terminal 88' is energized with a logic one signal to energize delay circuit 90 and then input terminal 92 of trip board 94.

The logic 1 signal for energizing output terminal 54B' and thus input terminal 98 of transmit signal control circuit 72 is:
In the absence of a logical 1 signal at input terminal 54', the output signal of OR circuit 258' provides the output signal from OR circuit 265'. Obviously, if there is no warning signal and there is a signal RI _SW , input terminal 25
8' and 261' are alternately supplied with logic value 1 signals,
The OR circuit 259' then outputs a logic value of 1 to the input terminal 264' of the OR circuit 265' through the timer circuit 263'.
A signal is supplied to the output terminal 54B' and the input terminal 98.
maintains a logic 1 signal. Therefore, no warning signal is sent, so that even if the fault detector 58 in the case of the phase current responsive relay networks 20-22 and the I _L overcurrent circuit 60 in the case of the earth current responsive relay network 23 Therefore, even if a logical value 1 signal is not generated, the protective relay device at the other end can operate its circuit or disconnector.

When a logic 1 signal is present at input terminal 54' and thus at input terminal 266', OR circuit 265' can output a logic 1 signal independently of the logic signal at input terminal 264'. Furthermore, input terminal 5
4' is also connected to input terminal 268', so that the two-input responsive OR circuit 26 is only required to initially supply a logical 1 signal to input terminals 269' and 270'.
7' provides a logic 1 signal to input terminal 222'.

As shown in FIG. 18, the two-input response OR circuit includes a plurality of transistors 278 connected in parallel with each other between a positive DC bus 280 and an intermediate potential bus 281 and in series with individual resistors. include.
Intermediate potential bus 281 is connected to negative DC bus 282 via variable resistor 283 . The output signal control transistor 284 is connected to the positive DC bus 280 via a resistor 285 and to the negative DC bus 2.
82. The base of the output signal control transistor 284 is connected to the connection point between the variable resistor 283 and the intermediate potential bus 281 via a Zener diode 286. The bases of transistors 278 are each connected to the input terminals of a two-input responsive OR circuit. FIG. 18 shows eight input terminals.
The number of input terminals is equal to the number of inputs required by the circuit arrangement. Variable resistor 283 is adjusted to determine the required number of transistors 278 that must conduct before output signal control transistor 284 is rendered conductive to provide a logic one signal output. As shown in FIG. 18, the two-input response OR circuit is an OR circuit that requires at least two inputs to output a logic value 1 signal.

In the embodiment of the invention shown in FIGS. 1-19, relay networks 20-23 were each individually armed. However, in the embodiment shown in FIG. 20, all output circuits of the relay network are armed simultaneously by OR circuit 315. This OR circuit 3
15, its only output terminal is AND circuit 31
6, 317, 318 and 319, respectively. The four input terminals of OR circuit 315 are connected to phase current responsive relay networks 320, 321 and 322 and ground current responsive relay network 323.
are individually connected to the four fault detectors inside. These relay circuit networks are relay circuit networks 20 to 23 in Figure 1.
corresponds to Since relay networks 320-323 are identical, only one of them, ground current responsive relay circuit 323, will be shown in detail. Fault detector 328
is the fault detector shown in FIG. 4 or FIG. 19,
Alternatively, it may take the form of any other suitable detector that provides a logic one signal to OR circuit 315 when the phase or ground currents reach a fault value. For this reason, phase current responsive current transformers 329, 330 and 3
31 and a ground current responsive current transformer 332 are provided and connected as in FIG. Each current transformer is provided with a load resistor such that a voltage responsive to the current of the current transformer is provided at the output side.

Current transformer 332 is connected to ground current responsive relay network 323
energizes the square wave generator 334 within, which then activates the delay timer 336 and the transmit signal control circuit 337 in the manner described above with respect to FIG.
to support. Transmit signal control circuit 337 controls transmit frequency controller 338, which in turn controls the output wave number of transceiver 339 as described with respect to FIG. Each output terminal of the pair of AND circuits 341 and 342 has two output terminals.
It is connected to each input terminal of an input OR circuit 343, and the output terminal of this OR circuit 343 is connected to the other input terminal of an AND circuit 319. AND circuits 341 and 342 are connected to AND circuit 216'
and 218'. AND circuit 3
41 is a non-inverting input terminal 345 and an inverting input terminal 3
46 and a non-inverting input terminal 347. AND circuit 342 has a non-inverting input terminal 348 and inverting input terminals 349 and 350. Non-inverting input terminal 345 is energized with a delayed square wave signal I _SWPD from delay timer 336. Non-inverting input terminal 3
48 also receives the delayed square wave signal I from the delay timer 336.
Supported by _SWND . One output terminal of transceiver 339 is connected to inverting input terminals 346 and 349 and energizes these inverting input terminals with a logic 1 signal when the opposite transceiver is receiving an alarm signal. Input terminals 347 and 350 are connected together to the other output terminal of transceiver 339 and provide pulsating logic 1 and 0 signals in response to a signal RI _SW provided when the transceiver is not receiving an alarm signal.
energized by a signal.

If the arming signal has already been provided by the OR circuit 315 to the AND circuits 316-319 and there is no warning signal, the delayed square wave signals I _SWPD and I
_SWND and signal RI _SW sequentially energize one or both input terminals of OR circuit 343 with a logic 1 signal, and then apply a logic 1 signal to the other input terminal of AND circuit 319 . At this time, the AND circuit 319 is opened and supplies a logical 1 signal to the timer circuit 352. This timer circuit 352, after a suitable delay of 4 milliseconds, outputs a logic value of 1 to one input terminal of the OR circuit 354.
supply the signal. This OR circuit 354 then provides a trip signal to circuit disconnectors 10, 11 and 12.

FIG. 21 shows a modification of the circuit breaker trip network 356 shown in FIG. A configuration is provided in which the networks 320 to 323 can be armed. Since the configuration for each relay network is exactly the same, only the configuration for ground current responsive relay network 323 is shown in detail here. The circuit breaker trip network 356' includes an AND circuit 36 having a pair of inverting input terminals 361 and 362.
Contains 0. The alarm signal is supplied to the inverting input terminal 361 of the AND circuit 360 through a conductor 363, while the signal RI _SW is supplied to the inverting input terminal 362 of the AND circuit 360 through a conductor 364. The output terminal of AND circuit 360 is connected to one input terminal of OR circuit 366, and the other input terminal is connected to conductor 3
64. The output of OR circuit 366 is applied to timer circuit 367. This time limit circuit 367
operates virtually instantaneously to produce a logic 1 signal in response to an applied logic 1 signal, but maintains such a logic 1 signal for 20 milliseconds after the logic 1 signal input is removed. . The output of timer circuit 367 is supplied to one input terminal of OR circuit 368. The other input terminal is connected to conductor 369 and is energized from fault detector 328 as shown in FIG. The output terminal of OR circuit 368 is connected to transmit signal control circuit 337 by conductor 370, so that transmit signal control circuit 337 is activated upon activation of fault detector 328 or by signal RI _SW .

AND circuits 341 and 342 in FIG.
3,374. These timer circuits provide a 5 millisecond delay on logic 1 signals, but do not provide any delay on reset. Time limit circuit 37
The 3,374 output terminals are each connected to a timer circuit 37.
5,376 to each one input terminal of a two-input responsive OR circuit 378. The arming input terminal 380 of the two-input response OR circuit 378 is the OR circuit 3.
It is connected to the output terminal of 81. This OR circuit 38
One input terminal 382 of 1 is connected to conductor 369 which is connected to fault detector 328 . The two-input response OR circuit 378 selects any two of its input terminals.
When a logical 1 signal is applied to a logic 1 signal, a logical 1 signal is applied to its output terminal. 2 input response OR circuit 3
78 therefore operates both timer circuits 375 and 37 independently of the signal supplied from OR circuit 381.
6 or the OR circuit 381
and one of the timer circuits 375 or 376.

Two-input responsive OR circuit 378, when its output terminal is energized, supplies a logical 1 signal to one input terminal of each of OR circuits 383, 384, and 385 if switch SW5 is in the position shown; A trip signal is applied to each of the circuit breakers 10-12. Similarly, each device for a phase current responsive relay network has a respective pair of conductors 388, 389, 390.
are connected to a pair of input terminals of a two-input responsive OR circuit 378, and also to one input terminal each of an OR circuit 381.

FIG. 22 shows the circuit breakers 10, 11, 12 when combined with the breakout trip network 356' of FIG. 21 and when switch SW5 in FIG. 21 is switched to the opposite position as shown. It is a circuit network that trips each of the two circuits individually or simultaneously. a pair of conductors 388, 389, 390 controlled by phase current responsive relay networks 320, 321, 322, respectively;
are connected to input terminal pairs 388A, 389A, and 390A of OR circuits 391, 392, and 393, respectively. The output terminals of the OR circuits 391, 392, 393 are connected to the AND circuits 394, 395, 3, respectively.
96 and to each one input terminal of OR circuit 398 . The output terminal of the OR circuit 398 is connected to the inverting input terminal of the AND circuit 400, and the output terminal of the OR circuit 402 is connected to the inverting input terminal of the AND circuit 400.
is connected to one input terminal of the AND circuit 39
The other input terminals of 4,395, 396 and 400 are all connected to a conductor 403, which is then connected to a two-input response OR circuit 3 via a timer circuit 401, input terminal 403A and switch SW5.
78 output terminal. Therefore, AND circuits 394, 395, 396, and 400 can provide a logic 1 signal only after being provided with a logic 1 signal from two-input responsive OR circuit 378. Each output terminal of AND circuits 394, 395, 396 has 2
Each input terminal is connected to one input terminal of input responsive OR circuit 404, and its output terminal is connected to the other input terminal of OR circuit 402.

The output terminals of AND circuits 394, 395, 396 are connected to the other input terminals of OR circuits 383, 384, 385 through 405, 406, 407, respectively. When a logic one signal is provided by conductor 403 to AND circuits 394, 395, and 396, these AND circuits are opened, and the logic one signal output from OR circuit 391, 392, or 393 causes the logic one signal to be applied. A logic one signal is individually provided to trip each circuit or disconnect when activated.

Since the output terminals of the OR circuits 391, 392, and 393 are connected to the input terminal of the OR circuit 398, when any one output terminal is energized with a logic value 1 signal, the OR circuit 398 is connected to the input terminal of the AND circuit 400. Apply a logic 1 signal to the inverting input terminal. This logic 1 signal prevents AND circuit 400 from providing a logic 1 signal to OR circuit 402 when timer circuit 401 acts to provide a logic 1 signal to conductor 403. Thus, each circuit or breaker can be activated and tripped directly from an AND circuit 394, 395 or 396, respectively. However, if AND circuits 394, 395 and 396
If two or more of the AND circuits provide logic 1 signals, then at least two input terminals of the two-input responsive OR circuit 404 are energized by these logic 1 signals. As a result, a logical 1 signal is provided to the other input terminal of OR circuit 402 and thus through conductor 408 to OR circuits 383, 384 and 3.
85, all circuits and disconnectors 10
Trip ~12.

If ground current responsive relay network 323 indicates the presence of a fault, but phase current responsive relay networks 320-322 do not indicate the presence of a fault, which input terminal pair 38
8A, 389A, and 390A do not receive a logic 1 signal, and none of the OR circuits 391, 392, and 393 supply a logic 1 signal to OR circuit 398, so AND circuit 400 is opened and outputs a logic 1 signal.
A logic one signal is provided to OR circuit 402 when the signal is provided from conductor 403 . As previously discussed for two-input responsive OR circuit 404, this causes OR circuit 402 to provide a logical 1 signal on conductor 408, which in turn causes OR circuits 383-385 to trip all circuit circuits and disconnects. I will let you do it.

Effects of the Invention As is clear from the above description, the protective relay device of the present invention is not only extremely reliable and reliable, but also prevents it from responding to false signals or accidentally tripping circuits or disconnectors. There is nothing to do.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a protective relay device that is combined with a three-phase power transmission line and embodies the present invention, Fig. 2 is a detailed block diagram of an embodiment of a relay network, and Fig. 3 is a phase comparison determination device. Figure 4 is the block diagram of the fault detector, Figure 5 is the circuit diagram of the square wave generator, Figure 6 is the circuit diagram of the circuit breaker open circuit detector, and Figure 7 is the transmitter block diagram. Fig. 8 is a block diagram of the transmitter frequency controller, Fig. 9 is a block diagram of the delay timer, Fig. 10 is a block diagram of the channel monitor, Fig. 11 is a block diagram of the trip board, Fig. 12 is a block diagram of the channel fault board, Fig. 13 is a circuit diagram of an overcurrent circuit that can be used as an I _L overcurrent circuit and an I _H overcurrent circuit, Fig. 14 is a circuit diagram of a frequency detector, and Fig. 15 16 is a block diagram of a frequency detector blocking circuit, FIG. 16 is a block diagram showing a circuit breaker trip circuit network of a modified example, FIG. 17 is a block diagram of a modified phase comparison determiner, and FIG. A circuit diagram of a two-input response OR circuit, FIG. 19 is a circuit diagram showing a modified fault detector, FIG. 20 is a block diagram of a protective relay device according to another embodiment, and FIG. 21 is a circuit diagram of a modified example. FIG. 22 is a block diagram of a circuit suitable for use in conjunction with FIG.

Claims (1)

[Claims] 1. A circuit breaker 10 provided for each phase conductor (4, 5, 6 in FIG. 1) of the multiphase AC power transmission line in order to protect the multiphase AC power transmission line. . output conductors 25, 26, 27, 28 connected individually to each input terminal of said OR circuit in the network;
circuits and disconnection control networks 20, 21, 2 for each phase and for the zero phase, which are individually connected to each phase conductor or connected to all phase conductors;
2 and 23, and the circuit and disconnection control network for each phase (52 in FIG. 2) controls changes in the phase current supplied from both terminal stations of the multiphase AC transmission line to each phase conductor. a fault detector 58 that detects a fault by a transmitter/receiver 78 that is connected to the fault detector and that transmits a warning signal to the other end and receives the alarm signal from the other end when the fault is not detected.
, a first AND circuit (82A in FIG. 3) that compares the phase of the positive half wave of the own end current and the other end current from the transmitter/receiver, and a negative half wave of the own end current and the other end current from the transmitter/receiver. Second AND circuit 8 for comparing wave phases
2B and OR circuit 86A to these AND circuits.
a third AND circuit 11 connected to the fault detector and the transceiver through the
0, and when the fault is not detected and therefore the alarm signal is being received from the other end, it is locked and does not operate; however, the fault is detected and therefore the alarm signal is not received from the other end. a phase comparison determiner 56 which is sometimes actuated and thereby supplies a signal from the third AND circuit to the output conductor to actuate the circuit breaker and the zero phase circuit breaker; The control circuitry 52 includes:
An I _L overcurrent circuit 60 that detects a ground current exceeding a set value as a fault current, and an I _L overcurrent circuit 60 that is connected to this I L overcurrent circuit and sends a warning signal to the other end when the fault current is not detected. a transceiver 78 for receiving an alarm signal from the other end;
a first AND circuit 82A that compares the phase of a positive half wave of the current at its own end and the current at the other end from the transmitter/receiver;
A second AND circuit 82B that compares the phase of the negative half wave of the current at its own end and the current at the other end, and a second AND circuit 82B connected to these AND circuits via an OR circuit 86A, and also connected to the I _L overcurrent circuit and the transmitting/receiving circuit. It has a third AND circuit 110 connected to the machine, and is locked and does not operate when the fault current is not detected and therefore the alarm signal is being received from the partner end, but when the fault current is detected, Accordingly, a phase comparison determiner 56 is activated when the warning signal is not received from the other end, thereby supplying a signal from the third AND circuit to the output conductor for activating the circuit switch or disconnector. protective relaying equipment, including; 2. In order to protect the multiphase AC power transmission line, individually connect the circuit breakers 10, 11, and 12 provided for each phase conductor (4, 5, and 6 in Figure 1) of this multiphase AC power transmission line. The first OR circuit (23 in Figure 16) connected to
5, 237, 239), a first AND circuit 234, 236, 238 individually connected to one input terminal of each first OR circuit, and a first AND circuit 234, 236, 238 connected to the other input terminal of every first OR circuit. Second OR circuit 2
43, a third OR circuit 249 connected between the first input terminal of this second OR circuit and all the first AND circuits and responsive to a plurality of inputs;
a timer circuit 247 connected to the second input terminal of the OR circuit of the circuit breaker for actuating the circuit breakers individually or simultaneously;
4' and each first circuit in this circuit and the circuit breaker actuation network.
a first output conductor 25, 26, 27 individually connected to one input terminal of the AND circuit, and a second output conductor 25a individually connected to the other input terminal of each of the first AND circuits; 26a, 27a and a circuit for each phase individually connected to each phase conductor and a disconnection control circuit (20, 2 in FIG. 1).
1, 22), and a zero-phase circuit breaker control network 23 having an output conductor 28 connected to a timer circuit in the circuit breaker operating network and connected to all phase conductors. and the circuit breaker actuation network further includes a second AND circuit 242 connected to the third input terminal of the second OR circuit and having a non-inverting input terminal 241 and an inverting input terminal 245. , a fourth OR circuit 240 connected between the non-inverting input terminal and all the first output conductors, and a fifth OR circuit 240 connected between the inverting input terminal and all the second output conductors. includes an OR circuit 244;
The circuit for each phase and the circuit breaker control network (5 in Figure 2)
2) includes a fault detector 58 that detects a fault based on a change in the phase current supplied from both end stations of the multiphase AC transmission line to each of the phase conductors and is connected to each second output conductor; a transceiver 78 connected to the detector and transmitting a warning signal to the other end and receiving the alarm signal from the other end when the failure is not detected; A first AND circuit 82A that compares the phase of a positive half wave of the current at its own end and a second AND circuit 8 that compares the phase of a negative half wave of the current at its own end and the current at the opposite end.
2B and OR circuit 86A to these AND circuits.
a third AND circuit 11 connected to the fault detector and the transceiver through the
0, and when the fault is not detected and therefore the alarm signal is being received from the other end, it is locked and does not operate; however, the fault is detected and therefore the alarm signal is not received from the other end. a phase comparison which is sometimes actuated to thereby provide a signal from said third AND circuit to each first output conductor and from said fault detector to each second output conductor for actuating said circuit breakers; The zero-phase circuit and breaker control network includes an I _L overcurrent circuit 60 that detects a ground current that is equal to or greater than a set value as a fault current, and _a a transceiver 78 that transmits a warning signal to the other end and receives the alarm signal from the other end when the fault current is not detected; A first AND circuit 82A that compares the phase of a positive half wave, a second AND circuit 82B that compares the phase of a negative half wave between the self-end current and the opposite end current, and an OR circuit 86A to these AND circuits. a third AND circuit 110 connected to the I _L overcurrent circuit and the transceiver; When the fault current is detected and therefore the warning signal is not received from the other end, it is activated, thereby causing the circuit to be disconnected from the third AND circuit to the output conductor 28. and a phase comparison determiner 56 for supplying a signal for activating the device. 3. In order to protect the multiphase AC power transmission line, the circuit breakers 10, 11, and 12 provided for each phase conductor (4, 5, and 6 in Figure 1) of this multiphase AC power transmission line are individually connected. (38 in Figure 21) connected to the first OR circuit (38 in Figure 21).
3,384,385), a first AND circuit (394,395,396 in FIG. 22) individually connected to one input terminal of each first OR circuit, and the other of all first OR circuits. the second connected to the input terminal of
a third OR circuit 404 connected between one input terminal of this second OR circuit and all the first AND circuits and responsive to multiple inputs;
a second AND circuit 400 connected to the other input terminal of the second OR circuit and having a non-inverting input terminal and an inverting input terminal; the non-inverting input terminal and one input terminal of all the first AND circuits; a timer circuit 401 connected to the inverting input terminal, a fourth OR circuit 398 connected to the inverting input terminal, and individually connected to each input terminal of this fourth OR circuit and the other input terminal of each first AND circuit. Fifth OR circuit 3
91, 392, 393, including a sixth OR circuit (380 in FIG. 21) connected to the timer circuit and responsive to multiple inputs, and a seventh OR circuit 381 connected to the sixth OR circuit; a circuit breaker actuation network for activating the circuit breakers individually or simultaneously; each fifth OR circuit in the circuit breaker actuation network; and the sixth OR circuit; first output conductors 388-388 individually connected to
A, 389-389A, 390-390A) and a second output conductor individually connected to each input terminal of the seventh OR circuit, and a circuit for each phase connected individually to each phase conductor. a first output conductor (37 in FIG. 20) connected to the sixth OR circuit in the circuit breaker control network (320, 321, 322 in FIG. 20) and the circuit breaker actuation network;
1,372) and a second output conductor 369 connected to the input terminal of the seventh OR circuit, and a zero-phase circuit and breaker control network connected to all phase conductors (Fig. 323), each circuit and disconnection control network detects a failure based on a change in phase current or an amount of ground current supplied from both terminal stations of the multiphase AC transmission line to each phase conductor, and each second
a fault detector 328 connected to the output conductor of the fault detector; and a transceiver 33 connected to the fault detector and transmitting a warning signal to the other end and receiving the alarm signal from the other end when the fault is not detected.
9, a first AND circuit 341 that compares the phases of positive half waves of the current at its own end and the current at the other end, and is connected to one of the first output conductors; a second AND circuit 3 connected to the other of said first output conductors;
A protective relay device including 42.