JPS6146690A - Processing circuit of multi-channel signal - Google Patents

Processing circuit of multi-channel signal

Info

Publication number
JPS6146690A
JPS6146690A JP59168156A JP16815684A JPS6146690A JP S6146690 A JPS6146690 A JP S6146690A JP 59168156 A JP59168156 A JP 59168156A JP 16815684 A JP16815684 A JP 16815684A JP S6146690 A JPS6146690 A JP S6146690A
Authority
JP
Japan
Prior art keywords
signal
processing circuits
circuits
processing circuit
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59168156A
Other languages
Japanese (ja)
Inventor
Fumio Nagumo
名雲 文男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP59168156A priority Critical patent/JPS6146690A/en
Publication of JPS6146690A publication Critical patent/JPS6146690A/en
Pending legal-status Critical Current

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  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE:To obtain a signal processing circuit of each channel, which can solve troubles relating to a temperature characteristic, etc., by arraying symmetrically the even-number of signal processing circuits so as to make them integrated and causing the symmetry to form a difference signal between channels so as to input it. CONSTITUTION:Signals R, G and B inputted from input terminals 1, 2 and 3 are supplied to processing circuits 4, 5, 6 and 7. The strain of the processing circuits 4 and 5 and that of the processing circuits 6 and 7 are made integrated on the same chip, and action characteristics of the circuits 4 and 5 become coincident and the same coincidence can be obtained in the circuits 6 and 7. When signals processed by such processing circuits 4, 5, 6 and 7 are applied to subtractors 8 and 10 and an adder 9, a luminance signal of an NTSC system can be obtained from the adder 9, while from the subtractors 8 and 10 red and blue color difference signals can be obtained. Since these color difference signals are formed in the processing circuits of the same action characteristic, the white balance can be secured.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多チャンネルの同時信号に対して信号処理を
施す多チャンネル信号処理回路に関し、例えばカラーテ
レビジョンカメラにおケルプロセス回路等に適用される
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multi-channel signal processing circuit that performs signal processing on simultaneous multi-channel signals, and is applicable to, for example, a Kel process circuit in a color television camera. be done.

〔従来の技術〕[Conventional technology]

従来より、カラーテレビジョンカメラでは、被写体を撮
影した撮影出力として得られる三原色信号すなわち赤色
信号、緑色信号および青色信号について、各信号ライン
にそれぞれプロセス処理回路を設けてガンマ補正処理等
のプロセス処理を施すようになっている。そして、上記
4!r@号ラインすなわち各チャンネルのプロセス回路
は、1個づつ個別に集積回路化したシ、するいは全チャ
ンネル分を総めて集積回路化していた。
Traditionally, in color television cameras, process processing circuits are installed in each signal line to perform process processing such as gamma correction processing on the three primary color signals, that is, the red signal, green signal, and blue signal obtained as the photographic output of a photographed subject. It is supposed to be administered. And above 4! The process circuits of the r@ line, that is, the process circuits of each channel, were individually integrated circuits one by one, or all the channels were integrated into an integrated circuit.

一般に、上記プロセス回路等の多チャンネル信号処理回
路では、チャンネル毎に集積回路化したのでは各チャン
ネルの調整誤差やプリント基板上の温度分布の差異に起
因する温度差が各チャンネルの動作特性差となってしま
う。また、全チャンネル分を総めて集積回路化すれば、
上記動作特性差を極めて小さく抑えることが可能になる
が、それでも集積回路内の温度分布の差異に起因する温
度特性差の影響を避けることはできない。
In general, in multi-channel signal processing circuits such as the process circuits mentioned above, if each channel is integrated into an integrated circuit, temperature differences due to adjustment errors of each channel and differences in temperature distribution on the printed circuit board will result in differences in operating characteristics of each channel. turn into. Also, if all channels are integrated into an integrated circuit,
Although it is possible to suppress the above-described difference in operating characteristics to an extremely small level, it is still not possible to avoid the influence of differences in temperature characteristics caused by differences in temperature distribution within the integrated circuit.

ここで、カラーテレビジョンカメラのプロセス回路では
、各チャンネル間の動作特性差が画像の色に影響を及ぼ
し、例えば白黒画像に色が付いてしまう等の画質劣化の
原因となる。
Here, in the process circuit of a color television camera, differences in operating characteristics between channels affect the color of the image, causing image quality deterioration such as coloration in black and white images, for example.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

すなわち、多チャンネル信号処理回路では、各、チャン
ネルの動作特性にチャンネル間差が存在することか問題
となり、特に温度特性の影響が大きな問題となっている
That is, in a multi-channel signal processing circuit, the existence of differences between channels in the operating characteristics of each channel is a problem, and the influence of temperature characteristics is a particularly big problem.

そこで、本発明は上述の如き従来の問題点に鑑み、温度
特性差等によるチャンネル開蓋が問題になることの々い
新規な回路構成の多チャンネル信号処理回路全提供し、
例えばカラーテレビジョンカメラのプロセス回路の集積
回路化を容易にするとともに低彩度画像の色の誤差全極
めて少なくすることを目的とする。
Therefore, in view of the above-mentioned conventional problems, the present invention provides a multi-channel signal processing circuit with a novel circuit configuration in which opening of channels due to differences in temperature characteristics is not a problem.
For example, the purpose is to facilitate the integration of process circuits in color television cameras and to minimize all color errors in low-chroma images.

〔問題点を解決するための手段〕[Means for solving problems]

本発明に係る多チャンネル信号処理回路は、偶数個の信
号処理回路を対称に配列して集積回路化するとともに、
その対称なチャンネル間の差信号を形成して出力する構
成となっている。
The multi-channel signal processing circuit according to the present invention has an even number of signal processing circuits arranged symmetrically to form an integrated circuit, and
The configuration is such that a difference signal between the symmetrical channels is formed and output.

〔作用〕[Effect]

本発明に係る多チャンネル信号処理回路では、偶数個の
信号処理回路を対称に配列して集積回路化することによ
り集積回路内の温度分布全均一にし、対称なチャンネル
間の差信号を出力とすることによって各チャンネルの温
度特性差等によるチャンネル開蓋が問題になら々いよう
にする。
In the multi-channel signal processing circuit according to the present invention, by arranging an even number of signal processing circuits symmetrically and integrating them into an integrated circuit, the temperature distribution within the integrated circuit is made completely uniform, and a difference signal between symmetrical channels is output. This prevents the opening of the channel lid from becoming a problem due to differences in temperature characteristics of each channel.

〔実施例〕〔Example〕

以下、本発明に係る多チャンネル信号処理回路の一実施
例について図面に従い詳細に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multi-channel signal processing circuit according to the present invention will be described in detail below with reference to the drawings.

第1図のブロック図は本発明をカラーテレビジョンカメ
ラの信号処理回路に適用した場合の一実施例を示すもの
で、この実施例において、第1ないし第3の信号入力端
子1,2.3には図示しないカラーイメージセンサにて
得られる赤色信号R1緑色信号G1青色信号Bが供給さ
れる。
The block diagram in FIG. 1 shows an embodiment in which the present invention is applied to a signal processing circuit of a color television camera. In this embodiment, first to third signal input terminals 1, 2, 3 are supplied with a red signal R1, a green signal G1, and a blue signal B obtained by a color image sensor (not shown).

この実施例の信号処理回路は、4個のプロセス処理回路
4,5,6.7を備え、これらが2個づつ対称に配列さ
れ所謂ミラーイメージ構造に集積回路化されている。同
一チップ上に対称に配列して集積回路化された第1およ
び第2のプロセス処理回路4,5は、その対称性によっ
て温度特性等の動作特性が一致する。また、上記第3お
よび第4のプロセス処理回路6,7も動作特性が一致す
る。ここで、上記第1および第2のプロセス処理回路4
,5は、 fCX)÷xr なるガンマγ〆補IE関数fcx)にて示される動作特
性を呈し、また、上記第3および第4のプロセス処理回
路6,7は、 5F(x)÷Xr なるガ/マ、S数1/(x)にて示される動作特性を呈
するものとする。なお、それぞれ集積回路化された第1
および第2のプロセス処理回路4,5と第3膠よび第4
のプロセス処理回路6,7は、同一集積回路内では温度
特性等の動作特性が略完全に一致しているのであるが、
集積回路毎に温度特性差等があるのでfCX) x f
(X)となっている。
The signal processing circuit of this embodiment includes four process processing circuits 4, 5, 6.7, two of which are arranged symmetrically and integrated into a so-called mirror image structure. The first and second process processing circuits 4 and 5, which are symmetrically arranged and integrated on the same chip, have the same operating characteristics such as temperature characteristics due to their symmetry. Further, the third and fourth process processing circuits 6 and 7 also have the same operating characteristics. Here, the first and second process processing circuits 4
. It is assumed that the operating characteristic is expressed by Ga/ma and S number 1/(x). In addition, the first
and second process processing circuits 4, 5, third glue and fourth
The process processing circuits 6 and 7 have almost completely identical operating characteristics such as temperature characteristics within the same integrated circuit.
Since there are differences in temperature characteristics etc. for each integrated circuit, fCX) x f
(X).

ただし、f (x) 1% f (x)である。However, f(x) is 1% f(x).

上記第1のプロセス処理回路4には上記第1の信号入力
端子1から赤色信号Rが供給され、また、上記第2およ
び第3のプロセス処理回路5,6には上記第2の信号入
力端子2から緑色信号Gが供給され、さらに、上記第4
のプロセス処理回路7には上記第3の信号入力端子3か
ら青色信号Gが供給されるようになっている。
The first process processing circuit 4 is supplied with the red signal R from the first signal input terminal 1, and the second and third process processing circuits 5 and 6 are supplied with the red signal R from the second signal input terminal 1. The green signal G is supplied from the fourth
A blue signal G is supplied to the process processing circuit 7 from the third signal input terminal 3.

上記第1のプロセス処理回路4は、上記赤色・信号Rに
ついてガンマ補正処理な施して、RO=、fcR) なる赤色補正出力信号R8を第1の信号減算合成器8と
信号加算合成器9に供給する。!た、上記第2のプロセ
ス処理回路5は、上記緑色信号Gについてガンマ補正処
理を施して、 Go=f(G) なる緑色補正出力信号G。を上記第1の信号減算合成器
8と信号加算合成器9に供給する。また、上記第3のプ
ロセス処理回路6は、上記緑色信号Gについてガンマ補
正処理を施して、 G1= i?(G) なる緑色補正出力信号G1を第2の信号減算合成器10
と上記信号加算合成器9に供給する。そして、上記第4
のプロセス処理回路7は、上記青色信号Bについてガン
マ補正処理を施して、Bユニ r(B) なる青色補正出力信号B1全上記第2の信号減算器10
と信号加算合成器9に供給する。
The first process processing circuit 4 performs gamma correction processing on the red signal R, and outputs a red correction output signal R8 as follows: RO=, fcR) to a first signal subtraction synthesizer 8 and a signal addition synthesizer 9. supply ! Further, the second process processing circuit 5 performs gamma correction processing on the green signal G to produce a green corrected output signal G such that Go=f(G). is supplied to the first signal subtraction combiner 8 and signal addition combiner 9. Further, the third process processing circuit 6 performs gamma correction processing on the green signal G to obtain G1=i? (G) The green color corrected output signal G1 is sent to the second signal subtraction synthesizer 10.
and is supplied to the signal addition/synthesizer 9. And the fourth above
The process processing circuit 7 performs gamma correction processing on the blue signal B to obtain a blue corrected output signal B1 as B uni r(B).
and is supplied to the signal addition synthesizer 9.

上記第1の信号減算合成器8は、供給される各信号R5
゜、Goの差信号CRo−Go)e形成してマトリクス
回路11に供給する。また、上記第2の信号減算合成器
10は、同様に差信号(B 1− G t)を形成して
上記マトリクス回路11に供給する。
The first signal subtraction synthesizer 8 receives each of the supplied signals R5.
A difference signal CRo-Go)e between ゜ and Go is formed and supplied to the matrix circuit 11. Further, the second signal subtractive synthesizer 10 similarly forms a difference signal (B1-Gt) and supplies it to the matrix circuit 11.

上記信号加算合成器9は、供給される各信号R8、Go
、G1.B1を所定の重みで加算合成して、例えば、 にて示されるN T” S C方式の輝度信号Yを形成
する。
The signal adder/synthesizer 9 receives each of the supplied signals R8, Go.
, G1. B1 is added and combined with a predetermined weight to form, for example, a luminance signal Y of the NT''SC method shown in the following.

また、上記マ) IJクス回路11は、供給される各差
信号CB、o−Go)、 CBl−Gl)Kついて、な
るマトリクス演算を行なって、赤色差信号cR−yと青
色差信号CB−Y k形成する。このマトリクス回路1
1に形成される各色差信号CR−Y p CB−Yは、
上述のように対称に配列して集積回路化することにfC
X)なる動作特性を呈するようにした第1および第2の
プロセス処理回路4,5の各出力信号R8,Goについ
て第1の信号減算合成器8により形成した差信号R8−
Goと、同様に第3および第4のプロセス処理回路6,
7の各出力信号G1゜B1について第2の信号減算合成
器10に、IJ影形成た差信号B1.G1とを用いて形
成されるので、ホワイトバランスの条件(すなわちR=
G=B )下では確実に零になる。
In addition, the matrix circuit 11 performs the following matrix operation on each of the supplied difference signals CB, o-Go), CBl-Gl)K to obtain a red difference signal cR-y and a blue difference signal CB-. Form Yk. This matrix circuit 1
Each color difference signal CR-Y p CB-Y formed in
fC in symmetrically arranging and integrating circuits as described above.
Difference signal R8- formed by the first signal subtraction synthesizer 8 for each output signal R8, Go of the first and second process processing circuits 4, 5, which are designed to exhibit operating characteristics as shown in FIG.
Go, as well as third and fourth process processing circuits 6,
The second signal subtractive synthesizer 10 receives the IJ shadow-formed difference signal B1.7 for each output signal G1.B1. G1, so the white balance conditions (i.e. R=
G=B), it definitely becomes zero.

すなわち、例えば赤色差信号CR−Yは、CR−Y =
0.70 (Ro−Go) −0,11(Bl−Gl)
= 0.700’(R) −f(G)) −0,11C
PCB)−r(G))にて示されるので、R=G=Bで
あればf(x)〆f (x)でめっても正確に零になり
、ホワイトバランスを確保することができる。
That is, for example, the red difference signal CR-Y is CR-Y =
0.70 (Ro-Go) -0,11 (Bl-Gl)
= 0.700'(R) -f(G)) -0,11C
PCB)-r(G)), so if R=G=B, f(x)〆f(x) becomes exactly zero, ensuring white balance. .

なお、上述の実施例では、4個のプロセス処理回路4,
5,6.7を2個づつ集積回路化した構成を採用したが
、第2図に示すように4個のプロセス処理回路4 t 
5r 6r 7 c iチップ上に対称に配列して集積
回路化し、その対称なチャンネル間の差信号R6−Go
、B、−01を各信号減算合成器8,10にて形成する
ようにしても良い。
In addition, in the above-mentioned embodiment, four process processing circuits 4,
We adopted a configuration in which two each of 5 and 6.7 were integrated into circuits, but as shown in Fig. 2, four process processing circuits 4t
5r 6r 7 c i They are arranged symmetrically on an integrated circuit, and the difference signal R6-Go between the symmetrical channels is
, B, -01 may be formed by the respective signal subtractive synthesizers 8 and 10.

また、上述の第1図に示した実施例における各プロセス
処理回路4,5,6,7の入力側に、それぞれ2チャン
ネル分づつ対称に配列して集積回路化した利得制御型増
幅器21.22,23,24を第3図に示すように設け
て、自動利得制@Aができる。
Further, gain control type amplifiers 21 and 22 each having two channels arranged symmetrically and integrated into an integrated circuit are provided on the input side of each process processing circuit 4, 5, 6, and 7 in the embodiment shown in FIG. , 23, and 24 as shown in FIG. 3, an automatic gain system @A can be achieved.

〔発明の効果〕〔Effect of the invention〕

上述の実施例の説明から明らかなように、本発明に係る
多チャンネル信号処理回路では、偶数個の信号処理回路
を対称に配列して集積回路化して、その対称なチャンネ
ル間の差信号を形成して出力するようにしたことによっ
て、温度特性差等によるチャンネル間差が問題拠なるこ
となく各チャンネルに信号処理を施すことができ、例え
ばカラーテレビジョンカメラのホワイトバランス全損な
うことなくプロセス処理金施すことができ、所期の目的
を十分に達成することができる。
As is clear from the description of the embodiments above, in the multi-channel signal processing circuit according to the present invention, an even number of signal processing circuits are arranged symmetrically and integrated into an integrated circuit, and a difference signal between the symmetrical channels is formed. This makes it possible to perform signal processing on each channel without causing problems due to differences between channels due to differences in temperature characteristics. can be applied, and the intended purpose can be fully achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明金力ツーテレビジョンカメラの信号処理
回路に用した場合の一実施例金示すブロック図であり、
第2図は同じく本発明の他の実施例を示すブロック図で
メジ、第3図はさらに他の実施例を示すブロック図であ
る。 4 s 5.6 v 7・・・プロセス処理回路8.1
0・・・信号減算合成器
FIG. 1 is a block diagram showing an embodiment of the present invention when used in a signal processing circuit of a TV camera;
FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram showing still another embodiment. 4 s 5.6 v 7...Process processing circuit 8.1
0...Signal subtraction synthesizer

Claims (1)

【特許請求の範囲】[Claims] 偶数個の信号処理回路を対称に配列して集積回路化する
とともに、その対称なチャンネル間の差信号を形成して
出力する構成の多チャンネル信号処理回路。
A multi-channel signal processing circuit configured to integrate an even number of signal processing circuits by symmetrically arranging them, and to form and output a difference signal between the symmetrical channels.
JP59168156A 1984-08-11 1984-08-11 Processing circuit of multi-channel signal Pending JPS6146690A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59168156A JPS6146690A (en) 1984-08-11 1984-08-11 Processing circuit of multi-channel signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59168156A JPS6146690A (en) 1984-08-11 1984-08-11 Processing circuit of multi-channel signal

Publications (1)

Publication Number Publication Date
JPS6146690A true JPS6146690A (en) 1986-03-06

Family

ID=15862849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59168156A Pending JPS6146690A (en) 1984-08-11 1984-08-11 Processing circuit of multi-channel signal

Country Status (1)

Country Link
JP (1) JPS6146690A (en)

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