JPS6145276A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device in which multiple bits of data, for example, one page's worth of data, can be serially read or written from an arbitrary starting bit. The present invention relates to a two-way access memory for video, for example.

(Prior art) Figure 9 shows a conventional video non-access memory c.
◇The video RAM shown in the figure has, for example, a memory cell array 1 having 512 x 512 bit memory cells, 512 word lines WL, and a word selection signal applied to these word lines WL. A word decoder 2 for applying voltage, 512 bit lines BL, . . . old . . . Furthermore, the video RAM shown in FIG. 9 is connected to each bit line BLo=...@BLgIl through a respective gate transistor Qos...1i1t in order to read out data in series, that is, serially read data. It has a 512-bit shift register 5t connected thereto.

The operation of the video RAM shown in FIG. 9 will be explained with reference to FIG. 1O. First, in order to activate each circuit related to the serial read operation, the serial read signal (2) is set to a low level at time to, and the row address RA is input to the word decoder 2. As a result, one word line WL is selected at time t1, a word line selection signal is applied to the word line WL, and each memory MC,..., MC is selected.
□The stored data of 1 is displayed on the line BL0.・・・・・・
...-Output to BLSII. At time t2, clock φ8 is set to high level, and transistors Q0.・・・
...m Qllll is all turned on. As a result, each memory cell MC, . . .

Read data from MC3II is set in shift register 5 in parallel. Thereafter, by applying a shift clock signal to the shift register 5, the shift register 5t
- By sequentially shifting each memory cell M Co
=..., the data stored in MC□1 is sequentially output as serial output data Dout(a), and
While such serial output data Dout(s) is being output, the row address strobe signal m and the column A address strobe signal CAS are set to low level, and the row address and column address are sent to the word decoder 2 and column decoder 3, respectively. By applying this voltage, a random access operation can be performed to any memory cell in one memory cell array one pit at a time.

However, in the conventional video RAM mentioned above, 1
When serial reading is performed from a memory cell connected to a word line of a book, it is always connected to the bit line BL, and data is read from nine memory cells, and any bit is shifted to any address within one page. 〇 (Problem to be solved by the invention) In view of the problems in the conventional type described above, the present invention has the disadvantage that it is impossible to perform serial reading from Based on the concept of using a latch circuit corresponding to each bit line and a shift register that controls data input/output to the latch circuit in a semiconductor memory device that can be programmed, serial read from an arbitrary address or serial write is performed. The purpose is to enable movement.

Means for Solving Problem C) According to the present invention, a memory cell array having a plurality of memory cells each arranged at an intersection of a bit line and a word line,
A data latch circuit provided corresponding to each bit line, a first gate means for controlling data transfer between each bit line and the corresponding data latch circuit, and a shift register capable of presetting data.

and a plurality of gate circuits &g connected to each data latch circuit, and each gate circuit is provided with a wt2 gate means controlled by the output of a corresponding stage of the shift register, and is arbitrarily selected according to the set state of the shift register. Provided is a semiconductor memory device characterized in that serial data can be input or output from the start bit of the serial data.

(Function) In the present invention, read data of nine memory cells connected to one word line is temporarily stored in each latch circuit, and it is determined which of these stored data is to be output. A ring counter type shift register that determines the address is used to control the data stored in each latte circuit so that the nine data are serially output to the data bus.
For example, is there a column decoder in the shift register? The data of the read start bit is preset, and reading is performed from the start bit.

(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 111 shows a video RAMo according to an embodiment of the present invention.
Outline. The video RAM in the same figure is the video RAM in FIG.
Memory cell array 1 similar to AM, word decoder 2,
Column decoder 3, input/output boot 4 and each bit line B
L, ..., BL, □.

connected to the next gate transistor Qoe...
*Q+t.

In addition, each of these transistors Qoe...e
Latch circuit v6 connected to each bit line via Qs1□
DL・.

......DLsste ring counter type shift register 6, second column decoder 7, and each latch circuit D Lo =..., D Lstt K are connected and controlled by the shift register 6 Transistors QAo*...*Qhsss are provided. The shift register 6 includes circuit stages SR0,..., SR
□, and each of these circuit stages SR,...
The output of SR,,□ is the transistor QAo e...
・C connected to the gate of eQ46U, and each transistor QAO*...The drain t or source of IQAill is connected to the data bus DB. Furthermore, each circuit stage SR of the shift register 6.

......-8Rs□X can be preset from the :1 ram decoder 7.

In the video RAM of FIG. 1, as shown in FIG. 2, the serial read signal "l" is at a low level at time t, and the row address RA is applied.
When the row address stroke signal RAS becomes low level, the row addresses P and A are input to the word decoder 2, and a high level word line selection signal is applied to the selected word line WL. This allows Word! Each memory cell MC connected to 91WL,...=MC
The data from 1t□ continues to be output to each bit line BL,...
..., output to BLllll. Then, at time t2, the clock φ.

is high level and the transistor Qot...5
Qstt is turned on. As a result, each memory cell M
C0゜...-The read signal from MCaxt beeps)fjlBLo.

......, each latch DL via BLssr warehouse
,,......

Set to DLSII. On the other hand, for example, at time t, the column address strobe signal Cτ1 is set to a low level and the column address CA is input to the column decoder 7.The 0co2m decoder 7 decodes this column address CA and, according to the result, sets the shift register 601. Set the circuit stage, for example, SBi t - for example, 11'. As a result, the transistor Qai is initially turned on, and the ratte DL
The read data from memory cell MC1 stored in i is serially output data D out via data bus DBt-.
Since the register 6 (0 shift outputted as (s)) is sequentially shifted by the serial clock SRC shown in @2, the output of the circuit stage S R,+ becomes high and becomes a high pulse, and the transistor Q is turned on and the latch DL
The contents of l+1 are output. In this way, the data is sequentially stored in each latch and output in series. That is, in the video RAM of FIG.
Serial reading can be performed sequentially from the read start bit specified by , and the read start bit can be arbitrarily selected by setting the column address CA input to the column decoder 7 (L-).

FIG. 3 shows an example of a detailed tri circuit of the shift register 6 in the video RAM shown in FIG. The shift register in the same figure is a patent application filed in 1788-172, which was previously filed by the present applicant.
1J No. 96, each circuit stage is composed of four simple circuits consisting of only three transistors and one capacitor, but detailed explanation thereof will be omitted. Note that the signal φ. and φ are two-phase clock pulses, which can be created, for example, by using the well-known circuit technology of the serial clock SRC controller described above.

Figure 4 schematically shows a video RAM according to another embodiment of the present invention. In the video RAM shown in FIG. 1, not only serial reading is performed via the data bus DBt in the video RAM shown in FIG. That is, the shift register 6 performs a shift operation from the circuit stage set by the column decoder 7, and the output of each circuit stage of the shift register 6 causes the corresponding gate transistor Q. ,...IQAltll is turned on sequentially from the specified one, and the human data Din(a)t
-Write to each latch sequentially. Thereafter, the clock φ is set to a high level, for example, and the transistor Q0.・・・・・・5Qs
stt" is turned on, each latch L9 DL0...
..., the data temporarily stored in DL, □1 is connected to the selected word MWL and the friend memory 7 MC,...
, 0 is written in parallel to MC5tt. In this way, data can be input serially from any bit.
Write operations can be performed. - Fifth- is related to yet another embodiment of the present invention.
AMt-indicated. The video RAM shown in FIG. 1rrI is connected to a data bus D B (f
) and this data bus DRσ) and each latch DLO,
. . ., DL, , □, write gate transistors Ql @ e . . . , Q□1□ are added. and a pair of transistors Q, each connected to the same latch. Work Q. ,・Old・・＊
Qaitt and Q□, , Ia are controlled by the outputs of circuit stages SR, . . . , 5Rsts of the shift register 6, respectively. The other parts are the same as the video RAM shown in FIG.

In the video RA"M of FIG. 5, each latte DL0
. . . Serial read and serial write operations can be performed in parallel via DLs□1. That is, the shift register 6 sequentially selects transistors QA, QAi+1*, etc., for example.

Qhm□1lQA<1#... is turned on, and each latte DL.

D L 144 ,...-D LaI3- D
The read data from Lo-, old, etc. is sequentially output in series via the successive output data bus DB(0)t-. The two outputs of each circuit stage of the shift register 6 are write gate transistors Q□.

What is supplied to Qml+t +... is the protruding gate transistor QA1 #QAt+s...
It is designed to be output with a slight delay from what is supplied to ....

For example, in the circuit stage SR1, the signals SS and t supplied to the gate of the transistor Qat are output first, and the signal SSI is supplied to the gate of the transistor Q□ with a slight delay.
, is output. Therefore, each transistor Q□'
Qll+1 m... is the transistor Q□*
Qal+x *...It turns on with a little delay, and the corresponding latte D L i , D Ll +1 m...
. . . First, data is read from the data bus DB(I), and then data is written serially from the data bus DB(I). In this way, serial read operations and serial write operations can be performed in parallel.

FIG. 6 shows a video R according to still another embodiment of the present invention.
AMt-indicated. In the video RAM of the same figure, there is a butterfly, and a read gate transistor Q, similar to that of FIG. ,
・・・・・・＊Qhs□ゎReading data bus D
B (0), write gate transistor Q1°.

...* Qms*t and a write data bus D B (I). However, shift register 6
The output of each circuit stage is l system, and one circuit stage, for example, the output SS1+1 of SRs+x corresponds to the output DL,+
, read gate transistor QA1+ connected to
1 and a write gate transistor Qms corresponding to the previous stage latte DLi. The other parts are the same as the video RAM shown in FIG.

In the video RAM shown in FIG. 6, data is read from one latch, for example, D L t's, and data is written to the preceding latch, for example, DLi, at the same time. Therefore, the timing of the serial write operation is the same as that of the serial read operation. Although the timing is delayed by one clock period, the output of each circuit stage of the shift register 6 is 1 clock period.
The circuit is simpler than the one shown in FIG. 5 because it only needs to be a system. 7 shows a video RaM2 according to still another embodiment of the present invention. The same video RAM has 80 stages of shift registers as the video RAM in each of the above embodiments.
The output of one circuit stage controls the readout gate transistors for two consecutive bits. Furthermore, two systems of serial data output data buses DB, DB, and DB are provided, and a selection circuit 10 is provided for selecting one of these data buses DBo=DB□. The column decoder IO for presetting data in the shift register 8 receives good signals except for the lower 1 bit of the column address CA mentioned above, and sets, for example, 1 of the 256 circuit stages of the shift register 8 to a high level. Udo.

The shift register 8 is shift-controlled by, for example, a clock frequency-divided by 2 of the serial read clock 5RCe in each of the aforementioned embodiments. Furthermore, the column decoder 11 applies a column selection signal CLt- to the selection circuit 9 using a signal similar to the shift clock applied to the shift register 8. Therefore, the column decoder 11 is composed of seven lip-flops that divide the serial read clock SRC into two.

In the video RAM of FIG. 7, data from each mesori cell MC, ..., MCHI is written to each latch DL, ..., DLs*t in the same manner as described above. It will be done. Then, two adjacent latches are connected to the data bus DB0. and connected to DBl. For example, if the output of circuit stage SRi is at a high level, transistors Q□ and QAl+1 are both on, and the outputs to latches DLi and DL,+1 are respectively data bus DB.

and transferred to DBt. The selection circuit 9 converts the read signals output to the data buses DB and DB into the control signal CL from the column decoder 11.
Therefore, it is selectively output as the next output data Dout(a). According to this embodiment, the operating speed of the shift register 8 can be reduced to half that of each of the above-described embodiments, so there is a margin in the operating speed of the shift register even when performing high-speed reading, and the circuit reliability is increased. FIG. 8 shows a video R according to still another embodiment of the present invention.
AMvi-show. The video RAM shown in FIG. 1 shares the column decoder 7 for serial access with the column decoder 3 for random access in the video RAM shown in FIG.
Therefore, in FIG. 8, each circuit stage SRo-... of the column decoder 3 and shift register 6 is
..., gate transistor Q, between the input of SR,2,. ,...*Qcsu are provided, and these transistors are, for example, latch DL,...
- A refined transistor Qoe that sets data in parallel to DLst□... Controlled by the same clock pulse φ3 as the clock that controls eQsxtt.

In the video RAM of FIG. 8, when performing a serial read operation, by setting the clock φ to a high level, for example, as described above, the transistor Qoe...
..., Q□1t- is turned on, and is connected to the selected word line WL, and the nine cells MC0, ....

Read data from MCIII to each latte DL,
.

......Set in DLsrt. Then, by the same clock pulse φ, the transistor Qco e・
・・・・・・．

Qcss□ is turned on and one of the circuit stages of the shift register 6 is set to, for example, %lI by data from the column decoder 3. Thereby, data from each latch is output in series according to the shift operation of the shift register 6. On the other hand, when a serial read operation is not performed, the clock pulse φ3 is not set to high level, so each transistor Qco *...IQ
csII is off, and column decoder 3 and shift register 6 are separated. Also, the transistor Q0. ......* Since Qllll is also off, the name latch DL0. ......, D Lstt is also the input/output gate 4, and the bit iBL is...
.

It is separated from BLsu. Then, the input/output gate 4 is controlled by the column address signal inputted to the column decoder 3, and the input/output gate 4 is connected to the selected word line WL and selected by the column decoder among the selected memory cells. Random access is performed. In addition,
A signal for presetting the shift register 6 and a signal for randomly accessing the memory cell array 1 are input to the column decoder 3 in a time-division manner. According to this embodiment, there is no need to provide a special column decoder for serial access, and the circuit configuration becomes simple.

(Effects of the Invention) As described above, according to the present invention, it is possible to perform a serial read operation and a serial write operation from any specified memory cell among multiple bit memory cells connected to a selected word line. , it becomes possible to cope with more sophisticated demands on video RAM.

[Brief explanation of the drawing]

1 is a block circuit diagram showing the configuration of a video RAM according to an embodiment of the present invention, FIG. 2 is a waveform diagram illustrating the operation of the video RAM shown in FIG. 1, and FIG. 3 is a diagram similar to that shown in FIG. 1. FIGS. 4 to 8 are block circuit diagrams showing the detailed structure of a shift register used in a video RAM according to still another embodiment of the present invention, and FIGS. The figure is a block circuit diagram showing the configuration of a conventional video RAM, and Figure @10 is a waveform diagram for explaining the operation of the video RAM in Figure 9.el: memory cell array, 2: word decoder, 3.7 .10.1
1: Column decoder, 4: Input/output gate, 5.6, 8:
Shift register, 9: selection circuit, h'i Co , -
・”, MC811: Memory cell, BL, . . . . * BL511: Bit line, WL: Word green, DL, . ”・”' * D LS l 1: Latch, Qo *
・” ”・QIII ＊ QAOt・・・・・・＊ Q
assl* Qm. ,・・・・・・5Q1s□m QC
6e... QC11 Phoenix: Transistor.

Claims (1)

[Claims] A memory cell array having a plurality of memory cells each arranged at the intersection of a bit line and a word line, a data latch circuit provided corresponding to each bit line, and a data transfer between each bit line and the corresponding data latch circuit. a first gate means for controlling, a shift register capable of presetting data;
and a plurality of gate circuits connected to each data latch circuit, each gate circuit comprising a second gate means controlled by the output of a corresponding stage of the shift register, and optionally depending on the set state of the shift register. 1. A semiconductor memory device characterized in that serial data can be input or output from a start bit.