JPS6143737B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to binary number conversion, and more particularly to binary number conversion from a limited range of numbers to a single number for each selectable binary input having a relatively large range. It concerns giving an alternative binary number of one.

PRIOR ART Two data processing system control methods are commonly used in stored program data processing systems. One is to design a hardware sequential circuit, and the other is to design a control storage element (CSE) consisting of storage elements that store consecutive microinstructions to form a microprogram. Both interpret machine language instructions transferred from main memory to the CPU, determine the coding of the operation code portion of the instruction, and determine the functions to be executed, such as addition, subtraction, and multiplication. When using CSE, an operation code is typically used to address a storage element and access the first microinstruction of a microprogram that performs the function required by the operation code.

An excellent discussion of the form of CSE can be found in “IEEE
Transaction On Computers,”Vol.C−23,
No. 8, August 1974, P817 paper “Microprogramming: Perspective and
One form of CSE includes at least two types of storage elements and is used to store consecutive microinstructions to form a microprogram.The two types of storage elements are read-only storage elements. (ROS) and Writable Control Storage (WCS). ROS consists of binary bit patterns that constitute addressable microinstructions and never change during the operation of the data processing system. A data processing system In this case, the contents of the ROS storage element are fixed during the manufacturing stage of the data processing system.Another form of ROS is an erasable storage element that can store information as needed.
Once a microinstruction is written, it is not changed during a data processing operation. On the other hand, WCS
is a read/write addressable storage element in which microinstructions can be read or accessed after being dynamically stored in the storage element and can be dynamically changed as needed during data processing operations. . The types of CSE configurations mentioned above are described in U.S. Pat.
No. 3735363.

Modern data processing systems, including CSEs, also include main memory and a CPU that stores the programs and data that the system executes. Also included is a processor controller or console that provides basic control over the entire system. The processor loads the necessary information into the data processing system when it is powered on.
This is a function of the controller.

Main memory has a portion reserved for a number of system control data blocks containing all of the microprograms necessary to operate the system.
The reserved portion of main memory is not addressable by program instructions executed by the system, but is addressable by the CPU, which is originally under the control of microinstructions. To initialize the data processor, the processor controller transfers all microcode and other control information needed by the system to a reserved portion of main memory. By utilizing special data paths, the processor controller can pre-specify various registers, triggers, or storage arrays within the CPU, including the CSE's ROS if the ROS is a read-write storage element. Has the ability to store information. This ability is
Not required if ROS is a permanent storage element. If a WCS is given, the WCS is initialized by the processor controller, or at least the processor controller
All microcode used by WCS is stored in main memory.

CSE's ROS is typically used for frequently used microcode. ROS is structurally dense and fast, but it is expensive compared to WCS. As data processing system design advances, all microprograms are written requiring frequent processing functions, and ROS storage elements are used to store the fixed bit patterns needed to provide the ordering of microinstructions. Manufactured by. It is often discovered during the data processing system design stage, or after the design is complete, that there are errors in the existing ROS microinstructions. Occurs after the entire data processing system design has been completed and microinstruction errors have been corrected
Another type of ROS error is due to a permanent failure in the ROS hardware equipment. Additionally, the microcode that is permanently stored in ROS is initially created by writing known characteristics, functions, and instructions that are performed during the data processing system design phase. Newly defined program instructions that require new characteristics, changes in functionality, or changes to the ROS bit pattern require lengthy and expensive processing that systems already in use cannot easily handle. cannot be changed to

SUMMARY OF THE INVENTION A primary object of the present invention is to provide a binary replacement device that creates alternative main memory addresses for the addresses of defective microinstructions in ROS. Main memory address may be defective ROS
One of the relatively small address areas set aside in main memory as a replacement microinstruction for the relatively large number of microinstructions stored in the memory.

The present invention is utilized in modern data processing systems that include main memory, a CPU, a processor controller, and a control storage element (CSE).
The CSE includes read-only storage (ROS) and writable control storage (WCS) as microinstruction storage.
ROS has a predetermined number of addressable microinstructions. WCS essentially functions similar to the high-speed buffer or cache storage that exists between main memory and the CPU in many data processing systems. That is, the WCS has a small number of microinstructions out of all the microinstructions that can be stored in an area reserved in main memory for microcode. The WCS uses main memory addresses, which are used to access main memory to transfer groups of microinstructions to the WCS, to identify and locate microinstructions in the WCS, including a complete address directory. It is an associative memory. Since the WCS has limited capacity, an algorithm is implemented to replace least recently used (LRU) microinstructions. new microinstructions from main memory
Once transferred to the WCS, the replacement algorithm identifies the portion of the WCS to be replaced with a new group of microinstructions. WCS from main memory if necessary
The dynamic transfer of microinstruction groups to is similar to data transfer between an input/output device and main memory,
This is called “paging”. Therefore, using WCS in the manner described above may be renamed pageable control storage (PCS).

A storage element called a stop array contains a single bit location associated with each addressable microinstruction in ROS. When an error is found in the operation of a particular microinstruction read from ROS, the maintenance personnel provides the necessary information to the processor controller to change the relevant bit position in the stop array to a binary one. The stop array is accessed by the same address of the microinstruction used to access ROS. Execution of the defective microinstruction is blocked when the corresponding bit position is fetched and a binary 1 is detected.

In response to a stop signal from the stop array, the address of the defective microinstruction in the ROS is utilized in the address replacement apparatus of the present invention to provide an alternate address addressing a location in main memory of the microinstruction in place of the defective microinstruction. .

Implementation and updating of the address replacement system is easily accomplished in accordance with the present invention by providing two readily available storage arrays each having 256 addressable locations of 8 binary bits. The two storage arrays are addressed by first and second portions of the input binary number, each representing the address of a ROS microinstruction. Only ROS addresses that match the address of the defective microinstruction indicated by the stop array require replacement addresses. Once a defective microinstruction in ROS is determined by the maintenance personnel, a matching main memory address is determined, and the first and second parts of that address are assigned to the first and second memory locations according to the input binary numbers. Stored in the addressed location of the array. The combination of the outputs provided by the addressed locations of the two storage arrays produces the necessary main storage addresses for use by the pageable control storage addressing system.

FIG. 1 is a block diagram illustrating the relationship between a processor/controller 20, main memory 21, and control storage element (CSE) in a modern data processing system. Only the portions of CSE necessary for understanding the present invention are shown. The CSE includes a control store data register (CSDR) 22 that stores microinstructions received on line 23 from either read-only control store (ROS) 24 or pageable control store (PCS) 25 on each cycle.

Each microinstruction stored in CSDR 22 includes a number of control fields 26 that, when decoded, control data flow, logic, and operations in the data processing system.
In many modern data processing systems that utilize CSE, each microinstruction also contains the information necessary to sequentially address the next microinstruction.
The address of the "next microinstruction", often referred to in the literature as the "next address (NA)", includes bit positions 0-13 of CSDR 22. To give the microinstruction the ability to branch, each microinstruction also has a branch control field X27 and a branch control field Y2.
Contains 8. Branch control fields 27 and 28 are coded to select a particular machine state for data processing and provide coded information for microinstruction branches. The branching function is disclosed in detail in the related cited patent No. 2 mentioned above. Branch information appears on line 29 in Figure 1, selecting one of the four microinstructions addressed and accessed from either ROS 24 or PCS 25, and forwarding the selected microinstruction on line 23 to CSDR 22. do.

A microprogrammer who is creating a series of microinstructions for a data processing device must code each microinstruction in CSDR22 and write it to ROS24 or PCS2.
It has the ability to be addressed and accessed from any of 5. The above selection is made by the state of the NA bit position 0. The binary “0” makes the rest of the NA bit position valid for address decoding 30.
The ROS 24 is accessed and read. PCS by binary “1” in NA bit position
Address decoding 31 associated with 25 becomes operational.

When a signal is sent on line 32 indicating that NA bit position 0 is a binary "0", gate 33 is enabled;
NA bits 1-13 are transferred over line 34 to address decoder 30 of ROS 24. When a signal is sent on line 35 indicating that NA bit position 0 is a binary "1", gate 36 is enabled and NA bit 1 is
-10 is transferred through line 37 to pageable address directory 38. The signal on line 35 also enables gate 39 and NA bits 11-
13 is transferred over line 40 and becomes part of the address used in address decoding 31 of PCS 25. The remainder of the addresses for use in address decoding 31 of PCS 25 are transferred on line 41 from encoding device 42 associated with pageable address directory 38.

The pageable address directory 38 is
The replacement algorithm provided by the LRU device 43 works correctly. The functions of pageable address directory 38, encoding device 42, and LRU device 43 are disclosed in detail in the related cited patents 3 and 4, cited above.

In the main memory 21, the area 44 is stored in the PCS 25 as necessary.
Reserved for microcode transferred to Reserved area 44 is loaded with microcode from processor controller 20. Each time an amount of microcode is transferred from main memory 21 to PCS 25 on line 45, main memory 21 is addressed by address decoder 46 and transferred to PCS 25 on line 45 of 512 consecutive 8-bit bytes. do. The 512 bytes are arranged to provide 32 microinstructions, and the 32 microinstructions are identified as a "line" of microcode.

Depending on how NA bits 1-13 are arranged, NA bits 11, 12 and 13, along with the last two bits provided by the XY branch function, identify individual microinstructions in a line of 32 microinstructions. The remainder of the NA bits are arranged to provide segment and row identification within the segment. That is, NA bits 1-5 can identify 32 segments of microcode, and NA bits 6-10 can identify 32 lines within each segment of microcode. The addressing capabilities of NA bits 1-13 and XY branch bits are reserved area 44.
It provides an addressability of 32K (K=1024) microinstructions that can be stored in the memory. The capabilities utilized in the preferred embodiment of the present invention are below these capabilities.
Specifically, ROS24 is designed to permanently store 8K microinstructions. Therefore, while address decoder 30 is shown receiving 13 NA bits,
Only one is required to provide access to one of the 8K microinstructions with XY branch selection.

The PCS 25 is arranged as shown in FIG. 1 and contains 32 lines of microcode, totaling 1K microinstructions. In accordance with the disclosures in Related Cited Patents 3 and 4, each of which specifies a pageable main memory address.
NA is a pageable address as shown in line 35.
Start an associative search in the directory 38,
Determine which line of PCS 25 contains the microcode line being addressed. If the sought row is stored in the PCS 25, one of the associated registers in the pageable address directory 38 will indicate a match and the match will be encoded by the encoder 42 to identify the correct row in the PCS 25. The five address bits necessary for selection are provided on line 41. NA bits 11-13
The remainder is transferred on line 40 to address decoder 31, which selects a branch group of four microinstructions. The particular microinstruction in the branch group that is transferred to CSDR 22 on line 23 is selected by XY branch decode 29.

If the pageable microcode lines identified by NA bits 1-10 are mismatched in pageable address directory 38, a signal on line 48 representing a mismatch is asserted at gate 49.
NA bits 1-10 are transferred to the address decoder 46 on lines 50 and a transfer to the PCS 25 of the 512 bytes containing the requested microcode line is initiated on line 45. The LRU device 43 is the related cited patent 4.
According to the disclosure in
Select the row. selected by LRU device 43
Next address bits 1-1 by row of PCS25
A zero is stored in the associated register of the pageable address directory 38.

FIG. 2 is a block diagram containing certain portions of the apparatus disclosed in FIG. 1, and the same reference numerals have been used. The additional structure of CSE in modern data processing systems is shown in Figure 2. Current address register 51 stores the complete address including the XY branch bits used to access the microinstruction for transfer to CSDR 22. When the next address portion 52 of each microinstruction is transferred to the address decoder 30 or 31 shown in FIG.
Transferred to current address register 51 on line 53. Therefore, the current address register 51 is
Holds the address of each microinstruction transferred to and stored in the CSDR 22. Another register shown in FIG. 2 is auxiliary address register 54, which is utilized in modern data processing systems to receive control storage address information from some other source on line 55 during CSE sequencing.

Additional inputs to the CSE have been added to the description of FIG. 2 in accordance with the related cited patent 1, which discloses the concept of first cycle control storage in the CSE.
That is, in the first cycle of machine language instruction execution, the operation code of the machine language instruction is used to access a control storage element that is used only for the first cycle of machine language instruction execution. The OP CODE portion of the machine language instruction is received at line 56 in FIG. Gate 58 is enabled when the signal on line 57 represents the first cycle of machine instruction execution.
Transfer the OP CODE bit to the current address register 51 on line 59. Current address register 51 therefore stores an indication of the OP CODE represented on line 56 during the cycle in which the microinstruction accessed in the first cycle is stored in CSDR 22.

As previously mentioned, some situations require a change in the normal order of microcode previously written and stored in the ROS of FIG. Such situations include permanent error detection of microinstructions, where an individual microinstruction is correct but causes an error condition in other hardware in the data processing system that requires correction; is defective or contains machine language instructions that the data processing system was not originally designed to execute.
Including when required to respond to OP CODE. In all of the above situations, it is a primary objective of the present invention to prohibit the microinstructions transferred to CSDR 22 from functioning properly and replace them with microinstructions accessed from PCS 25 of FIG.

The device of the present invention that achieves the above objectives includes a first cycle stop array 60, a ROS stop array 61,
and an address replacement device 62. array 60
and 61 each have a single bit storage location for each microinstruction that can create an error condition. If the OP CODE received on line 56 has the standard 8 bit locations, then the first cycle stop array 60 has 256 bit locations. In a preferred embodiment of the invention, ROS24 is
Storing 8K microinstructions, the ROS stop array 61 therefore consists of 8K bits of storage locations.

When either the first cycle stop array 60 or the ROS stop array 61 is accessed, the next address portion 52 of the line 63 is gated by the OP CODE on line 59 or the signal line 32 indicating the address of ROS 24. Thus, a binary "1" in the accessed bit storage location will provide a stop signal on line 46 indicating an error condition and will cause the control field of the microinstruction accessed from either the first cycle control store or ROS 24 of FIG. 26 is prohibited by line 65.

Processor controller 20 of FIG. 1 is utilized during initial setup of a data processing system and
Provide the cycle stop array 60 or ROS stop array 61 with the correct pattern of binary "1s" and binary "0s." This information is created by maintenance personnel and is
7, and 68 into the array. When it becomes necessary to change microinstruction execution, the correct bit pattern is created by the maintenance personnel for the storage of the stop array at the address associated with the microinstruction that is to be inhibited.

When a stop is indicated on signal line 64, the address stored in the current address register 51 of the microinstruction to which the replacement microinstruction is to be accessed is passed through gate 70 to address substitution device 62 on line 69. will be forwarded to. Address substitution device 62 converts the address stored in current address register 51 into a main memory address and
is transferred to the auxiliary address register 54. As part of the address translation process, bit position 0 of current address register 51, shown as a binary "0" at 72, is transferred to bit position 7 of auxiliary address register 54.
It is converted to a binary "1" indicated by 3. Thereafter, the address stored in the auxiliary address register 54 -
The main memory address - is transferred on line 74 to pageable address directory 38 to begin normal access functions of PCS 25 as described in connection with FIG.

Processor controller 20 in FIG.
6 and 75 to provide the address of the microinstruction - located in main memory in FIG. 1 - to replace the defective microinstruction during the initialization process. The main memory address on line 75 associated with the address of the defective microinstruction in current address register 51 is replaced by address replacement device 62.
After being stored in , it is generated on line 71 whenever the address of the defective microinstruction is utilized.

FIG. 3 illustrates several alternative methods of creating main memory addresses for replacement microinstructions as inputs to address replacement unit 62 of FIG. One method requires each 8K ROS 76 address to provide an associated main memory address creating an 8K storage patch area 77. In the manner described above, the only requirement on address substitution device 62 of FIG. be. In this method, the address substitution device 62 becomes very simple, but
Main memory address space is extremely wasteful, and 8K microinstruction addresses must be permanently reserved in main memory.

Another method, shown in FIG. 3, utilizes the next address (NA) bit 53 to address an 8K address permutation table 78. i.e. 8KROS
has an addressable entry in address substitution table 78 only if the respective address provides access to the defective microinstruction. Therefore, the address replacement device 62 of FIG.
not only detects defective microinstructions, but also
gives the ability to reserve only one location in main memory for each defective location in ROS, as shown in .
By including the relatively expensive address substitution table 78, a great deal of compression can be achieved in main memory 21 while allocating very little space to alternative microinstructions.

Good results for address replacement device 62 of FIG. 2 are represented at 80 and 81 in FIG.
8KROS address space 80 is memory patch area 8
Compressed to 1. This is a compromise between the amount of main memory that needs to be reserved for replacement microinstructions and the cost and efficiency of the address translations performed by address replacement unit 62 of FIG. As shown, the 8KROS address 80 is 0000−
FFFF (each location consists of 4 binary bits)
represents the hexadecimal number), and the memory patch area 8
1 is the total in the range of main memory address F800-FFFF
Indicates a 2K microinstruction address. Although hexadecimal representation is widely used, an individual representation of the four binary bits representing a hexadecimal number is shown in FIG.

FIG. 4 shows the address substitution device 62 of the present invention, located between the current address register 51 and the auxiliary address register 54 shown in FIG. Address substitution device 62 consists of a first translation array 82 and a second translation array 83. The format of the address to be translated includes the first cycle format shown at 84 or any ROS address shown at 85. The first cycle microinstruction address contains an 8-bit OP CODE in bit positions 4-11. Also, the mode bit in bit position 12 of 84 represents the presence of an OP CODE in a data processing system having, for example, two different instruction sets. 84
The remaining bit positions are binary "0"s. ROS address range 0- at bit position 3-15 of 85
Represents 8K. Bit positions 0-2 are all binary "0" and represent the address of the ROS.

Translated addresses are inserted into auxiliary address register 54 from first and second translation arrays 82 and 83. Bit positions 0-2 are in register 51.
It represents a ROS address and is converted to a binary “1” to represent a pageable address in main memory, as shown in Figure 1.
Contains the prefix value used by the PCS 25 access device.

Compression of main memory addresses is performed by first translation array 82 and second translation array 83. The two arrays are addressed using first and second portions of address information in current address register 51, respectively. That is, the first translation array 82 is addressed by bit positions 3-9 and the second
Translation array 83 is addressed by bits 10-15. Each addressed location in arrays 82 and 83 is given the correct main memory address as determined by maintenance personnel and received from processor controller 20. First conversion array 82
The output of the second translation array 83 provides an alternative address in bit positions 3-9, and the output of the second translation array 83 provides an alternative address in bit positions 10.
-15 gives alternative address information. The alternate address provided in auxiliary address register 54 is transferred on line 74 to access the pageable address directory shown in FIG.

In FIG. 5, it is determined by maintenance personnel that when a malfunction is found at an individual ROS address, the first translation array 82 and the second translation array 83 of FIG.
The theory of information stored in is explained.
On the left side of FIG. 5, under the title "Current Address", an example of 16 ROS addresses from 0 to F in hexadecimal notation is shown.
The ROS address designation is indicated by the left bit position, which is all binary "0". Defective microinstruction operations at addresses "2", "9" and "D" are indicated by stars. Under the heading "Pageable Addresses, Uncompressed Case", it is stated that address translation methods in which only the most significant binary bit position is changed must reserve 16 main memory addresses for alternate microinstructions. shows. On the right side of FIG. 5, under the heading "Compression Case", the first translation array 82 and the second translation array 83 compress the number of main memory addresses that must be reserved for alternative microinstructions. It means to be done.

As shown in FIG. 5, the first translation array 82 is addressed by the first two bits of the current address;
The second translation array 83 is addressed by the next two bits.

The error condition indicated by address number "2" causes translation arrays 82 and 83 to be addressed as shown, providing a hexadecimal "0" as the translated address output. The next defective address is indicated at address "9". The first and second arrays 82 and 83 are given translation addresses by the maintenance personnel and produce a hexadecimal output "1".

When a third defective microinstruction is found at address "D," the translation address information provided by the maintenance personnel is an output that is distinct from the output provided when translation arrays 82 and 83 are accessed at defective address "9." must be given. The first translation array 82 is provided with the information necessary to create a unique translation address. This is the first 2
This is done by changing the location in first translation array 82 addressed by one address bit to provide an output of "01". The translated addresses provided by translation arrays 82 and 83 then yield a pageable address of hex "5" for the defective address "D" in ROS.

Address substitution device 62 operating according to FIG.
achieves unique main memory address conversion and compression efficiently and at low cost. This was due to the recognition that only a subset of 8K addresses required replacement microinstructions. Conversion array 82 by 8K conversion table giving 16 bit output
The significant reduction in size and price of the 83 and 83 is quite obvious. Arrays 82 and 83 are each readily available, low cost 256.times.8 memory chips that provide sufficient conversion power for the number of microinstructions that actually require replacement.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main components of a control storage element (CSE). FIG. 2 is a block diagram showing the addition of the present invention to a certain portion of FIG. 1 and its relationship. FIG. 3 shows main memory address compression using the address replacement device of the present invention. FIG. 4 is a block diagram of the address substitution device of the present invention. FIG. 5 is a diagram illustrating a theoretical explanation of main memory address compression resulting from the address replacement device of the present invention. 20...processor controller, 21...
Main memory, 22... Control storage data register, 2
4... Read-only control memory, 25... Pageable control memory, 30, 31, 46... Address decoding device, 38... Pageable address directory, 42... Encoding device, 43... LRU device, 62...Address replacement device.

Claims (1)

[Claims] 1 consisting of a first conversion array that receives a predetermined upper part of an input binary number made up of a plurality of bits, and a second conversion array that receives a predetermined lower part of the input binary number; A binary number permutation device, characterized in that the range of output binary numbers represented by the output from the second conversion array and the output from the second conversion array is compressed.