JPS6139194B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method and apparatus for creating a constant period clock signal, and more specifically, uses a constant period reference signal that is longer than the period of a desired constant period clock signal, and uses a constant period reference signal that is longer than the period of the desired constant period clock signal. The present invention relates to a method and apparatus for creating a constant period clock signal from a short period clock signal.

Conventionally, the operating timing of a data output device (for example, a printer) connected to a computer or measuring device is given to the computer or measuring device by the data output device, and data is output according to the timing signal. was the norm. The reason for this is that the operating speed of the data output device is variable, the operation timing period does not match, and so on, so that data output to the data output device is performed asynchronously with the clock signal of the computer or measuring instrument.
In other words, it was necessary to output data from a computer or measuring device by receiving a status signal from the data output device.

For example, when an electronic desktop calculator (hereinafter referred to as a calculator) is equipped with a dot printer that prints by colliding a needle with the printing paper while moving the head perpendicular to the feeding direction of the printing paper, a print command from the calculator to the dot printer is given. For pulses, the calculator receives a print timing signal and, in some cases, a pulse width regulation signal for print command pulses from the dot printer, and in response to these signals, the calculator outputs print command pulses (data output) to the dot printer. He had a method.

However, due to physical limitations within the dot printer of the device for generating the print timing signal and the pulse width regulation signal of the print command pulse from the dot printer, and the high proportion of the cost of the dot printer, these print timing signals and print command pulses are A dot printer that does not have a pulse width regulation signal generating device is conceivable. In such a dot printer, the head starts moving from the edge of the printing paper and gives a print start signal to the calculator when it enters the print area. Within the printing area, the head moves at a constant speed. When the calculator receives the print start signal,
Thereafter, it outputs a print command pulse of a constant width to the dot printer at the print timing it creates within the print area. In order to improve printing quality, the period and pulse width of the printing command pulse must be constant.

In this case, if the print command pulse is to be created based on the calculator's arithmetic control clock, the calculator's arithmetic control circuit is currently implemented as an LSI, the clock oscillation circuit is not adjusted, and there are cycle fluctuations due to the environment, which is the worst case scenario. Since the deviation from the cycle setting value (target value) reaches ±50%, as a result, the cycle and pulse width of the print command pulse also fluctuate at the same rate. In order to reduce this fluctuation, it is difficult to adjust the clock oscillation circuit when assembling the calculator, or to replace it with a high-quality clock oscillation circuit that is resistant to environmental changes, due to the cost of the calculator.

SUMMARY OF THE INVENTION An object of the present invention is to provide an inexpensive method and apparatus for creating a constant period clock signal that is the basis for making the period and pulse width of the print command pulse constant.

Still another object is to provide an inexpensive method and device for creating a constant period clock signal, which is the basis of not only dot printers but also equipment that requires a constant period operation timing signal and a constant width timing signal. be.

Hereinafter, the system and apparatus of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of the method and apparatus of the present invention, and FIG. 2 is a timing chart thereof. Reference numeral 1 denotes an oscillation source such as a clock oscillation circuit for arithmetic control of a calculator, and for the following explanation, it is assumed that the oscillation circuit has an oscillation frequency of ₀ =100 KHz. It is assumed that this oscillation frequency gradually changes around 100KHz. 2 is an n frequency divider circuit where n=32. 3 is the signal source of the reference signal generator, and the period Tr ₀ =
The AC wave is 20mSsec (frequency = 50Hz). 4 is a reference signal generating device which converts the reference signal (for example, a pulse signal) into a period Tr (here Tr=
mTro/2; m = integer). 5 is a main counter, 10 is a constant period clock signal output circuit, 6, 7, and 8 are examples of the contents of 10, 6 is a memory register, 7 is a second counter, and 8 is a zero detection circuit for the contents of the second counter. , 9 is a control circuit for the above device.

First, a certain period Tr of the reference signal (for the following explanation, Tr = Tr ₀ = 20 mSec; m = 2 is assumed).
The 100KHz clock signal from oscillation source 1 is
Assume that the frequency is divided by 32 by the frequency dividing circuit and counted by the main counter 5.

(1) The contents of the main counter 5 are transferred to the memory register 6 by the reference signal from the reference signal generating device 4, and immediately after that, the main counter 5 is reset to zero, and the contents are immediately transferred to the next cycle Tr of the reference signal. The incoming main counter 5 starts counting.

(2) The contents of the memory register 6 are transferred to the second counter 7.
, and immediately starts subtraction in the second counter 7 using the 100 KHz clock signal from the oscillation source 1. When the content of the second counter reaches zero, the zero detection circuit 8 outputs a zero detection signal (pulse signal).

(3) The operation in (2) is based on one period of the reference signal.
is repeated until the end. When the next reference signal appears, the operation moves to (1), and then
Operations (2) and (3) are performed.

The zero detection signal becomes a constant period clock signal.

Now, the reference signal period is Tr, the frequency division of the n-divider circuit 2 is divided by n, and the average value of the clock frequency of the oscillation source 1 within i-th (i: integer) reference signal period Tr is _0. , oscillation source 1 within the i+1th reference signal period Tr,i+1
The average value of the clock frequency of ⁰ +△ ₀ (△
₀ : very small), the content N of the main counter 5 after Tr,i ends is Tr,i=Tr+i, N= ₀ Tr/n (1) If the zero detection signal period is Tz, then Tz≒N/( ₀ +△ ₀ )≒N/(1-△ ₀ / ₀ )/ ₀ =Tr(1-△ ₀ / ₀ )/n (2).

In other words, if ₀ is constant, △ ₀ = 0
Therefore, the zero detection signal period Tz is a number that is related only to Tr and n and is unrelated to ₀ , and a signal can be obtained at a constant period Tr/n regardless of ₀ .

Also, even if ₀ changes gradually, for example, considering the CR oscillator of a calculator, unless the environment (e.g. ambient temperature) changes suddenly and greatly, △ ₀ / ₀
Assuming that Tr=20 msec, Tz will be at most 10 ^-4 or less before and after 20 msec, so Tz is considered to be sufficiently constant within the practical range.

Now, assuming ₀ 100KHz, n = 32, Tr = 20msec, the content of the main counter 5 N≈62, the zero detection signal period Tz = 625μsec, and even if it is +100% of the target value when ₀ is set, N <125, so the main counter 5, meseri register 6, and second
Since the number of bits of the counter 7 is only 7 bits, the circuit size is not very large and the cost is low.

The biggest error factor (trouble) is, for example, when N changes from 62 to 63 or from 62 to 61 when ₀ happens to change by a few Hz. In that case, Tz suddenly becomes large at a certain moment. It's going to change. The amount of change △Tz is (2)
From the formula, △Tz≒△N/ ₀ ≒1/100KHz=10μ
sec, it is about 1.6% of Tz=625 μsec, and even if we consider using the zero detection signal as a timing signal for a dot printer, for example, it cannot be said to be fatal in terms of print quality.

If a CR oscillator with good temperature characteristics can be used from a cost perspective, the chances of the above trouble occurring will be further reduced.

Fluctuations in the commercial power supply frequency, which has a frequency of 50 Hz, can also be considered as an error factor, but the actual fluctuations are very gradual and are unlikely to cause any major trouble.

In the above explanation, ₀ = 100KHz, n = 32, Tr =
We have set it to 20msec, but the current situation is that ₀ takes various values depending on the LSI, and in reality it is ₀ for calculator LSIs.
is about 50KHz to 200KHz, and n also depends on the required value of Tz and required accuracy.
We also need to change.

In addition, the subtraction of the second counter 7 in FIG.
Although this subtraction is performed using a clock signal of ₀ = 100KHz, this subtraction may also be performed using a clock signal with a longer period obtained by dividing ₀ , or a clock signal obtained by multiplying ₀ with a shorter period than ₀ (or ₀
(original clock signal originating from).

Furthermore, the signal source 3 of the reference signal generating device 4 is supplied with various types of signals other than the AC wave from the commercial power supply, such as signals output at regular intervals from a magnetoelectric transducer, a photoelectric transducer, a piezoelectric transducer, or a mechanical contact. It will be.

Furthermore, in the above explanation, an example has been given in which the contents of the constant period clock signal output circuit 10 are composed of a memory register 6, a second counter 7, and a zero detection circuit 8 for the contents of the second counter, as shown in FIG. However, various other configurations are possible. For example, the third
As shown in the figure, the second counter (subtraction counter) in Figure 1 is used as a normal integration counter, and instead of a zero detection circuit, a signal is output every time the contents of the memory register and the second counter match. A match detection circuit is provided, that is, the memory register 11, the second
The counter (accumulation counter) 12 and the content matching detection circuit 13 may also be used.

Furthermore, as shown in FIG. 4, there is also a method in which the contents of 10 in FIG. Its operation is as follows. Instead of being transferred to the memory register 6, the contents of the main counter 5 of FIG. 1 are transferred to the second counter 14 and at the same time the third counter 15 is reset to zero. The contents of the second counter 14 are subtracted by the clock signal of the oscillation source 1, and at the same time the third counter 15 is incremented by 1 by the same clock signal. When the content of the second counter 14 becomes zero, a signal is output from the second counter content zero detection circuit 16, and at the same time, the content of the third counter 15 is transferred to the second counter 14 and the third counter 1
5 is reset to zero. Immediately after that, the above-mentioned subtraction of the second counter and addition of the third counter, output of the zero detection signal, transfer of the contents of the third counter to the second counter, and resetting of the third counter are repeated until the next reference. This will continue until the signal is given. In other words, the third counter 15 is used as a type of dynamic memory register.

A constant cycle output from the constant cycle clock signal output circuit 10 according to the timing chart shown in FIG.
An example of using the zero detection signal period of Tz as a print timing signal of a dot printer will be explained.

In the numerical example above, the period of the reference signal
Since Tr=20 mse and the frequency division number n of the n frequency divider circuit is 32, Tz=625 μsec, which is an appropriate value as the time for energizing the head solenoid of a dot printer. Generally, with current technology, energizing time =
If it is about 625 μsec, the time from when the head solenoid starts energizing until the needle collides with the printing paper and returns (1 dot cycle) is 2 to 3 times the energization time, which is 1.25 to 1.875 msec (2 Tz).
~3Tz) is an appropriate value. In other words, in Fig. 5, one period of the zero detection signal is used for the energization time (pulse width of the print command pulse), and the remaining two periods are rested, that is, one-third of one dot cycle is used to energize the head solenoid. This is an example when used for.

Not limited to dot printers, if you want accurate timing and pulse width, use the pulse width of the output pulse of the zero detection signal (extremely inaccurate) as shown in Figure 5.
It is noteworthy that it can be obtained by using only its period Tz instead of using .

Furthermore, when using the above-mentioned zero detection signal as the print timing signal of a dot printer, if a synchronous motor is used as the head drive source of the dot printer, the reference signal period can be calculated from equation Tz(2).
The moving speed of the head V and the commercial power frequency Tro Considering that is inversely proportional, the amount of head movement x in Tz time is
Tro) = constant, and therefore the amount of head movement within one dot cycle does not depend on the commercial power frequency, and regardless of whether the commercial power frequency is 50Hz or 60Hz, it will fluctuate to some extent in the vicinity of 50Hz or 60Hz. This means that the same size can be printed regardless of the size of the print, which is a great advantage in terms of print quality. However, in this case, the lower the frequency of the commercial power supply, the slower the printing speed and the longer the energization time to the head solenoid (the pulse width of the print command pulse), so care must be taken when designing the head solenoid.

As explained above, it is very inexpensive, and if you incorporate the circuit into LSI, it will be even cheaper.
It is possible to create a constant period clock signal from an oscillation source with a gradually changing clock oscillation frequency, which is the basis of a device that requires a constant period operation timing signal and a constant width timing signal. can.

As is clear from the description, the effect of the above invention is that it can eliminate the need for an operation timing detector for the equipment, and especially in the case of dot printers, it eliminates the need for a print timing detector, which accounts for a large proportion of the cost and takes up space. This can greatly contribute to reducing the cost of dot printers.

Although the device of the present invention has been explained above mainly using dot printers and calculators as examples, it is not limited to these, but can be applied to all devices and their controllers that require constant period timing signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating one example of the system and apparatus according to the present invention. DESCRIPTION OF SYMBOLS 1...Oscillation source, 2...N frequency divider circuit, 3...Signal source, 4...Reference signal generation device, 5...Main counter, 6...Memory register, 7...Second counter, 8... . . . zero detection circuit, 10 . . . constant period clock signal output circuit. FIG. 2 is an example of a timing chart of the system and device according to the present invention. 3 and 4 show different examples of the constant period clock signal output circuit 10 shown in FIG. 1. In FIG. 11...Memory register, 12...Second counter, 13...Content matching detection circuit, 14...Second
counter, 15...Third counter, 16...
Zero Detection Circuit FIG. 5 is an example of a timing chart when the constant cycle clock signal produced by the apparatus of the present invention is used as the basis for producing print command pulses for a dot printer.

Claims (1)

[Scope of Claims] 1. An oscillation source that generates a first periodic signal with a high frequency; a frequency dividing circuit that divides the first periodic signal from the oscillation source by n (an integer); and the first periodic signal. a reference signal generating device that generates a reference signal having a relatively lower and fixed frequency; a counter circuit that counts the output signal from the frequency dividing circuit for each cycle of the reference signal; The counted value is loaded into the counter circuit every cycle, and the first periodic signal from the oscillation source is counted until the counted value is reached. When the loaded value is reached, a match signal is output. 1. A constant-period clock signal generating device comprising: a circuit for outputting a constant period clock signal;