JPS6137870B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speed control device for an electric motor.

Conventionally, in a speed control device for an electric motor, a speed detection device is provided to detect the actual rotational speed of the electric motor. A large number of slits are provided at equal intervals on the same circumference of a disc, and a light emitting part and a light receiving part are arranged on both sides of the disc, and the rotation of an electric motor directs light from the light emitting part through the slits. A detection device configured to be intermittently detected by a light receiving section and generate a speed signal at a frequency proportional to the actual rotational speed of the motor is used, and the speed signal generation from the speed detection device The actual speed of the motor is compared with the desired set speed, and power is supplied or cut off to the motor according to the comparison result, and speed control is performed so that the motor speed reaches the desired set speed. was. The speed detecting device has a detection ability to detect the actual speed of the electric motor over a predetermined speed control range, and is configured to be suitable for driving the electric motor at a medium set speed within the speed control range. The structure of the speed detection device, for example, the number of slits, has been considered.

However, the generation cycle of the speed signal generated by the speed detection device becomes shorter as the speed of the motor increases. During the generation period, the operation of comparing the actual speed of the motor with the desired speed and the operation of controlling the power to the motor must be performed as described above, and the generation period is the minimum control operation allowed by the speed control circuit of the motor. When the time becomes shorter than the time, the speed control circuit cannot follow the speed signal and cannot operate normally. Therefore, it is necessary to limit the set speed of the maximum speed of the motor so that the minimum value of the generation period of the speed signal is longer than the minimum control operation time in the speed control circuit as described above. Conversely, the lower the speed of the electric motor, the longer the generation cycle of the speed signal becomes. Therefore, when driving the electric motor at a low speed, the period in which power is supplied to the electric motor and the period in which it is cut off becomes extremely long, and The actual speed of the motor fluctuates greatly, making the low-speed drive characteristics of the motor unfavorable. Therefore, the minimum set speed of the electric motor cannot be set unnecessarily low, and there is a limit in setting the set speed.

Due to the above circumstances, the speed control range of the electric motor, that is, the set speed range from low speed to high speed, becomes narrow, so it is not used in applications that require a wide speed control range, such as speed control devices for electric motors for industrial sewing machines. Therefore, the range of application of conventional electric motor speed control devices is limited.

SUMMARY OF THE INVENTION Therefore, an object of the present invention was to eliminate the above-mentioned defects, and to provide a speed control device for an electric motor that can accurately and reliably control the speed of an electric motor over a wide speed control range from low speed to high speed. It's about doing.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a speed control device for an electric motor embodying the present invention will be described below with reference to the drawings. 1st
The figure is an electrical circuit diagram of a speed control device for an electric motor. The desired rotation speed to be controlled is roughly divided into the speed range from low speed rotation to high speed rotation, and the command signal corresponding to the desired rotation speed is selected. a speed command circuit 1 that generates a speed command; a speed detection device 2 that detects the actual speed of the motor and generates a speed signal with a frequency proportional to the actual speed; Detection device 2
a frequency dividing circuit 3 that divides the frequency of a speed signal from the frequency dividing circuit 3; a time measuring circuit 4 that repeatedly performs a timing operation based on a command signal of the speed command circuit 1 each time an output signal from the frequency dividing circuit 3 is generated; and the time measuring circuit. a first control circuit 5 that sets a control state to supply or cut off power to the motor based on the output signal of the clock circuit 4 and the output signal of the frequency divider circuit 3; a second control circuit 6 that determines the duty ratio of a control pulse signal for low-speed rotation control in response to an output signal from the first control circuit 5; The selective supply circuit 7 selects one of the control pulse signals from the circuit 6 and effectively applies the selected control pulse signal to the switching circuit 8 that controls power to the motor. ing.

First, the speed command circuit 1 will be explained.
1 is an automatic reset type start/stop switch, and one terminal 11a is connected to the positive voltage +Vcc terminal with a resistor 1.
2, and the other terminal 11b is directly connected to the ground terminal (zero voltage terminal). FF
1 connects its input terminal T to the start/stop switch 11
This is a flip-flop circuit connected to the terminal 11a of the J-K flip-flop, and the terminals J and K of the J-K flip-flop are connected to a positive voltage +Vcc so that the output signal from the output terminal Q is inverted every time the start/stop switch 11 is pressed and released. They are connected to terminals and used as a T-type flip-flop. 13 is a monostable multivibrator that is triggered in response to the rise of the output signal SP4 from the output terminal Q of the flip-flop circuit FF1;
SP1 is the reset terminal RT of the OR circuit 23 of the frequency divider circuit 3 and the subtraction counter 27 of the timer circuit 4, which will be described later.
and is supplied to the AND circuit 17 of the speed command circuit 1. 14 is a rotary switch that can change and set the rotational speed of the DC motor M in five stages, and its common terminal 14a is directly connected to the ground terminal (zero voltage terminal);
b, 14c, 14d, 14e, and 14f are respectively connected to the next stage encoder 15. This encoder 15 indicates that when the rotary switch 14 is switched and connected to the terminal 14b, the rotation speed of the DC motor M is 6000 r.p.m., and when it is connected to the terminal 14c, the rotation speed is 4500 r.p.m. terminal 1
2000r・p・m when connected to 4d, terminal 14e
It outputs a code signal corresponding to each rotation speed so that it can be selectively controlled to 1000 r.p.m when connected to the terminal 14f and 200 r.p.m when connected to the terminal 14f.

16 is a memory circuit which receives a code signal corresponding to each rotation speed from the encoder 15 as an address input signal at an address input terminal ADS,
Outputs the memory contents in the specified address according to the code signal corresponding to each rotation speed to terminals MD1 and MD.
2. It is configured to output to MD3. In this embodiment, when the rotary switch 14 is set to the switching terminal 14b corresponding to the rotation speed of 6000 r.p.m., the memory circuit 16 outputs a binary value representing the decimal number "5" from the output terminal MD1. Frequency divider circuit 3 that generates preset signals in code format
A preset signal is supplied from the output terminal MD2 to the preset input terminal IN of the subtraction counter 21 of the clock circuit 4, and a preset signal in the form of a binary code representing the decimal number "300" is supplied to the preset input terminal IN of the subtraction counter 27 of the timekeeping circuit 4, which will be described later. At the same time, a code signal SP5 of "0" is supplied from the output terminal MD3 to the AND circuit 17 at the next stage.

Similarly, the rotary switch 14 is switched to the terminal 14.
When set to c, output terminal MD1 outputs a preset signal representing decimal number "4", output terminal MD
2, a preset signal representing decimal number "335", and output terminal MD3 a code signal SP5 of "0", and when rotary switch 14 is set to switching terminal 14d, output terminal MD1 outputs 10.
Preset signal representing base number “1”, output terminal
A preset signal representing the decimal number "300" is sent from MD2, a code signal SP5 of "0" is sent from the output terminal MD3, and when the rotary switch 14 is set to the switching terminal 14e, the output terminal MD1 outputs a
A preset signal representing a decimal number "0", a preset signal representing a decimal number "300" from the output terminal MD2, a code signal SP5 of "0" from the output terminal MD3, and a switching terminal for the rotary switch 14. When set to 14f, the output terminal
A preset signal representing a decimal number "0" from MD1, a preset signal representing a decimal number "1500" from an output terminal MD2, and a code signal SP5 of "1" from an output terminal MD3 are sent to the subtraction counter 21, 27 and the AND circuit 17.

Next, the speed detection device 2 and the frequency dividing circuit 3 will be explained. Reference numeral 20 is a pulse generator that generates a speed pulse signal with a frequency proportional to the actual rotational speed of the DC motor M.
200 slits are provided at equal intervals on the same circumference of a disk (not shown) attached to the rotating shaft of
A light emitting diode is provided on one side of the disk, and a phototransistor is provided on the other side opposite the light emitting diode. As the DC motor M rotates, the phototransistor intermittently detects the light from the light emitting diode through the slit and generates a speed pulse signal with a frequency proportional to the rotation speed of the DC motor M. It's summery. The structure of the pulse generator 20, ie, the number of slits (200), is determined to be suitable for driving the DC motor M at a medium set rotational speed (1000 r.p.m.).

21 connects the pulse generator 2 to the counting input terminal DN.
It is a subtraction counter to which a speed pulse signal from 0 is supplied as a counting signal, and the preset signal representing a preset value P1 is supplied from the output terminal MD1 of the memory circuit 16 to its preset input terminal IN, and the speed pulse signal is In response to a falling edge, the preset value P1 is subtracted, and the counted contents are output to output terminals A, B, C, and D in the form of a 4-bit binary code. Further, the subtraction counter 21 has its output terminal A as its most significant bit output terminal, and its output terminal D.
is configured to output the count contents using the least significant bit as the output terminal.

22 is the output terminal A of the subtraction counter 21;
It is an AND circuit to which output signals from B, C, and D are supplied, and the output signal is sent to the next OR circuit 23.
The signal is supplied to the load terminal LD of the subtraction counter 21 through the subtraction counter 21. Based on the subtraction operation of the subtraction counter 21, the output signals from the output terminals A, B, C, and D are (1, 1, 1,
1) When it becomes, AND circuit 22 and OR circuit 2
3, an output signal of "1" is supplied to the load terminal LD, whereby the subtraction counter 21 is set to the preset value P1 and returns to the initial state, and the speed pulse from the pulse generator 20 is again output. Signal counting operation begins.

Reference numeral 24 denotes an OR circuit to which output signals from output terminals A, B, C, and D of the subtraction counter 21 are supplied, and the output signals are supplied to a NOT circuit 25 at the next stage. 26 is an AND circuit to which the output signal of the note circuit 25 and the speed pulse signal of the pulse generator 20 are supplied, and its output signal SP2 is connected to a load terminal LD of the subtraction counter 27 of the timekeeping circuit 4, which will be described later; It is supplied to the clock input terminal T of the flip-flop circuit FF2 of the first control circuit 5.

Note that in this embodiment, the memory circuit 16
2 representing the decimal number "5" from the output terminal MD1 of
The preset signal in decimal code format is subtracted by counter 2.
1 is supplied to the preset input terminal IN, and when a load signal of "1" is supplied to the load terminal LD of the subtraction counter 21, the count content of the subtraction counter 21 corresponds to "5" in decimal notation. is set to a preset value (0, 1, 0, 1),
Thereafter, each time the falling speed pulse signal is supplied, the output terminals A, B, C, and D of the same subtraction counter 21 are
The output signal from is (0, 1, 0, 1) → (0,
1, 0, 0) → (0, 0, 1, 1) → (0, 0,
1, 0) → (0, 0, 0, 1) → (0, 0, 0,
0) → (1, 1, 1, 1) → (0, 1, 0, 1)
The subtraction counter 21 repeats the counting operation so that . Then, the output terminal A of the subtraction counter 21,
When the output signals of B, C, and D become (0, 0, 0, 0), the output signal of the OR circuit 24 changes from "1" to "0" and is sent to the AND circuit 26 via the NOT circuit 25. As a result, the output signal SP2 of the AND circuit 26 is generated once every six speed pulse signals are generated from the pulse generator 20, and the frequency of the output signal SP2 is equal to that of the speed pulse signal. It becomes 1/6 of the frequency.

Similarly, the output terminal of the memory circuit 16
When the count contents of the subtraction counter 21 are respectively set to the preset value P1 based on the preset signal representing ``4'', ``1'', or ``0'' in decimal form from MD1, the subtraction counter 21 is set to the preset value P1 as described above. The output signals from output terminals A, B, C, and D are output (0, 0,
0, 0), the output signal "0" of the OR circuit 24 receiving the output signal (0, 0, 0, 0) periodically opens the AND circuit 26 through the NOT circuit 25. Pulse generator 20
The output signal SP2 is generated by periodically passing the speed pulse signal from the AND circuit 26. Therefore, the rotary switch 1
When the rotary switch 14 is set to the switching terminal 14c, the frequency of the output signal SP2 is 1/5 of the frequency of the speed pulse signal from the pulse generator 20, and when the rotary switch 14 is set to the switching terminal 14d, the output signal SP2 is The frequency of is 1/2 of the frequency of the speed pulse signal, and the rotary switch 14
is set at the switching terminal 14e or 14f, the frequency of the output signal SP2 becomes equal to the frequency of the speed pulse signal.

Therefore, the rotation speed of the DC motor M is 6000r・p・
Set the rotary switch 14 to the switching terminal 14b so that the motor M operates normally.
When rotating at a constant rotation speed of 6000 r/p/m, the subtraction counter 21 is
The AND circuit 26 receives a speed pulse signal with a frequency of ×10 ⁴ pulse/sec and changes its output terminals A, B, C, and D to (0, 0, 0, 0) every time it receives six speed pulse signals. One output signal is generated at the output terminal of , so that the frequency of the output signal SP2 is 1/3×10 ⁴ pulse/sec, which is 1/6 of the frequency of the speed pulse signal 2×10 ⁴ pulse/sec. become.

Also, in the case of 4500r/p/m, the subtraction counter 21
receives a speed pulse signal with a frequency of 15×10 ³ pulse/sec, divides the frequency of 15×10 ³ pulse/sec into 1/5, and outputs an output signal SP2 of 3×10 ³ pulse/sec from the AND circuit 26. output. Similarly, 2000r・p・
m, 1000r・p・m and 200r・p・m, the frequency is divided into 1/3×10 ⁴ pulse/sec, 1/3×10 ⁴ pulse/sec and 2/3×10 ³ pulse/sec, respectively. Output signal SP2
is output from the AND circuit 26.

Next, to explain the clock circuit 4, 27 is a subtraction counter that receives a preset signal from the output terminal MD2 of the memory circuit 16 at its preset input terminal IN, and receives an output signal SP2 from the AND circuit 26 at its load terminal LD. It's hot,
The rotary switch 14 is connected to a switching terminal 14b,
When set to 14c, 14d, 14e, and 14f, the subtraction counter 27 has the values ``300'', ``335'', ``300'', ``300'' and ``1500'' in decimal notation converted into binary code. A preset value P2 is received from the output terminal MD2 of the memory circuit 16. The subtraction counter 27 selects one of the preset values P2 based on the clock pulse signal SP6 with a frequency of 1×10 ⁶ pulse/sec from the clock pulse oscillator 29 supplied to the counting input terminal DN via the AND circuit 28. The count is subtracted step by step, and the counted contents are output to the output terminal CD.

Note that the preset value P2 output from the output terminal MD2 of the memory circuit 16 is, for example, 10 which is output when the rotary switch 14 is set to the switching terminal 14b corresponding to the rotation speed of 6000 rpm.
The preset value P2 corresponding to the base number "300" is the rotation speed corresponding to the set switching terminal 14b.
6000 r.p.m and an output terminal of the memory circuit 16 determined in advance corresponding to the rotation speed of 6000 r.p.m.
It is predetermined based on the preset value "5" output from MD1 and the frequency of the clock pulse signal SP6 from the clock pulse oscillator 29 of ^{1.times.10.sup.6} pulse/sec. Therefore, 6000r・p・
When the rotation speed is m, the DC motor M is accurately
If it is rotating at 6000rpm, the frequency of the speed pulse signal from the pulse generator 20 is 2×
10 ⁴ pulse/sec, and the period is 50×10 ⁻⁶ sec, so the frequency is divided by the subtraction counter 21 to 1/6 of the frequency 2×10 ⁴ pulse/sec as described above. The period of the output signal SP2 from the AND circuit 26 is 300×10 ^{−6 sec, which is six times the period of the speed pulse signal, 50×10 −6 sec} . Therefore, its output signal
During one cycle of SP2, 300×10 ^-6 sec, the clock pulse signal from the clock pulse oscillator 29 is
Since 300 SP6s are generated, the value "300" is stored in the memory circuit 16 as a preset value corresponding to the rotation speed of 6000 r.p.m. Also, rotation speeds other than 6000r/p/m are 4500r/
p・m, 2000r・p・m, 1000r・p・m, 200r・
Preset values corresponding to the rotation speed of p and m
P2 is also predetermined as described above.

Reference numeral 30 is an OR circuit that receives the output signal from the output terminal CD of the subtraction counter 27, and supplies the output signal to the AND circuit 28. Therefore, the count contents of the subtraction counter 27 are sequentially subtracted from the preset value P2 by the clock pulse signal SP6, and when the count contents eventually reach "0", the output signal of the OR circuit 30 becomes "0". The clock pulse signal from the clock pulse oscillator 29 is used to interrupt the AND circuit 28.
The supply of SP6 to the subtraction counter 27 is blocked, so that the subtraction counter 27 stops its subtraction operation and holds the output signal from its output terminal CD at "0". Then, the subtraction counter 27 does not restart the counting operation until it receives the frequency-divided output signal SP2 from the AND circuit 26 of the frequency divider circuit 3 and the count contents are set to the preset value again. The output signal of the OR circuit 30 continues to be held at the "0" state.

Therefore, set the rotary switch 14 to 6000r.
When set to the switching terminal 14b corresponding to the rotational speed of p.m, the subtraction counter 27 is set to the switching terminal 14b corresponding to the rotation speed of
The count contents are reset to the preset value "300" corresponding to the rotation speed of 6000 r.p.m., and the subtraction operation is repeated, so that the subtraction counter 27 receives 300 clock pulse signals SP6 from the clock pulse oscillator 29. The period to be counted, i.e. 300×
The period of 10 ^-6 sec and the generation period of the output signal SP2 of the AND circuit 26, which is related to the actual rotation speed of the DC motor M, are calculated by the subtraction counter 27 and the AND circuit 2.
8 and an OR circuit 30, and a signal representing the comparison result is generated from the OR circuit 30 as an output signal (first control pulse signal).

Based on the preset value P2 from the output terminal MD2 of the memory circuit 16, if the actual rotational speed of the DC motor M is higher than the respective set rotational speed, the pulse period of the output signal SP2 becomes shorter. Since the subtraction counter 27 receives the next output signal SP2 during subtraction counting, the subtraction counter 27 sets its preset value P2, returns to the initial state, and starts subtraction from the beginning. Therefore, in such a case, the OR circuit 30 at the next stage maintains the "1" state, and performs an operation to cut off power to the DC motor M, which will be described later, to reduce the rotation speed. or,
Conversely, when the actual rotation speed of the DC motor M is lower than the set rotation speed, the pulse period of the output signal SP2 becomes longer, so the subtraction counter 27 finishes subtraction and the next output signal SP2 is supplied. Counting operation stops until Therefore, in such a case, the OR circuit 30 at the next stage maintains the "0" state and performs the operation of supplying power to the DC motor M, which will be described later, to increase the rotation speed.

Next, the first control circuit 5 will be explained.
FF2 is a flip-flop circuit which receives the output signal of the OR circuit 30 at its data input terminal D, and receives the data input at the rising edge of the output signal SP2 of the AND circuit 26, which is supplied to the clock input terminal T of the flip-flop circuit FF2. Terminal D
The state is stored and the state is output to the output terminal Q. Therefore, the OR circuit 30
When the output signal of is “0”, the output signal SP2
is supplied to the clock input terminal T of the flip-flop circuit FF2, the output signal of the output terminal Q becomes "0" in response to the rise of the output signal SP2, and conversely, the output signal of the OR circuit 30 becomes "1".
When the output signal SP2 is supplied in the state of , the output signal from the output terminal Q becomes "1".
31 is an AND circuit that receives the output signal of the flip-flop circuit FF2 and the output signal SP2 of the AND circuit 26; 32 is a NOT circuit whose output terminal is connected to the set terminal ST of the flip-flop circuit FF2; is connected to the positive voltage +Vcc terminal via the resistor 33, thereby keeping the set terminal ST of the flip-flop circuit FF2 always at the logical value "0".

FF3 is a flip-flop circuit having the same function as the flip-flop circuit FF2, and its data input terminal D is connected to the note circuit 32 and the resistor 3.
The clock input terminal T is connected to the output terminal of the AND circuit 31, and the logic value is always set to "1".
Also, this flip-flop circuit FF3 changes the output signal SP7 of the AND circuit 31 from "0" to "1".
In response to the rising edge when the signal changes to , the state of the data input terminal D, that is, the logical value "1" state is stored, and the inverted "0" state of the "1" state is output to the output terminal. I'm starting to do that.
Further, the reset terminal RT of the flip-flop circuit FF3 is connected to the OR circuit 3 via the NOT circuit 34.
When the output signal of the OR circuit 30 changes from "1" to "0" in response to an output signal of 0, the NOT circuit 34
The output signal SP3 changes from "0" to "1", so that the output signal from the output terminal of the flip-flop circuit FF3 has a logical value of "1". A selection circuit 7 to which this output signal will be described later
is supplied to the input terminal of the AND circuit 35.

Next, explaining the selection circuit 7, 35 is an AND circuit which receives the output signal from the flip-flop circuit FF3 of the first control circuit 5 and the code signal SP5 from the output terminal MD3 of the memory circuit 16 via the not circuit 36. When the code signal SP5 of the output terminal MD3 of the memory circuit 16 is "0", the output signal is output from the output terminal of the flip-flop circuit FF3, and when it is "1", the output signal is output from the output terminal of the flip-flop circuit FF3. Block the signal. That is, this AND circuit 35 controls the rotary switch 14 at 6000 r.p.m.
4500r・p・m, 2000r・p・m and 1000r・p・m
Switching terminals 14b, 14c, corresponding to the rotation speed of m.
14d and 14e, the output signal of the flip-flop circuit FF3 of the first control circuit 5 is allowed to pass when the code signal SP5 of logic value "0" is supplied via the NOT circuit 36. . 35a is a second control circuit 6 which will be described later.
The AND circuit receives the output signal from the comparator circuit 49 and the code signal SP5 from the output terminal MD3 of the storage circuit, and the rotary switch 1
Switching terminal 1 corresponding to the rotation speed of 4 to 200r/p/m
When set to 4f, the output terminal MD3 receives a code signal SP5 having a logic value of "1" and becomes conductive, allowing the output signal from the comparator circuit 49 to pass through. Therefore, a switching circuit 8 to be described later connects the rotary switch 14 to the switching terminals 14b, 14.
When the rotary switch 14 is set to the switching terminal 14f, the switching operation is performed based on the output signal from the first control circuit 5. A switching operation is performed based on the output signal.

37 is an OR circuit to which the output signals of the AND circuits 35 and 35a are supplied; 38 is the OR circuit 37;
It is an AND circuit that receives an output signal SP4 from the flip-flop circuit FF1 of the speed command circuit 1, and receives an output signal SP4 from the first control circuit 5 based on the operation of the start/stop switch 11, which will be described later. The output signal from the second control circuit 6 is made conductive or cut off. Reference numeral 39 is a not circuit which receives the output signal of the AND circuit 38, and supplies the output signal to a switching circuit 8, which will be described later.

Next, the second control circuit 6 will be explained.
0 is an AND circuit receiving the output signal SP3 from the NOT circuit 34 of the first control circuit 5,
The output signal is supplied to an addition counting input terminal UP of an addition/subtraction counter 42 to be described later. Reference numeral 41 is an AND circuit which similarly receives an output signal SP7 from the AND circuit 31 of the first control circuit 5, and supplies the output signal to a subtraction counting input terminal DN of an addition/subtraction counter 42, which will be described later.

42, a preset signal representing the preset value P3 is supplied from the output terminal of the data setting circuit 43 to a preset input terminal IN, and an output signal of the AND circuit 17 of the speed command circuit 1 is supplied to the load terminal LD as a load signal. an addition/subtraction counter which increases the count by one in response to the fall of the output signal when the addition count input terminal UP receives the output signal from the AND circuit 40;
Further, when the subtraction count input terminal DN receives the output signal from the AND circuit 41, the count is decreased by one in response to the fall of the output signal, and the count is converted into a 4-bit binary code format. The output signal X is output to output terminals A, B, C, and D. In this embodiment, the addition/subtraction counter 42 is configured to output the count contents using its output terminal A as the most significant bit output terminal and its output terminal D as the least significant bit output terminal. Setting circuit 43
supplies a preset signal in the form of a binary code representing the decimal number "7" to the preset input terminal IN of the addition/subtraction counter 42, and inputs " from the AND circuit 17 of the speed command circuit 1 to the load terminal LD of the addition/subtraction counter 42. When a load signal rising from "0" to "1" is supplied, the count contents of the addition/subtraction counter 42 are set to a preset value (0, 1, 1, 1) corresponding to "7" in decimal notation.

44 is an output terminal B of the addition/subtraction counter 42;
This is an OR circuit to which output signals from C and D are supplied, and the output signal is supplied to the input terminal of the AND circuit 41. And addition/subtraction counter 4
The output signals from output terminals B, C, and D of 2 are (0,
0, 0), the output signal of the OR circuit 44 becomes "0" and the AND circuit 41 is cut off, so that the output signal SP7 from the AND circuit 31 of the first control circuit 5 is added and subtracted. The supply to the subtraction counting input terminal DN of the counter 42 is prevented,
Thereby, the addition/subtraction counter 42 stops the subtraction operation.

45 is an AND circuit to which output signals from output terminals B, C, and D of the addition/subtraction counter 42 are supplied, and the output signal is supplied to the input terminal of the AND circuit 40 via a NOT circuit 46. . Then, the output terminal B of the addition/subtraction counter 42,
When the output signals from C and D become (1, 1, 1), the output signal of the AND circuit 45 becomes "1",
Then, the output signal SP3 from the NOT circuit 34 of the first control circuit 5 is sent to "0" via the NOT circuit 46 to cut off the AND circuit 40.
is the addition count input terminal of the same addition/subtraction counter 42
The addition/subtraction counter 42 stops adding. Therefore, the output signal X of the output terminals A, B, C, and D of the addition/subtraction counter 42 changes from "7" to "7" in decimal by the output signals from the OR circuit 44 and the AND circuit 45. 2 in the range up to 0
Controlled to be a hex-encoded number. The output signal X of the addition/subtraction counter 42 is supplied to a word input terminal C1 of a comparison circuit 49, which will be described later.

47 is a frequency dividing circuit to which a clock pulse signal SP6 of 1×10 ⁶ pulse/sec from the clock pulse oscillator 29 of the clock circuit 4 ^is supplied;
The frequency of the clock pulse signal SP6 of pulse/sec is divided by 1/100 to output a clock pulse signal of a frequency of 10×10 ³ pulse/sec. 48 is the count input terminal UP which receives 10×10 ³ pulse/from the frequency divider circuit 47.
It is a binary coded septa-ary counter to which a sec clock pulse signal is supplied as a counting signal, and counts in response to the falling edge of the clock pulse signal, and outputs the count contents as an output signal Y in the form of a 4-bit binary code.
The signals are output to output terminals A, B, C, and D as follows. The binary coded septa-ary counter 48 is configured to output the count contents using the output terminal A as the most significant bit output terminal and the output terminal D as the least significant bit output terminal. Therefore, 10×
Every time a clock pulse signal of 10 ³ pulse/sec is supplied, the output terminal A of the binary coded heptad counter 48,
The output signals Y of B, C, and D are (0, 0, 0, 1) →
(0, 0, 1, 0) → (0, 0, 1, 1) →
(0, 1, 0, 1) → (0, 1, 1, 0) →
The hexadecimal hexadecimal counter 48 repeats the counting operation so that (0, 1, 1, 1)→(0, 0, 0, 1).

Reference numeral 49 is a comparison circuit which receives output signals Y from output terminals A, B, C, and D of the binary coded heptad counter 48 at a word input terminal C2, and is supplied from the addition/subtraction counter 42 to the word input terminal C1. The output signal An output signal with a logical value of "1" is output.

Therefore, the output signal X from the addition/subtraction counter 42
corresponds to the decimal number "7" (0, 1, 1, 1)
When , the output signal Y from the binary coded heptad counter 48
Since the condition of output signal Therefore, the output signal of the comparator circuit 49 always maintains the state of "1" as shown in FIG. 3b. Also, the output signal X from the addition/subtraction counter 42 corresponds to "6" (0, 1, 1,
0), the output signal Y of the binary coded hexadecimal counter 48 corresponds to the decimal number "7" (0, 1, 1,
1) (that is, when the seventh clock pulse signal is supplied from the divider circuit 47 to the binary coded heptad counter 48), the output signal Y (decimal "7") becomes the output signal X ( The output signal of the comparator circuit 49 is as shown in Fig. 3c.
As shown in the figure, the 8th clock pulse signal changes from "1" to "0", and then the 8th clock pulse signal is sent to the binary coded heptad counter 4.
8, the output signal The ratio T ₁ /T ₁ +T ₂ is 6/7.

Similarly, the output signal X is decimal "5", "4",
......, etc., the duty ratio T ₁ /T ₁ +T ₂ becomes "5/7" as shown in Fig. 3 d to h.
An output signal with a pulse waveform of "4/7", . . . is output from the comparator circuit 49. That is, the addition/subtraction counter 42 set to the preset value P3 from the data setting circuit 43 changes its counting contents in response to the output signals supplied to the addition and subtraction counting input terminals UP and DN, and changes its output. Terminals A, B,
The duty ratio T ₁ /T ₁ +T ₂ of the output signal (second control pulse signal) from the comparator circuit 49 is changed by the output signals X from C and D.

Next, the switching circuit 8 will be explained according to FIG. 2. 50 is a holding type power switch,
By pressing this switch 50, a DC voltage +Vs is applied to the switching circuit 8, and one positive pulse signal SN is generated, and the pulse signal SN is applied to the flip-flop circuit FF.
1, FF2, the subtraction counter 21, and the addition/subtraction counter 42 are supplied to the respective reset terminals RT and the set terminal ST of the flip-flop circuit FF3. Tr1 and Tr2 are Darlington-connected switching transistors whose collector terminals are connected to the power switch 50 via the DC motor M.

Tr3 is a switching transistor whose base terminal is connected to the output terminal of the NOT circuit 39 of the selection circuit 7 through a diode D, and whose collector terminal is connected to the base terminal of the switching transistor Tr1. .

Therefore, when the base terminal of the switching transistor Tr3 receives an output signal of "0" from the NOT circuit 39, the transistor Tr3 becomes non-conductive, so that the next stage switching transistors Tr1 and Tr2 receive a DC voltage. +Vs to resistance 51
The DC motor M is supplied with a base current through it and becomes conductive, and a DC voltage +Vs is applied to the DC motor M, causing it to rotate.
Conversely, when receiving an output signal of "1" from the NOT circuit 39, the switching transistor Tr3 is supplied with an appropriate base bias current by the low resistor 52 and becomes conductive, so that the switching transistors Tr1 and Tr2 become conductive. The base and emitter are short-circuited and become non-conductive, and the supply of DC voltage +Vs to the DC motor M is cut off.

Next, the operation of the electric motor speed control device configured as described above will be explained.

Now, a case will be explained in which the speed of the DC motor M is controlled at a rotation speed of 6000 r.p.m. First, when the rotary switch 14 is operated and connected to the switching terminal 14b, the memory circuit 16 receives a code signal corresponding to the rotation speed of 6000 r.p.m. from the encoder 15 and is addressed. Next, when the power switch 50 is pressed and closed, a pulse signal SN is generated, and the output signals of the output terminals Q of the flip-flop circuits FF1 and FF2 and the output terminal of the flip-flop circuit FF3 are reset and set to "0". At the same time, the subtraction counter 21 of the frequency dividing circuit 3 and the addition/subtraction counter 42 of the second control circuit 6 are reset, and the output terminals A,
B, C, and D are changed to (0, 0, 0, 0), and the output terminals MD1, MD2, and MD of the memory circuit 16 are changed to (0, 0, 0, 0).
3 outputs a preset signal and a code signal SP5. At this time, the AND circuit 38 of the selection circuit 7
receives an output signal SP4 of "0" from the output terminal Q of the flip-flop circuit FF1 and is cut off, and the AND circuit 35a is cut off from the memory circuit 16.
Since it is cut off by receiving the code signal SP5 of "0" from It supplies an output signal (cutoff command signal) and cuts off power to the DC motor M.

Then, when the start/stop switch 11 is pressed in this state, the output signal SP4 at the output terminal Q of the flip-flop circuit FF1 is inverted from "0" to "1", and the monostable multivibrator 13 in the next stage is triggered and output signal SP1 is generated, which resets the subtraction counter 27 and outputs the output terminal CD.
The output signal of the OR circuit 30 becomes "0" and the AND circuit 28 is cut off, causing the clock pulse oscillator 29 to send a clock pulse to the counting input terminal DN of the subtraction counter 27. The supply of signal SP6 is stopped. Therefore, the output signal of the OR circuit 30 is held at the "0" state until the output signal SP2 from the frequency dividing circuit 3 is supplied to the load terminal LD of the subtraction counter 27, and the subtraction counter 27 stops counting operation. do. The output signal in the "0" state from the OR circuit 30 is supplied to the reset terminal RT of the flip-flop circuit FF3 via the NOT circuit 34, thereby resetting the flip-flop circuit FF3 and causing the output signal from its output terminal to become "0". ” to “1”
The output signal from the output terminal is supplied to one input terminal of the AND circuit 35. On the other hand, the AND circuit 35 receives a code signal SP5 having a theoretical value of "0" from the output terminal MD3 of the memory circuit 16 at the other input terminal, and allows the output signal of the flip-flop circuit FF3 to pass through. The output signal of is supplied to the NOT circuit 39 via the OR circuit 37 and the AND circuit 38, and the NOT circuit 39
An output signal (supply command signal) in the "0" state is supplied to the motor M, and a DC voltage +Vs is applied to the DC motor M to start it.

The pulse generator 2 is activated by starting the DC motor M.
The generation of the speed pulse signal starts from 0, and when the speed pulse signal is frequency-divided by the subtraction counter 21 etc. and one output signal SP2 is generated from the AND circuit 26, the output signal SP2 is applied to the load terminal LD of the subtraction counter 27. The subtraction counter 27 sets the preset value "300" supplied to the preset input terminal IN to make the count content "300". When the subtraction counter 27 reaches the preset value P2, that is, the initial state, the output signal of the OR circuit 30 at the next stage changes from "0" to "1" and opens the AND circuit 28. Then, clock pulse oscillator 2
The clock pulse signal SP6 from 9 is supplied to the count input terminal DN of the subtraction counter 27 via the AND circuit 28, and the subtraction counter 27 starts a subtraction operation.

On the other hand, one output signal SP2 generated from the AND circuit 26 is supplied to the clock input terminal T of the flip-flop circuit FF2, and the flip-flop circuit FF2 changes the output signal of the OR circuit 30 from "0" to "1". Immediately before this, the rising edge of the output signal SP2 is caught and the "0" state output signal of the OR circuit 30 supplied to the data input terminal D is read, and a "0" output signal is generated at the output terminal Q. . As a result, AND circuit 3
1 is cut off to prevent the output signal SP2 from passing through, the output signal of the flip-flop circuit FF3 is held at the "0" state, and the DC motor M continues to receive the DC voltage +Vs to increase the rotation speed.

Then, by repeating such operations, the DC motor M increases the rotational speed to 6000 r.p.m., and the pulse period of the output signal SP2 is also shortened, gradually approaching the period of 300×10 ^-6 sec. After that, when the rotation speed of the DC motor M increases to 6000 r/p/m or more, the pulse period of the output signal SP2 becomes 300×
Since it is shorter than 10 ^-6 sec, the subtraction counter 27
receives the next output signal SP2 while subtracting the value "300", and immediately starts subtracting the same subtraction counter 27.
returns to its initial state and starts subtracting from the initial value of "300" again. Therefore, the output signal of the OR circuit 30 continues to maintain the "1" state without changing to the "0" state, and the output signal of the flip-flop circuit FF2 is equal to the output signal of the OR circuit 30 and the output signal SP2. is inverted from “0” to “1” based on
is passed through to the next stage flip-flop circuit FF3.
Inverts the output signal from "1" to "0". As a result, the switching circuit 8 receives an output signal of "1" via the selection circuit 7, and the supply of DC voltage +Vs to the DC motor M is cut off, and the rotation speed of the motor M becomes 6000rpm. It will be dropped as it is.

Conversely, if the rotational speed of DC motor M falls below 6000rpm, the pulse period of output signal SP2 will be 300rpm.
Since it is longer than ×10 ^-6 sec, the subtraction counter 27
Before the next output signal SP2 is supplied to the load terminal LD of the subtraction counter 27, the counting operation of the subtraction counter 27 is completed and the output signal of the OR circuit 30 becomes "0". The output signal is then supplied to the reset terminal RT of the flip-flop circuit FF3 via the note circuit 34, and the flip-flop circuit FF3 is reset and its output signal is inverted from "0" to "1".
DC voltage +Vs is again applied to the DC motor M, and the rotation speed is accelerated to 6000 r.p.m.

Next, when you want to stop the DC motor M, press the start/stop switch 11 and the flip-flop circuit will start.
Since the output signal SP4 of FF1 is inverted from "1" to "0" and the AND circuit 38 is cut off, no matter what state the output signal of the flip-flop circuit FF3 is in, the DC voltage +
The application of Vs is cut off and the DC motor M eventually stops.

Note that during this series of speed control operations of 6000rpm, the output terminal of the memory circuit 16
Since the code signal SP5 from the MD 3 is in the "0" state, the AND circuit 35a receiving the code signal SP5 is still in the cutoff state, and the switching circuit 8 is turned off regardless of the operating state of the second control circuit 6. A switching operation is performed according to an output signal from the first control circuit 5.

Similarly, the rotation speed of DC motor M is set to a constant value.
4500r・p・m, 2000r・p・m, 1000r・p・m
In order to control the speed so that Output signals SP2 are output by dividing the signal into 1/5, 1/2, and 1, respectively. On the other hand, the subtraction counter 27 also corresponds to "335", "300",
The value of “300” is set to the clock pulse signal SP6.
It operates to subtract based on. Therefore, the above
Similarly to the speed control of 6000 r.p.m., the output signal of the OR circuit 30 is used to determine whether or not the subtraction counter 27 completes subtraction of each preset value before receiving the next output signal SP2. Based on the state of the output signal, a DC voltage +Vs is applied to the DC motor M, and the speed of the DC motor M is controlled to a desired set rotation speed.

Next, set the rotation speed of DC motor M to 200 r/min at low speed.
A case will be described in which the speed is controlled so that the speed becomes p.m.

First, when the rotary switch 14 is operated and connected to the switching terminal 14f, the memory circuit 16 receives a code signal corresponding to the rotation speed of 200 r.p.m. from the encoder 15 and is addressed. Next, when the power switch 50 is pressed, the flip-flop circuit turns on as in the case of the rotation speed control of 6000rpm.
FF1, FF2, FF3, subtraction counter 21, and addition/subtraction counter 42 are reset or set. The output terminal MD1 of the memory circuit 16 outputs a preset signal with a preset value P1 expressed as a decimal number "0", and the output terminal MD2 outputs a preset signal with a preset value P2 expressed as a decimal number "1500". A code signal SP5 of "1" is output from the terminal MD3. As a result, the AND circuit 35 of the selection circuit 7 receives the code signal SP5 via the NOT circuit 36 and is cut off.
The AND circuit 35a receives the "1" code signal.
In response to SP5, the output signal from the comparator circuit 49 is allowed to pass through. On the other hand, the AND circuit 38 receives an output signal SP4 of "0" from the flip-flop circuit FF1 and is cut off, thereby cutting off the power to the DC motor M.

Then, when the start switch 11 is pressed in this state, the output signal SP4 of the flip-flop circuit FF1 is
is inverted from “0” to “1”, and in response to the rising edge, the monostable multivibrator 13 at the next stage is triggered and generates the output signal SP1, which causes the addition/subtraction counter 42 to be loaded via the AND circuit 17. A load signal of “1” is supplied to the terminal LD,
The output signals of output terminals A, B, C, D are (0, 1,
1, 1) (output signal X representing decimal number "7"), and supplying the output signal The output signal is supplied to the OR circuit 37 via the AND circuit 35a. Then, the OR circuit 37 that receives the output signal of "1" supplies an output signal (supply command signal) of the state of "0" to the switching circuit 8 via the AND circuit 38 and the NOT circuit 39, and supplies the output signal of the state of "0" (supply command signal) to the DC motor M. Start by applying DC voltage +Vs. On the other hand, at this time, the output signal SP1 from the monostable multivibrator 13 is connected to the reset terminal RT of the subtraction counter 27.
The flip-flop circuit FF3 of the first control circuit 5 outputs a "1" output signal from the output terminal of the flip-flop circuit FF3 of the first control circuit 5 to the AND circuit 35 of the selection circuit 7 of the next stage. The AND circuit 35 receives the code signal SP5 in the "1" state from the output terminal MD3 of the memory circuit 16.
Since this is received as an output signal of "0" via the knot circuit 36, the output signal from the first control circuit 5 is cut off.

When the DC motor M starts, the pulse generator 20 starts generating a speed pulse signal, and the AND circuit 26 generates an output signal SP2 with a frequency division ratio of "1" via the subtraction counter 21 and the like. The preset value "1500" supplied to the load terminal LD and the preset input terminal IN of the subtraction counter 27 is set to make the count content "1500". In this way, when the subtraction counter 27 changes to the state where the preset value P2 is set, the output signal of the OR circuit 30 at the next stage changes from the "0" state to the "1" state, and the
Subtraction counter 27 as in the case of 6000r・p・m
starts the subtraction operation. On the other hand, the output signal SP2 generated from the AND circuit 26 is supplied to the clock input terminal T of the flip-flop circuit FF2, and since the AND circuit 31 is cut off as described above, the output signal SP7 is output in response to the output signal SP2. Since is not supplied to the AND circuit 41, the comparator circuit 49 outputs the output signal shown in FIG. raise.

Then, by repeating such operations, the DC motor M increases the rotational speed to 200 r.p.m., and the output signal SP2 also shortens the pulse period, gradually approaching the period of 1.5×10 ^-3 sec. While the period of the output signal SP2 is longer than 1.5×10 ^-3 sec,
The actual rotation speed of DC motor M is longer than the set rotation speed.
While the value is lower than 200r.p.m, the addition/subtraction counter 42 does not receive the output signal for subtraction operation from the AND circuit 41, and the output terminals A,
The output signals of B, C, and D maintain the state of (0, 1, 1, 1), and the AND circuit 4 is controlled by the output signals.
Since the AND circuit 40 is cut off via the 5 and NOT circuit 46, the addition/subtraction counter 42 does not perform an addition operation.

After that, the rotation speed of DC motor M is 200r・p・m
When the pulse period of output signal SP2 exceeds 1.5
Since it is shorter than ×10 ^-3 sec, the subtraction counter 2
7 receives the next output signal SP2 while subtracting the value "1500" and immediately starts subtracting counter 2.
7 returns to its initial state and starts subtracting from the value "1500" again. And the above 6000r・
As in the case of p/m, the AND circuit 31 outputs the output signal SP7 to its output terminal in response to one output signal SP2, and the output signal SP7 is used for subtraction by the addition/subtraction counter 42 via the AND circuit 41. Supplied to counting input terminal DN. The subtraction counter 42 subtracts the count by one in response to the rise of its output signal SP7, and the output terminals A, B, C, and D are in the state of (0, 1, 1, 0), that is, the decimal number "6". The next stage comparator circuit 49 generates an output signal X ^expressed as The output signal of the waveform is passed through the AND circuit 35.
a. The power is supplied to the switching circuit 8 via the OR circuit 37, the AND circuit 38, and the NOT circuit 39, and the power supply time to the DC motor M is shortened and the rotational speed is controlled to decrease.

Also, this duty ratio T ₁ /T ₁ +T ₂ is “6/
Even if the power supply time is intermittently shortened by the output signal from the comparator circuit 49 with a pulse width of 7" (pulse width 6×10 ^-4 sec), the power supply time is still long and the rotational speed of the DC motor M is 200 r. If it does not fall to p.m, the output signal SP2 is generated while the subtraction counter 27 is subtracting the value "1500" as described above, so the AND circuit 31 outputs the output signal SP7, and the output signal SP7 is output from the AND circuit 31. The output signal SP7 is supplied to the input terminal DN of the addition/subtraction counter 42 via the AND circuit 41, and the addition/subtraction counter 42 subtracts the count contents.
Change the decimal number "6" to "5". As a result, the comparison circuit 49 selects the output signal of the output waveform pulse width modulated to the duty ratio "5/7" (pulse width 5×10 ^-4 sec) as shown in FIG. 3d to the selection circuit 7.
The power is supplied to the switching circuit 8 via the DC motor M, and is controlled to shorten the power supply time to the DC motor M and further reduce the rotational speed. And the DC motor M
The addition/subtraction counter 42 performs a subtraction operation until the rotational speed reaches 200 r.p.m, and the appropriate duty ratio T ₁ /T ₁ + is reached.
Comparison circuit 4 outputs the pulse width modulated output signal to _T2 .
9 to control the rotation of the DC motor M.

Conversely, the rotation speed of DC motor M increases due to the increase in load.
If it falls below 200r・p・m, the pulse period of the output signal SP2 becomes longer by 1.5×10 ^-3 sec, so the next output signal SP is sent to the load terminal LD of the subtraction counter 27.
The counting operation of the subtraction counter 27 ends before 2 is supplied, and the output signal of the OR circuit 30 becomes "0". And the output signal is from the node circuit 3.
4. Addition/subtraction counter 42 via AND circuit 40
The addition/subtraction counter 42 performs an addition operation in response to the rising edge of the supplied output signal. Therefore, contrary to the above, the output signal X of the addition/subtraction counter 42 is pulse width modulated by increasing its duty ratio T ₁ /T ₁ +T ₂ and sent to the switching circuit 8 via the selection circuit 7.
As a result, the power supply time to the DC motor M becomes longer and the rotational speed of the DC motor M increases to 200r.
It is accelerated to become p.m.

Next, when stopping the DC motor M,
As in the case of 6000 r.p.m., when the start/stop switch 11 is pressed, the AND circuit 38 is cut off, the application of the DC voltage +Vs to the DC motor M is cut off, and the DC motor M eventually stops.

As can be understood from the above explanation, from high speed rotation to medium speed rotation (in this example, from 6000 r.p.m.
When controlling the speed of the DC motor M in the range of 1000 r/p/m), the frequency of the speed pulse signal from the pulse generator 20 is divided by a frequency division ratio corresponding to each set rotation speed to generate the speed signal SP2. Therefore, the timing circuit 4 and the first control circuit 5 should be operated at a cycle longer than the minimum operating time of 200×10 ^-6 sec. The timing circuit 4 and the like can accurately determine the magnitude relationship between the actual rotational speed and the set rotational speed of the DC motor M, and generate a power supply command signal and a power cutoff command signal. Further, when controlling the speed of the DC motor M at a low rotation speed (200 r.p.m. in this embodiment), the supply command signal and cutoff command signal to the DC motor M output from the first control circuit 5 are Instead, a control pulse signal pulse width modulated by the second control circuit is supplied to the switching circuit 8 during a relatively short cycle of 6×10 ^-6 sec, and power is supplied to and cut off from the DC motor M. DC motor M
The DC motor M can be driven at a constant low speed without changing the rotational speed.

Note that in this embodiment, the rotary switch 14
Operate the DC motor M to 6000r・p・m,
4500r・p・m, 2000r・p・m, 1000r・p・m
The speed control circuit is designed to control the speed at each rotation speed of m, 200 r/p/m, but the speed can also be controlled by setting various other desired rotation speeds, or the speed command circuit 1, frequency dividing circuit 3. The digital circuit components in this embodiment, such as the clock circuit 4, the first and second control circuits 5 and 6, and the selection circuit 7, are configured with a microprocessor to simplify and downsize the speed control circuit. etc., may be arbitrarily changed without departing from the spirit of the present invention.

As detailed above, the present invention generates a pulse signal with a frequency proportional to the rotation speed of the motor, and in the case of high-speed rotation control, the period of the pulse signal is longer than the minimum operating time of the speed control circuit. The frequency of the pulse signal is divided by the frequency dividing means, the length of the period of the divided signal and the time corresponding to the desired set rotation speed is determined by the time measuring means, and the first control is performed based on the determination result. The means controls the motor to rotate at high speed, while in the case of low speed rotation control, the timer determines the length of the period of the pulse signal and the time corresponding to the set rotation speed without frequency dividing the pulse signal, The second control circuit is configured to change the duty ratio of a control pulse signal generated in a relatively short period according to the determination result, and control the motor to rotate at a low speed according to the control pulse signal. It is possible to reliably and accurately control the speed of an electric motor over a wide range from high-speed rotation to low-speed rotation, and has excellent industrial effects as a speed control device for an electric motor.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram illustrating an embodiment of a motor speed control device embodying the present invention, FIG. 2 is a switching circuit diagram, and FIGS. 3 a to 3 h are output signal waveforms from a comparison circuit. It is a time chart diagram showing. Speed command circuit...1, Speed detection device...2, Frequency dividing circuit...3, Timing circuit...4, First control circuit...5, Second control circuit...6, Selection circuit...
7. Switching circuit... 8. Addition/subtraction counter...
...42, Comparison circuit...49, DC motor...M.

Claims (1)

[Scope of Claims] 1. A switching device for performing on/off operations to supply and cut off power to the electric motor, and a speed command for generating a command signal corresponding to a desired speed within a speed range from low speed to high speed. a speed sensing device for detecting the actual speed of the motor being driven within the speed range and generating a speed signal with a frequency proportional to the actual speed; frequency dividing means for dividing and outputting the speed signal according to the command signal when the desired speed is higher than the reference speed, and directly outputting the speed signal when the desired speed is lower than the reference speed; It operates in response to an output signal from the frequency dividing means, performs a time measurement operation determined according to the command signal, and responds to the end of the time measurement operation when the output signal is not generated during the time measurement operation. a timekeeping means for generating a timekeeping end signal based on the timer; and a timekeeping means responsive to the timekeeping end signal and the output signal from the frequency dividing means to a supply state for supplying power to the electric motor and a cutoff state for cutting off the power. a first control means for generating a first control pulse signal according to a supply state and a cutoff state thereof, the first control means being configured to be able to be set respectively as generating a second control pulse signal at a predetermined frequency higher than the frequency of the output signal output from the frequency dividing means when the clock is running; a second control means for determining a duty ratio of the second control pulse signal; and selecting the first control means when the desired speed is higher than the reference speed, and selecting the first control means when the desired speed is lower than the reference speed. selection means responsive to the command signal to select the second control means; and switching the control pulse signal to turn on and off the switching device in accordance with the control pulse signal from the selected control means. A speed control device for an electric motor, comprising a device for effectively applying voltage to the device. 2. The second control means includes a reversible counter whose counting contents change in response to the output signal from the frequency dividing means and a timing end signal, respectively, and a counter whose counting contents repeatedly change at a predetermined short period. The vessel and
Claim 1, further comprising a comparator for comparing the counts of both counters, and generating the comparison result of the comparator as the second control pulse signal. Electric motor speed control device.