JPS6136257B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an error detection and monitoring device, and more particularly to an error detection and correction device that occurs in operations on data expressed in a number system of residual classes. The present invention can be used to monitor and correct errors that occur in results obtained during operations performed by a computer based on a remainder class number system. Current devices and methods for providing noiseless coding are primarily suited for data transfer and are handled based on the nature of the error (single, duplex, etc.). If the data is modified when an error of an improperly determined nature occurs, the error is not corrected and a new error is introduced as a result of such modification. The code for the number system of the remainder class is an arithmetic code. Thus, it is necessary for a reliable processor to have an error correction and monitoring device that can operate to correct errors in data operations or transfers. The present invention partially solves this problem. Devices for detecting and correcting errors in remainder class number systems are well known. (For example, USSR inventor certificate number 398950, September 27, 1973. Int.Cl.G06F11/0
0). This device operates on the principle of extending the display range of numbers in a remainder class number system. To simplify this decompression process, decompression with imprecise ranks is used. This process does not require additional equipment to convert numbers from the remainder class number system to the positional number system, compared to the exact rank decompression process. The apparatus includes an input register having an input connected to the input bus, a first constant storage unit having an input connected to the output of the input register, and a first constant storage unit connected to a first and a first output of the first constant storage unit, respectively. first and second inexact rank calculators having inputs, a first input connected to the output of the first inexact rank calculator, a second input connected to the first output of the first constant storage unit, and a first input connected to the output of the first inexact rank calculator; first and second check reference adders each having a third input connected to a third output of the second constant storage unit; and a first check reference adder connected to the output of the second inexact rank calculator.
third and fourth check reference adders having second and third inputs connected respectively to the input and second and fourth outputs of the first constant storage unit; an analysis unit having an input connected to a 3,4 check reference adder, the output of the second constant storage unit being connected to the first
to the output bus and the output of the above analysis unit to the second
Connect to each output bus. The above arrangement is complex because the location and magnitude of the error is determined by extending the range of the representation of the numerical value, and therefore requires calculation of the magnitude of the inaccuracy rank. Other known detection and correction devices are shown in the USSR Invention Certificate (issued January 27, 1967, Int.Cl.G06F11/08). The device includes a register having a first input connected to an input bus, an adder having first and second inputs connected to respective outputs of the register, first inputs connected to the outputs of the adder, and respective first and second inputs connected to the outputs of the adder. an analysis unit having first and second outputs connected to the first and second output buses; a single error detector having an input connected to the third output of the unit; and an input connected to the output of the detector. and an error correction unit having an output connected to a second input of said register;
a storage unit having a first input connected to the first output of the register, a second input connected to the fourth output of the analysis unit and an output connected to the third input of the adder. This device is incapable of detecting and correcting many errors. Furthermore, when multiple errors occur, the device has a tendency to detect the error as a single one and correct it in the usual manner before producing a new error. The purpose of the present invention is to detect and correct many errors that occur as a result of data processing by a computer.
An object of the present invention is to provide an error detection and correction device for a remainder class number system. a register for storing a check operand with an input connected to the input bus, and a constant to be added algebraically to said operand to correct possible errors therein; a constant storage unit for storing a binary number for determining an erroneous remainder; and a constant storage unit for storing a binary number for determining an erroneous remainder, and a multi-stage analysis of the binary number at a position where an error is assumed to be in the above check operation number to discriminate the erroneous remainder of the above check operation number. an analysis unit having a first output connected to the output bus for indicating the occurrence of an error in the arithmetic operation; and an input connected to the first output of the register. a remainder calculator for calculating the remainder of said operational number with respect to a check criterion of said operational number, which makes it possible to detect errors in said operational number; and an input connected to a first output of said constant storage unit. an error syndrome calculator, having an input connected to the output of the remainder calculator and an input connected to the second output of the register, for algebraically adding the real remainder to the check criterion and adding the calculated remainder to the a modulo adder for calculating the syndrome of the check operand by algebraically adding it to a check criterion; an input connected to the output of the modulo; and an input connected to the output of the error syndrome calculator; a comparator responsive to the error syndrome and the syndrome of the operand to determine whether an error has occurred in the operand; and first and second outputs connected to the respective inputs of the analysis unit together with an input connected to the output of the comparator and first and second outputs of the single error detector; a multi-stage (K) error detector for discriminating the error remainder of the above-mentioned operation number by multi-stage analysis of the binary number at the position where the number is assumed to have an error; an input connected to the output of the above-mentioned register; an input connected to a first output and an output connected to an input of said error correction adder, the location of an error within said operand being caused and capable of applying said operand to said error correction adder; a control flip-flop having an input connected to the input bus and an output connected to the input of the logic unit for selecting a mode of operation of the device;
having an output connected to an input of said constant storage unit and an input of a first group of AND gates having an input connected to a second output of said storage unit, controlling the operation of said means for correcting said error check operand; a control unit, an input connected to a third output of said single error detector and a third output of said multi-stage feed detector and a first input connected to an output of said modulo via a second group of AND gates; and said analysis. an OR having an output connected to an input of said constant storage unit having a second input connected to a second output of the unit;
a first input connected to the first output of the constant storage unit and a second input of the second AND gate group;
a fourth AND gate group having a second input connected to the second output of the analysis unit connected to the input and an output connected to the output bus, and a remainder class whose result of each operation is a check operation number. An apparatus for detecting and correcting errors in processing data represented by a number system is provided. Preferably, each of the multi-stage error detectors is
First and second comparisons are applied to the inputs of a flip-flop having an input connected to the output of the 1AND gate group and an output connected to the second input of the respective AND gate, and to the respective inputs of the OR gate group and the respective inputs of the above analysis unit. The circuit has an AND gate with true and complement outputs connected to an input of an adder with an output connected through the circuit. Preferably, the analysis unit has a plurality of adders, the input of the first adder being connected to the second output of the single error detector, and the inputs of the remaining adders being connected to the second output of the multi-stage error detector. 2 outputs and their outputs are
It is connected via a group of AND gates to the input of an OR gate, the output of which is connected to the fourth input of the logic unit, which in turn is connected to the first output of the single and multi-stage error detector. and a third input connected to the output of the group of AND gates having the inputs. This logic unit consists of three groups of AND gates whose outputs are connected to the inputs of OR gates whose outputs are connected to the inputs of error-correcting adders, the complement inputs of the first group of which are connected to the outputs of control flip-flops. , the second input of the first group is the last input of the third group, and the third input of the first group is combined with the first input of the second group and the second input of the third group to the first input of the register. output, the fourth input of the first group is combined with the second input of the second group and the first input of the third group and connected to the second input of the register, and the complement input of the second group is connected to the parsing input. Connect to the first output of the unit. The present invention allows errors in data transmission or processing to be detected and corrected without predetermining the nature of the error. When the present invention is used in data processing and transfer systems, the reliability of the hardware may be low because the validity of the calculation results is perfect. The device according to the invention comprises a register 1 (FIG. 1) having an input 2 connected to an input bus 3, a remainder calculator 4 having an input 5 connected to the output of register 1, a control unit 6 and a constant storage unit 7. Consisting of
The input 8 of the unit 7 is connected to the output of the control unit 6. The device has an error syndrome calculator 9 having an input 10 connected to the output of the constant storage unit and an output connected to the input 11 of the comparator 12. Comparator 1
The input 13 of 2 is connected to the output of modulo 14.
The input 15 of the adder 14 is connected to the output of the remainder calculator 4, and the input 16 of the adder 14 is connected to the output of the register 1. The output of comparator 12 is connected to input 17 of AND gate group 18. AND gate group 18
The inputs 19, 20 of are connected to the output of the control unit 6 and the output of the constant storage unit 7, respectively. The output of the AND gate group 18 is _the combined input ₂₁ ,
22,...22 _k , respectively. The first and second outputs of the single error detector 23 and the multistage error detectors 24 ₁ , . . . 24 _k are the input 2 of the analysis unit 28 .
5, 25', 26, 26', 27, 27'. Single and multi-stage error detectors 23, 24 ₁ ,
...24 The third output of _k is input 2 of OR gate group 32
Connected to 9, 30, and 31. OR gate group 32
The output of is connected to the input 34 of constant storage unit 7 via AND gate group 33, and the input of unit 7 is connected to analysis unit 28 via AND gate group 36.
The AND gate group 33 is connected to the output of the unit 28. The input of the AND gate group 36 is connected to the modulus 14. The device further includes an input 38 connected to the input bus 39.
a control flip-flop 37 with inputs 41 and 4 connected respectively to the output of this flip-flop, to the output of register 1 and to the output of analysis unit 28;
Logic unit 40 having 2, 43, 44, 45
and an input 47 connected to the output of unit 40.
An error correction adder 4 having an input 48 connected to the output of the storage unit 7 via a group of AND gates 49
6. The output of adder 46 is connected to output bus 50. The first output of the analysis unit 28 is connected to the output bus 51, and the second output of this unit is connected to the output bus 51.
The output is connected to AND gate group 49. Each of the multi-stage error detectors 24 ₁ , . . . 24 _k and the single error detector 23 have an input 53 ₁ , 53 ₂ , .
AND gates 52 ₁ , 52 ₂ , . . . with 53 _n
...52 _n (Figure 2). AND gate 52
The true and complementary outputs of ₁ , 52 ₂ , ...52 _n are connected to the inputs of flip-flops 54 ₁ , 54 ₂ , ...54 _n , and the outputs of these flip-flops are
Input 5 of AND gate 52 ₁ , 52 ₂ , ... 52 _n
5 ₁ , 55 ₂ , ...55 _n , the inputs 29, 30, 31 of the OR gate group 32 (Fig. 1), and the adder 56
(Fig. 2), and the output of this adder is connected to the inputs 25, 25', 26, 26' or 27, 27' (27, 27') of the analysis unit 28 via comparison circuits 57, 58. Connect to (Figure 1). The analysis unit 28 includes adders 59 (FIG. 3), 6
0 ₁ ,...60 _k , and the input of the adder 59 is ANDed with the second output of the single error detector 23 (FIG. 1).
It is connected to the first input of the gate group 61 (FIG. 3). The inputs of the adders 60 ₁ , . . . 60 _k are the second output of the multi-stage error detector and the AND gate group 61 (the third
Connect to the remaining inputs in Figure). The outputs of adders 59, 60 ₁ , ... 60 _k are AND
It is connected to the input of the OR gate 64 through gates 62, 63 ₁ , ... 63 _k , and the output of this gate is
It is connected to input 43 (FIG. 1) of logic unit 40, which has input 44 connected to the output of AND gate group 61. The logic unit 40 includes three groups of AND gates 65'.
(Fig. 4), 66, 67, and their output is
Connect to the input of OR gate 68. OR gate 68
The output of is the input 47 (first
(Figure). The auxiliary input of AND gate group 65 (FIG. 4) is connected to the output of control flip-flop 37. AND
The input 69 of the gate group 65 is connected to the input of the AND gate group 67 and to the second output of the analysis unit 28. Input 71 of AND gate group 65 is connected to the first output of register 1 in combination with input 72 of AND gate group 66 and input 73 of group 67. Group 6
Input 74 of register 1 is combined with input 75 of group 66 and input 76 of group 67 and is connected to the second output of register 1. The supplementary input of group 66 is the first input of analysis unit 28.
Connect to output. The remainder calculator 4 includes decoders 77 ₁ ,...77 _o
(FIG. 5), and the outputs of these decoders are connected to the inputs of modulo 78. The output of adder 78 is connected to input 15 of modulo 14. Decoder 7
The inputs of 7 ₁ and 77 _o are connected to the first output of register 1. The device of the invention operates as follows. An arithmetic number A to be checked (check arithmetic number) expressed in the remainder class notation system as follows is added to the input bus 3. A=(α ₁ , α ₂ , ...α _i ...α _o , α _o+1 ) (1) where α _i is the check operation number A for the absolute value P _i
It is the remainder of α _i ≡AmodP _i (i=1, 2,..., n+1). P ₁ , P ₂ , ...P _i ...P _o is the base of the number system of the remainder class within the operating range, and P _o+1
is the check cardinal number of the remainder class number system. Check operation number A is stored in register 1.
Part A' of operation number A = (α ₁ , α ₂ , ... α _i , ...
..., α _o ) is calculated from the output of register 1 by remainder calculator 4
is sent to input 5 of , where the calculated remainder of the check operator _A for the check base P determined by However, λi (i=1, 2,...,
n) is a scheduled constant. The calculated remainder α ¹ _o+1 from the output of the remainder calculator 4 and the actual remainder α _o+1 from the second output of the register 1 of the check operation number A are added to the inputs 15 and 16 of the modulo 14, respectively. The output of adder 14 produces the syndrome of check operand A as follows. δ _A ≡α ¹ _o+1 −α _o+1 modP _o+1 (3) The value of the syndrome δ _A is compared by the comparator 12 with the value of the error syndrome δΔ calculated as described below. The following signal sequence is sent from the output of the control unit 6 to the input 8 of the constant unit 7. First signal sequence: Based on this, the first output of the constant storage unit 7 generates the error value _Δi occurring in the remainder of the check operation number A. However, △ is the error value, and i is the number of the error remainder α _i (i=1, 2, . . . n). Second signal sequence: Based on this, the first output of the constant storage unit 7 gives the error values (Δ _i , Δ _j ) occurring in the two remainders of the check operation number A. However, i≠
j, and i, j=1, 2, . . . , n. Final (nth) signal string: Based on this, the first output of the constant storage unit 7 is the error value (△ ₁ , △ ₂ , . . . ) that occurs in all n remainders of the check operation number A.
△ _i , ...△ _o ). These error values are stored in the first constant storage unit 7.
From the output is sent to the input 10 of the error syndrome calculator 9. The output of calculator 9 is the following error syndrome δ
Generates △. The value of δΔ is compared in a comparator 12 with the value of the syndrome δ _A of the check operator A. If the syndrome of the check operation number A is equal to the error syndrome, that is, if δ _A =δ△, an error occurs in the check operation number A with the error syndrome δ△. In this case, X _i (i=1, 2, ..., n) is set to the value {0,
1} as one of the binary numbers X=X ₁ , X ₂ , ...X _i ,
..., X _o is from the second output of constant storage unit 7
It is sent to input 20 of AND gate group 18. The value of X _i is chosen equal to 1 when there is an error in the remainder α _i of the check operand A, and equal to 0 when there is no error in the operator A. The location where the binary number X is stored is determined by the number X _i ≠0 contained therein as follows.

When [formula], the binary number X is a single error detector remembered in 23,

When [Formula], the binary number X is stored in the multi-stage error detector ₂₄₁ , and the same applies hereafter.

When [Formula], the binary number X is stored in the multi-stage error detector 24 _k (k=n-1). Error syndrome δ△ and check operation number A syndrome δ
If _A is not compared, that is, when δ△≠δ _A ,
The AND gate group 18 is shut off and other possible errors in the check operand A are outputted from the constant storage unit 7. The conditions under which the binary number X occurs at the input of the single error detector 23 or at the input of one of the multiple error detectors 23 are stored in the analysis unit 28. It is found that only one of these detectors holds a binary number X for which X _i ≠0 (i=1,2,...n) during a given operating cycle of the device, and that Assume that an error is detected if this occurs several times, for example in the case of three newly given check operands. Under these conditions a logic 1 appears at the second output of analysis unit 28. With this logic 1, the binary number X indicating the incorrect remainder of the check operation number A is ANDed with the OR gate group 32.
It passes via a group of gates 33 to an input 34 of constant storage unit 7. Due to this logic 1, the syndrome δ A of the check operation number _A is further transferred from the output of the modulus 14 to the AND gate group 3.
6 to the input 35 of the constant storage unit 7. In this case, the following error values are provided from the first output of the constant storage unit 7 via the AND gate group 49 to the input 48 of the error correction adder 46. △=△ ₁ , △ ₂ , ..., △ _i , ... △ _o (5) The check operation number A is sent from the output of register 1 to input 4 of error correction adder 46 via logic unit 40
7 is given. The error value determined by the constant held in the constant storage unit 7 is subtracted from the check operation number A by an error correction adder 46, and the error occurring in the check operation number A is removed. The modified check operand A is passed from the output of adder 46 to bus 50. Single error detector 23 and multi-stage error detector 24
₁ ,...24 _k store a binary number X such that X _i ≠ 0 during a given operating cycle of the device (this condition is certified by the application of a logic 1 to the input of the analysis unit 28). ), the first output of the analysis unit 28 becomes a logical 1 and the device begins handling the new check operand A. If none of the detectors 23, 24 ₁ , _. . . 24 _k is found to hold a binary number means that there is no error. Now, in this case, analysis unit 2
The first output of 8 produces a logic 0, which causes the check operand A to be transferred from register 1 to logic unit 40.
and error correction adder 46 to output bus 50 . The device of the invention is such that the processor to be monitored is kept in operation, the latter being supplied via the input bus 3 to the current value of the check operand A and via the input bus 39 to the input 38 of the control flip-flop 37. It operates as described above to provide the former with a control signal (logic 1) that puts flip-flop 37 in the 1 state. It may be the case that the calculation process in the monitored processor ends, but an error remains in the check operand A. Under these conditions a logic 1 is placed on output bus 51 and control flip-flop 37 is in a 0 state such that a logic 0 from input bus 39 appears at its output. In this case, the check operation number A is passed through the logic unit 40 to register 1.
to the error correction adder 46, where it is stored until an error is detected and corrected.
This is evidenced by the occurrence of a logic zero on output bus 51. The operation of the multi-stage error detector 24i (FIG. 1) will be described next. However, i=1, 2,...k, and k=n-
It is 1. Before the multi-stage error detector 24i starts operating, the flip-flops 54 ₁ , 52 ₂ , . . . 54 _n (second
2) is assumed to be in one state due to a set bus line (not shown in FIG. 2). At this time, m=C ⁱ⁺¹ _o =n・(n-1)...(n-i)/(
i+1)i・(i−1)…1(6) The binary numbers X=X ₁ ,X ₂ ,…X _n are applied to the input 22i of the detector 24i and in this case the value of =1, 2,...m). When Xj = 1, a logic 1 from the true output of AND gate 52j is applied to the set input of flip-flop 54j if it is 1;
If it is 0, it is not added to the set input of that flip-flop. When X _i =0, a logic one from the complementary output of AND gate 52j is applied to the reset input of flip-flop 54j regardless of its state. Flip-flop 54 ₁ , 54 ₂ , ... 54 _n
The signal from the output of is applied to the input of adder 56. In this case, an addition result equal to 0 is accepted by the first comparison circuit 57 and an addition result equal to 1 is accepted by the second comparison circuit 58. The condition that the addition result is compared with 0 indicates that there is no error in the form given to the check operation number A. The condition for the addition result to be compared with 1 is that the error remainder of the check operation number A is found and this is revealed by the logic 1 obtained from the outputs of the flip-flops 54 ₁ , _{54 2} , . . . This shows what happens to the third output. Analysis unit 28 (FIG. 1) operates as follows. Single error detector 23 and multi-stage error detector 24 ₁ ,
...24 The signal from the first output of _k is AND gate 6
1 (Figure 3). The complement output of this gate produces a logic 0 to indicate that the check operand A is free of errors. Single error detector 23 and multi-stage error detector 24 ₁ ,
...24 The signal from the second output of _k is sent to the adder 59,
60 ₁ , 60 ₂ , ...60 _k . Each adder is a two-number cumulative adder having a bit position with an output. The signals applied to the adders 59, 60 ₁ , . . . 60 _k undergo an addition process. When the addition results are respectively equal to 3, they are AND gate 6
₂ , 63 1 , _{63 2} , . Logic unit 40 operates as follows. The output of the OR gate group 68 generates the check operand A under the following conditions. An error is found in the check operand A: in this case the signal applied to the input 70 of the AND gate group 67 enables the passage of the check operand A from the output of the register 1 to the output of the logic unit 40. There is no error in the check operation number A: In this case,
A signal applied to the complementary input of AND gate group 66 enables the passage of check operand A from the output of register 1 to the output of logic unit 40. There is an error in the check operand A, but the calculation process on the monitored processor is complete:
In this case, a signal applied from the output of the control flip-flop 37 to the complementary input of the AND gate group 65 allows the check operation A to be passed from the register 1 to the output of the logic unit 40. The remainder calculator 4 operates as follows. Check operation number A from the first output of register 1
is added to input 5 of remainder calculator 4. Remainder α ₁ , α of check operation number A with respect to the base number of the operating range
₂ , ...α _i , ...α _o are decoders 77 ₁ , ...7
7i... _77o (FIG. 5), respectively, and these outputs give the following values: qi=ηiα _i modP _o+1 (7) where i=1, 2,...n and η ₁ , η ₂ ,...
...η _o is a scheduled constant. The values of qi from the outputs of decoders 77 ₁ , 77 _{2 ,} . The calculated remainder of the check operation number A with respect to the check cardinal number is expressed by the following equation. or The present invention provides detection and correction of errors in data transmission or processing and requires no assumptions as to the nature of the error. When the present invention is used as a data processing and transfer method, the validity of the calculation results is perfect, so the reliability of the hardware may be low.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
3 is a block diagram of the multi-stage error detector, FIG. 3 is a block diagram of the analysis unit, FIG. 4 is a block diagram of the logic unit, and FIG. 5 is a block diagram of the remainder counter. 1... Register, 3... Input bus, 4... Remainder calculator, 6... Control unit, 7... Constant storage unit,
9... False syndrome calculator, 12, 57, 58... Comparator, 14... Modulus, 28... Analysis unit, 37
...control flip-flop, 40...logic unit,
46...Error correction adder, 52...AND gate, 5
4...Flip-flop, 56,59,60...Adder, 62,63...AND gate, 64,68...OR
Gate.

Claims (1)

[Scope of Claims] 1. A register 1 for storing a check operation number having an input 2 connected to an input bus 3, and a possibility of storing a constant to be added algebraically to said check operation number and resulting therein. A constant storage unit 7 stores a binary number which allows certain errors to be corrected and determines the erroneous remainder; an analysis unit 28 having a single error detector for discriminating erroneous remainders of the operand and a first output connected to the output bus 51 for indicating the occurrence of an error in the check operand;
and input 5 connected to the first output of register 1 above.
a remainder calculator 4 for calculating the remainder of the check operation with respect to a check criterion of the check operation, which has a function of detecting errors in the check operation; an error syndrome calculator 9 having an input 10 connected to the output 1 and an input 1 connected to the output of the remainder calculator 4;
5 and 16 connected to the second output of the register 1, and calculates the check operation number by algebraically adding the real remainder to the check criterion and algebraically adding the calculated remainder to the check criterion. a modulo 14 for calculating the syndrome of the error syndrome, an input 13 connected to the output of the modulo 14, and an input 11 connected to the output of the error syndrome calculator 9, for determining whether an error has occurred in the check operation number. a comparator 12 responsive to said error syndrome and said check operand syndrome in combination with the input 21 of said single error detector 23 and connected to the output of said comparator 12 via a group of AND gates 18; inputs _{22 1} , .
It has first and second outputs connected to terminals 6', 27, and 27', and calculates the error remainder of the check operation number by multi-stage analysis of the binary number at the position where it is assumed that there is an error in the check operation number due to an error syndrome. _multi -stage error detectors 21, . Input 4 connected to output
5 and an output connected to an input 47 of said error correction adder 46, indicating the location of an error within said check operand and enabling application of the check operand to said error correction adder 46. a control flip-flop 37 having an input 38 connected to the input bus 39 and an output connected to the input 41 of the logic unit 40 for selecting the mode of operation of the device; AND with input 8 of constant storage unit 7 and input 20 connected to the second output of said constant storage unit
a control unit 6 having an output connected to the input 19 of the gate group 18 and controlling the operation of the means for correcting the error check operand; a third output of the single error detector 23; error detector 24
₁ ,...24 Input 2 connected to the third output of _k
9, 30, 31 and via an AND gate group 33 to the output of an AND gate group 36 having a first input connected to the output of the modulo 14 and a second input connected to a second output of the analysis unit 28. a group of OR gates 32 having an output connected to an input 34 of the constant storage unit 7 having an input 35, a first input connected to a first output of the constant storage unit 7 and a second input of the AND gate group 33; a group of AND gates 49 having a second input connected to a second output of the analysis unit 28 connected to the output bus 50 and an output connected to a second input of the error correction adder having an output connected to the output bus 50;
An error detection and correction device in the processing of data represented by a remainder class number system in which the result of each operation is a check operation number. 2. The error detection and correction device according to claim 1, wherein each of the multi-stage error detectors has an input 5 connected to the output of the AND gate group 18.
3 ₁ , 53 ₂ , . . . 53 _n and an AND gate 52 ₁ , with true and complement outputs connected to the inputs _{of flip-flops 54 1 ,} 54 2 , . . . 54 _{n
52 2 , .}
…52 _n inputs 55 ₁ , 55 ₂ , 55 _n and the above
It is connected to the inputs 29, 30, 31 of the OR gate group 32 and the input of an adder 56, and the output of the adder is connected to the input of the analysis unit 28 via a first comparator circuit 57 and a second comparator circuit 58. 26', 27', and an error detection and correction device connected thereto. 3. In the error detection and correction device according to claim 1 or 2, the analysis unit 28 includes a plurality of adders 59, 61 ₁ , . . . 60 _k
, the input of adder 59 is connected to the second output of said single error detector 23, and the input of adder 59 is connected to the second output of said single error detector 23;
₁ ,...60 _k inputs are input to the multi-stage error detector 24.
₁ , ...24 _k and their outputs are ORed via AND gates 62, 63 ₁ , 63 _k .
The output of this OR gate is connected to the input 45 of the logic unit 40, the input 44 of which is connected to the input of the single and multi-stage error detectors 23, 24 ₁ , . . . 24 . _k
an error detection and correction device such as to be connected to the output of a group of AND gates 61 having an input connected to a first output of the circuit; 4. An error detection and correction device according to any one of claims 1 to 3, in which the logic unit 40 is an input of an OR gate 68 having an output connected to an input 47 of the error correction adder 46. The complement input of the AND gate group 65 is connected to the control flip-flop 37.
The input 69 of the AND gate group 65 is connected to the input 70 of the AND gate group 67 and the second output of the analysis unit 28;
The input 71 of the AND gate group 65 is connected to the input 72 of the AND gate group 66 and the AND gate group 67.
The input 74 of the AND gate group 65 is combined with the input 75 of the AND gate group 66 and the input 76 of the AND gate group 67. and the second output of register 1 above.
The complement input of AND gate group 66 is such that it is connected to the first output of analysis unit 28.