JPS6136254B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a microprogram-controlled data processing device, and more particularly to a data processing device having a function of expanding the address space of a main memory device. In recent years, the performance and functionality of microprocessors have significantly increased and they are approaching the realm of minicomputers. This is particularly the case with the expansion of main memory capacity, which has become one of the recent selling points of minicomputers. For a computer with a 16-bit word length, the maximum main memory capacity that can be addressed is basically ²¹⁵ , or 64K words, but due to advances in software, multi-task configurations, multi-computer design, etc., 64K words cannot be used at all. There is a shortage situation. Therefore, in many systems, as shown in FIG.
Auxiliary storage device 101 with drums and disks
is added to perform roll-in and roll-out of task groups in the non-resident task area in the main memory 100, and switch between multiple tasks. However, the S area and the global data (inter-task shared data) area in the main memory 100 reside permanently, narrowing the 64K address space. In addition, in systems that add special input/output devices using memory interfaces to non-resident task areas, restrictions are placed on the address space of the task area due to the address area of main memory allocated to the input/output devices. . Furthermore, in dual systems and multisystems, it is necessary to be able to refer to the main memory (or data) of other systems, so expanding the address space of the main memory is essential for the versatility of the computer. In the past, attempts have been made to expand the main memory address space, especially in the field of minicomputers, but
The main methods are the mapping method and the bank register method. A conceptual diagram of the mapping method is shown in FIG. 2, and will be explained. A main memory address with a word length of 16 bits is stored as a logical address in the main memory address register 200, and is divided into two or more segments. For example, the lower 12 bits of segment 2b become the lower 12 bits of the physical address. , the remaining upper 4 bits of segment 2a
serves as an address specification for the small capacity storage device 202 in which data for address expansion has been written in advance,
For the above 4-bit information, the decoder 201 selects one word (the word length is, for example, 8 bits) 2c in the small capacity storage device 202 to create a physical address of 20 bits in total, and a maximum of 1M words between addresses.
Although the contents of the small capacity storage device 202 are dynamically rewritten and complex mapping becomes possible, problems arise such as an increase in circuit scale and delays associated with creating physical addresses. Another bank register system will be explained with reference to FIG. A bank is a unit of main memory divided into bank registers, and FIG. 3 shows a case where one bank has 64K words. Therefore, the 16-bit content 36 of the main memory address register 200 becomes part of the 20-bit physical address (address within the bank), and bank switching is performed by the decoder 300 due to an external factor 3a such as a code in the instruction register. This is done by one word (for example, 4 bits) 3c of the small capacity storage device 301 that is selected, and finally
Create a 20-bit physical address. In the case of this method, the configuration is somewhat simpler than that of the mapping method, but its control is still troublesome. In either method, incorporating these main memory address space expansion mechanisms into a microprocessor results in (1) an increase in the number of pins, (2) an increase in the degree of integration, and (3) an increase in element delay. occurs. On the other hand, if the above mechanism is provided outside the microprocessor, the number of components, which is the most important feature of the microprocessor, will increase, and the access time for main memory reference will increase. The present invention has been devised in view of the above-mentioned drawbacks of the prior art, and its purpose is to reduce the increase in the number of package pins and the degree of integration of a microprocessor, and to increase the access time of expanded main memory. The purpose of the present invention is to provide a data processing device whose main memory can be expanded without having to do anything. A feature of the present invention is that the microprogram in a data processing device that is microprogram controlled uses the fact that each macro instruction flows through a different microprogram address, and when passing through a predetermined microprogram address, This is detected and the address space of the main memory is expanded only when the microinstruction refers to the main memory. Preferred embodiments of the present invention will be described in detail below based on the drawings. FIG. 4 is a block diagram of the entire data processing apparatus to which the present invention is applied. This configuration includes a microprocessor 400 that is the center of data processing, a fixed memory address register 401 that specifies the address of the microprogram, a fixed memory device 402 that stores the microprogram, and the microprocessor 40
Bus drive circuit 403 between input/output bus 0 and data bus, main memory address register 200, main memory 1
00, and a main memory expansion device 404. The operation of this device will be explained below. (i) Execution of microinstructions A microprogram address that corresponds one-to-one to a macroinstruction determined by the microprocessor 400 is placed in the fixed memory address register 401 by the clock 4i via the signal line 4c. . The address information of the microprogram stored in the register 401 is transferred to the fixed storage device 4 via the microprogram address bus 4a.
A predetermined microinstruction is read out from the microprocessor 400 through the signal line 4b, and processing according to the microinstruction is performed.
The microprogram is divided into macroinstructions, and the macroinstructions are executed as shown in the flowchart shown in FIG. That is, the presence or absence of an interrupt is determined, and if there is no interrupt, the macro instruction is read from the main memory 100, decoded, and the address of the operand is calculated via the "status routine" for each decoded macro instruction. The execution routine branches into multiple execution routines 1 to N, and processing is performed in each execution routine. After this execution is completed, the process returns to determining the presence or absence of an interrupt. On the other hand, if there is an interrupt, the microprogram is moved to the interrupt processing routine and processed, and after the processing is completed, the process returns to determining whether or not there is an interrupt. Further, the microprogram control format is a advance control method in which the next microinstruction is read out while a microinstruction is being executed, as shown in FIG. (ii) Reference to main memory 100 The main memory address created inside the microprocessor 400 is loaded onto the common bus 4e through the input/output bus 4d of the microprocessor 400. This address data is placed in the main memory address register 200 and communicated to the main memory 100 via the address bus 4g, while the microprocessor 400 outputs an activation signal 4j to the main memory 100. Data read from main memory 100 is input to microprocessor 400 via data bus 4f, bus drive circuit 403, common bus 4e, and input/output bus 4d.
The completion of access to the main memory 100 is notified from the device to the microprocessor 400 via the signal line 4k. On the other hand, the main memory expansion device 404, which is a characteristic part of the present invention, decodes the microprogram address on the bus 4a and decodes the main memory address bus 4a.
Create a signal line 4h that extends g. Next, a detailed example of the main memory expansion device 404, which is a feature of the present invention, will be explained with reference to the drawings. FIG. 7 is a detailed circuit diagram of the main memory expansion device 404. Its structure consists of a microprogram address decoder 700, a clock gate 701, and a flip-flop 702 for instructing main memory expansion. Refer to FIG. 8 for an explanation of the operation of this circuit. The microprogram number placed in the fixed memory address register 401 by the falling edge of the clock 4i is
The address is placed on bus 4a, which is decoder 70
0 is detected and a signal 7a is obtained. Main signal 7a
clock gate 701 between clock 4i
The logical AND is performed by the flip-flop 70
Main memory expansion signal 4h
get. The release (reset) condition for flip-flop 702 is the fall of access end signal 4k from main memory 100, as shown in FIG. 8, and is also reset by system initialization signal 7c. According to the circuit explained above, the main memory is a flip
The system has an address space equivalent to one bit of flop 702, that is, twice as much address space. FIG. 9 shows a method of accessing the main memory address space. As shown in the following table, for example, the data to be decoded at a 12-bit fixed memory address is determined in advance, and data 3CO to F, 7CO
~F, BCO~F, and FCO~F, the decoder 700 is configured.

[Table] When passing through this fixed memory address, bank 1 (64K
(above) main memory is referenced, otherwise bank 0 (64K or less) is referenced. That is, for example, assume that a microinstruction "LDACC" that accesses data from main memory and stores the data in register 902 in microprocessor 400 is stored at addresses 2CO and 3CO in fixed memory. When executing the microinstruction stored at address 2CO, main memory 9 of bank 0
The data of 00 is transferred to the register 902, but
When the microinstruction stored at address 3CO is executed, the above address is detected by the decoder 700, so that the data in the main memory device 901 of bank 1 is transferred to the register 902. In this way, even if the same microinstruction is stored, the address of the main memory can be changed depending on the fixed memory address where the instruction is stored, and the space can be expanded. The above is an example of expanding the main memory to 128K words in banks 0 and 1, but according to the present invention, it is essentially possible to further expand the address space. An example of expanding the address space to 1M words will be explained using FIG. The configuration of this device is a programmable logic array (hereinafter abbreviated as PLA) 1000 that decodes all bits of the microprogram address bus 4a, and a clock that takes the AND of the output patterns 10a to 10d of this PLA 1000 and the clock 4i. Consists of a gate group 701a-d and a flip-flop group 702a-d set by the output. Inside PLA1000 is AND array 1000
a, 1000b etc. and R array 1000c, 10
00d, etc., and the result decoded by the AND array can be output as a predetermined pattern by the R array. That is, PLA
There are 16 patterns of 10a to 10d of 1000 outputs (4 bits) from O to F, and by switching 16 banks of the main memory, an address space of 1M words can be obtained as a whole. Now, if we decode the microprogram address on bus 4a and obtain a pattern of "0110", each signal 10a-d will be sent to clock gate 7.
01a to 01d, the clock 4i is set to the gate 701.
b, 701c only, signals 10f, 10g
via flip-flops 702b, 702c
only the flip-flop 702a,
702b remains unchanged. As a result, bank designation signals 10i to 10l are "0110", that is, bank 6 is designated. The flip-flops 702b and 702c are reset by the access end signal 4k from the main memory, and also by the system initialize signal 7c, and after being reset, bank 0 (64K or less) is designated. As described above, according to the illustrated embodiment, expansion of the address space of the main memory in a microprogram-controlled data processing device can be done without making any changes to the microprocessor and by adding very few parts. This can be achieved. As described in detail above, a preferred embodiment of the present invention provides a data processing device of this type that can expand the address space of the main memory without increasing the input/output pins or the degree of integration of the microprocessor. can.

[Brief explanation of the drawing]

Figure 1 shows the use of main memory in a normal computer system, Figure 2 shows the mapping method, which is a conventional main memory expansion method, and Figure 3 shows the bank register, which is a conventional main memory expansion method. 4 is a block diagram of the entire data processing device to which the present invention is applied, FIG. 5 is a flow diagram of macro instructions, FIG. 6 is a time chart of microprogram control, and FIG. 7 is a diagram of the present invention. Fig. 8 is a time chart for explaining the operation of the main memory expansion device, Fig. 9 is a diagram showing how the address space of the main memory is expanded, and Fig. 10 is the main memory expansion. FIG. 3 is a circuit diagram showing another example of the device. 700...decoder, 701...clock gate, 702...flip flop.

Claims (1)

[Claims] 1. In a microprogram-controlled data processing device in which a microprocessor sequentially specifies addresses in a microprogram memory and sequentially reads microinstructions specified by the addresses to process data in a main memory device, the microprogram address bus temporary storage means for temporarily storing information decoded by the main memory expansion decoding means connected to the main memory expansion means; and outputting the output of the temporary storage means to the main storage device as a main memory expansion bit line of an address bus of the main storage device. the decoding means detects that the address of the microprogram memory becomes a predetermined address, the detection result is stored in the temporary storage means, and the contents of the temporary storage means are stored in the main memory. A data processing device controlled by a microprogram, characterized in that bits are output to a main memory device as address space expansion bits of the device.