JPS6135631B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory, and particularly to a memory structure suitable for a semiconductor memory using a MOS transistor (hereinafter referred to as MOST). Specifically, it is a half-precharge memory that includes dummy cells and has substantially equal charging and discharging waveforms.

[Background of the Invention] In order to facilitate understanding of the present invention, a dummy cell will first be explained, then a half precharge memory will be explained, and finally, problems will be clarified.

(1) Explanation of dummy cells Conventionally, two sets of data lines are used to detect potential changes in data lines that appear when data is read from a memory cell, with a memory cell connected to one and a reference voltage applied to the other. There is a method that combines dummy cells that generate .

FIG. 1A shows a memory cell having dummy cells.

A memory cell MC is provided at the intersection of word line W ₀ and data line D ₀ , and a dummy cell DMC is provided at the intersection of dummy word line DW and data ₀ .

A memory cell MC consists of a single MOST and a capacitor connected in series with it.

Further, as a dummy cell, there is one shown in, for example, Japanese Unexamined Patent Publication No. 40246/1983.

In this dummy cell, the storage capacitor has the same capacitance as the memory cell, and the dummy cell has the potential of "1" and "0" used when storing "1" and "0" in each memory cell. It is charged to a potential between .

Dummy word line DW and word line W ₀ are selectively driven, respectively, to couple memory cell MC and dummy cell DMC to data lines D ₀ and ₀ , and change their respective potentials.

The preamplifier PA differentially detects this potential change and reads out the stored information.

FIG. 1B is a diagram showing potential changes of the data line.

Here, the reason why the dummy cell is necessary is as follows.

In conventional memory, before driving the word line _W0 and dummy word line DW, the data line is
D ₀ and ₀ are charged to a high voltage (V _{CC )} of the memory cell write voltage. This is called flip charge.

When "0" is stored in the memory cell MC, when the word line W ₀ is driven at time t ₀ , the capacitance of the data line D ₀ exhibits a curved waveform.
It is stabilized at a potential determined by the distribution ratio between the capacitance of the data line D ₀ and the storage capacitance of the memory cell MC. In this case, even without the dummy cell DMC, the data lines D ₀ ,
Since a potential difference occurs between the preamplifier PA and _the preamplifier PA at time _t1 , it becomes possible to read the stored information.

On the other hand, when "1" is stored in the memory cell MC, even if the word line W ₀ is driven, the potential of the data line D ₀ does not change as shown in FIG. In this case, if there is no dummy cell DMC,
Since there is no potential difference between the data lines _D0 and _D0 , normal storage information reading cannot be performed even if the preamplifier PA is subsequently driven at time _t1 .

In this way, the dummy cell is required to set the potential of data line 0 to the intermediate potential ( _{C in the figure) between the two potentials acquired by the potential of data line D 0 from} which the memory cell is read. It can be said that this is a reference voltage generation means for the preamplifier PA.

(2) Explanation of half-precharge memory On the other hand, there are memories whose dummy cell DMC is basically unknown, such as in JP-A-52-113131.
It is shown in the publication No. In this memory, before driving the word line, the data line is set to the high potential (V _CC ) and the low potential (0) of the write voltage of the memory cell.
It is charged in advance to a potential between . This is called half puri charge. The structure of this memory is shown in FIG. 1C. The difference from FIG. 1A is that data line ₀ does not have a dummy cell or a dummy word line.

FIG. 1D shows potential changes on the data line.

Assume that "1" is stored in memory cell MC1. Data lines D ₀ and ₀ are set to V _CC /
It is charged to 2.

When word line W ₀ is selected at time t ₀ ,
The storage charge of the memory cell MC1 flows onto the data line, and the potential of the data line _D0 rises as shown in (D).
On the other hand, the potential of data line ₀ remains at V _CC /2. As a result, a potential difference is generated between the data lines _D0 and _D0 , allowing the preamplifier PA to read stored information.

On the other hand, it is assumed that "0" is stored in the memory cell MC1. This time, the charge stored in the data line D ₀ flows into the storage capacitance of the memory cell MC1, so that the potential of the data line D ₀ falls as shown in FIG. On the other hand, the potential of data line ₀ is V _CC /2
It remains as it is. As a result, a potential difference is generated between the data lines _D0 and _D0 , allowing the preamplifier PA to read stored information.

In this way, in a memory using the half precharge method, the precharge voltage itself is
Since it becomes a reference voltage for PA, a means for generating a reference voltage such as a dummy cell is not originally required.

For this reason, half pre-charge memories, such as the memory described in Japanese Patent Laid-Open No. 52-113131 mentioned above and the memory described in Japanese Patent Laid-Open No. 50-98249, do not have dummy cells.

(3) Problems However, the inventor of the present application has confirmed that the half-precharge memory has the following drawbacks.

When word line W1 is selected, word line W1
At this time, since there is a capacitance between the word line and the data line, when a pulse voltage is applied to the word line, a combined voltage appears on the data line via this capacitance. As a result, the read voltage from the original memory cell overlaps with the voltage.

FIG. 1E shows changes in the data line voltage when "0" is written in the memory cell MC1 so as to clarify the problem.

In the figure, the waveform (g) is the potential waveform of the data line when it is affected only by the voltage change of the word line W1. The waveform shown in FIG. 2 is an ideal potential waveform of the data line when the memory cell is read without the above-mentioned capacitive coupling.

In reality, the waveform change is the sum of the waveform G and the waveform I, that is, the waveform change shown in the figure. As a result, the potential difference from V _CC /2 becomes smaller than the ideal waveform, resulting in a disadvantage that the operating margin is reduced. In other words, G acts as noise.

[Object of the Invention] An object of the present invention is to solve the above problems and provide a memory with a large operating margin.

[Summary of the Invention] The present invention is configured such that a word line and a dummy word line are capacitively coupled to both sides of a data line pair in a half precharge memory. Thereby, the voltage fluctuation of the data line pair due to capacitive coupling from the word line is offset by the combined voltage of the dummy word line, thereby expanding the operating margin.

[Embodiments of the invention] Examples of the present invention will be described below.

In FIG. 2, a plurality of memory cells MC are connected to data lines d ₀ and ₀ , respectively. The data lines d ₀ and ₀ are made of the same material and have the same geometric dimensions. As the memory cell MC, a known memory cell consisting of, for example, the same MOST and a capacitor connected in series is connected. In the figure, one memory cell connected to data line d ₀ is shown. A plurality of memory cells of the same number are connected to the data lines d ₀ and ₀ . When this memory cell is selected by the word line W connected to it, it changes the potential of the data line to which it is connected by a value corresponding to the signal stored in its capacitor. For example, a value of +7.0 (V) as a high level signal or 0 (V) as a low level signal is stored in this capacitor. data line
d ₀ , ₀ is set in advance to a potential of about half the power supply potential (V _DD (=10) (V)) (to be exact, 4 (V)) in response to the precharge signal before reading the storage signal of the memory cell. ) is connected to precharge means for precharging the data lines ₀ and _d0 , as will be described later. Specifically, MOSTQ _P and _P act as this precharging means. Therefore, when a storage signal is read from a memory cell, the potential of the data line connected to that memory cell becomes the above 4 (V).
The potential will be slightly larger or smaller.

A dummy cell DMC is connected to the data lines d ₀ and ₀ , and is coupled to the data line via a dummy word line DW. In the figure, only dummy cells and dummy word lines connected to data line ₀ are shown. When reading memory cells connected to data lines ₀ and _d0 , dummy cells connected to data lines ₀ and _d0 are read respectively. The dummy cell serves to set the potential of the data line to an intermediate value between two values that the potential of the data line from which the memory cell is read corresponds to the contents of the memory cell.

The preamplifier PA is a flip-flop consisting of a cross-coupled transistor _Q1 , ₁ , and the input node
d ₁ , ₁ are connected to data lines d ₀ , ₀ by MOSTQ ₀ , ₀ , respectively. This preamplifier PA is
After reading the storage signal from the memory cell, it is detected which of the data lines d ₀ and ₀ has a higher potential, and the detection result is held. connected in series
MOSTs ₃ and ₆ are for connecting the power supply V _DD to the data line ₀ and charging the potential of the data line ₀ to a potential close to V _DD . Similarly connected in series
MOSTQ ₃ and Q ₆ are for connecting the power supply V _DD to the data line D ₀ and charging the potential of the data line d ₀ to a potential close to V _DD . Also, transistors ₄ and ₅ and Q ₄ and Q ₅ connected in series connect data lines ₀ and d ₀ to ground, respectively, and
This is to discharge each of ₀ and d ₀ to the ground potential. The gates of MOSTQ ₄ and ₄ are respectively
It is connected to the gates of MOSTQ ₁ and ₁ and is controlled in response to the detection results from this preamplifier PA.
MOSTQ ₃ and ₃ gates respectively
MOSTQs ₂ and ₂ are connected to the input nodes d ₁ and ₁ of the preamplifier PA, respectively. this
MOSTQ ₇ and ₇ are connected to nodes n and which connect MOSTQ ₃ and Q ₂ and ₃ and ₂ , respectively. These MOSTQs ₇ , ₇ connect these nodes n, to the gates of MOSTQs ₃ , ₃ , and
This is to precharge the voltage required to turn on the MOST. That is, when a high-level precharge signal P is applied to the gates of _MOSTQ7 , ₇ , nodes n precharge to the power supply voltage _VDD, respectively.

Below, using the time chart showing the various control signals and voltages at various points shown in FIG.
The operation of the circuit shown in the figure will be explained.

Before reading the signal from the memory cell, the signal is ₀ .
It is held at a potential of 10 (V). As a result, MOSTQ ₀ , ₀ are in the on state. In this state, the precharge signal P is initially at a high level (12
(V)). As a result, the data line d ₀ , ₀
are 4 by MOSTQ _P , _P connected to them
(V). At the same time, MOSTQ ₇ and ₇ are turned on by this precharge signal P, so that node n is precharged to the power supply potential V _DD . Thereafter, the precharge signal P is lowered to 0 (V) while the signal ₀ is held at a high level. As a result, the precharging of the data lines d ₀ and ₀ ends, and the precharging of the node n also ends with MOSTQs ₇ and ₇ turned off.
After this, the word line W connected to the memory cell MC
Start up and read out the memory cell MC. As an example, a case will be described in which a memory cell MC connected to data line ₀ is read. this memory cell
When reading MC, data is also read to the dummy cell DMC connected to the data line d ₀ via the dummy word line DW. The potential of the data line _d0 changes from the original precharge potential of 4 (V) to 4.1 (V) or 3.9 (V) in accordance with the read storage signal of the memory cell MC. At this time, nodes d ₁ and ₁ also change in the same way. As an example, a case will be described below in which the potentials of the data line d ₀ and the node d ₁ change to 3.9 (V). The potential of data line ₀ hardly changes.

During the above period, a high voltage (10 (V)) φ ₀ is applied to both the sources of MOSTQ ₁ and ₁ of the preamplifier PA, and the voltage between the source and gate of each MOSTQ ₁ and ₁ is ₁ , which is smaller than the threshold value Vth of ₁ (which is approximately 1 (V)). Therefore, both MOSTQ ₁ and ₁ in the preamplifier PA are in the off state. After that, signal ₀ becomes low level (0
(V)), MOSTQ ₀ , ₀ turns off. At this time, the magnitude of the signal read out from the memory cell is taken into the nodes d ₁ and ₁ . When signal ₀ drops to low level, the preamplifier
PA starts its amplifying effect, turning one of MOSTQ ₁ , ₁ on and the other off. In the example I'm thinking of now,
Since the potential of node d ₁ is greater than the potential of node ₁ , MOST ₁ is turned off and Q ₁ is turned on. As a result, due to the action of the preamplifier PA, the potential of the node ₁ decreases only slightly, and the potential of the node _d1 rapidly decreases to 0 (V). In this way, the preamplifier PA
As a result, the signal of the memory cell is detected and held. This preamplifier has nodes d ₁ ,
This means that the potential difference of d ₁ is amplified. This width increase
Since this is done with MOSTQ ₀ and ₀ off,
It's done extremely fast.

Here, when increasing the width using the preamplifier PA,
Keeping MOSTQ _0,0 off has _the following benefits: That is, in addition to the pair of data lines shown in FIG. 3, many pairs of data lines are provided, and charging and discharging, which will be described later, are performed on these data lines at the same time. As a result, the potential of the word line changes through the coupling capacitance between the word line, which is provided in common with these data lines and intersects with these data lines, and these data lines.
This change again causes a voltage change on each data line via this coupling capacitance. This change in the voltage of the data line may act as noise and adversely affect the amplification effect of the preamplifier PA, but since MOSTQ ₀ and ₀ are in the off state, such a problem does not occur.

The detection results of this preamplifier PA are MOSTQ ₂ ,
It is transmitted to the control electrodes Q ₄ , ₂ , and ₄ . That is, when the node d ₁ is at a high level and the node ₁ is at a low level, MOSTQs ₂ and ₂ are in the on and off states, respectively, and MOSTQs ₄ and ₄ are in the on and off states, respectively. As a result, node n is
It is discharged to a low level (0 (V)) through MOSTQ ₂ and Q ₁ , and MOSTQ ₃ is turned off. On the other hand, the node does not discharge and is held at a high level. When the signal φ ₁ is changed from low level (0 (V)) to high level (10 (V)) in this state, MOSTQ ₅ ,
Since Q ₆ , ₅ , _{and 6} are on and MOST ₄ is off, data line ₀ is not connected to ground, so data line ₀ is not discharged, but
Since MOSTQ ₄ and Q ₅ are on, the data line d ₀ is connected to ground, and the data line d ₀ is connected to this MOSTQ ₄ ,
Discharge through _Q5 . On the other hand, since MOST ₃ and ₆ are on, the data line d ₀ is charged to a potential close to the power supply V _{DD (} approximately 8 (V)).
The signal _φ1 is inputted to the gates of 3 and ₃ via the putot strap capacitor C _B . This putostrap capacitor consists of a capacitor using an inversion layer. A capacitor using this inversion layer is known, for example, from the following document.

REJohnson et al. “Eliminating Threshold
Losses in MOS circuits by Boots trapping
Using Varactor Coupling”IEEE J.of Solid―
State Circuits SC-7, No. 3p, 217 (1972.6).

The electrode of this capacitor connected to MOSTQ ₃ or ₃ is connected to the gate electrode on the inversion layer,
The electrodes connected to MOSTQs ₅ and ₆ are connected to a diffusion layer connected to this inversion layer.
As a result, the bootstrap capacitor C _B connected to the node is held at a high level.
It has a relatively large capacitance. Due to the action of this capacitor, when the signal _φ1 goes high, the node returns to its original precharge level of 1.0.
(V) will be raised to an even higher level of 12 (V).
As a result, the source potential of MOST ₃ is approximately equal to the power supply voltage V _DD (10 (V)), and the data line ₀ has a potential (approximately 8 (V)) lower than the power supply voltage V _DD by the voltage drop caused by MOSTQ ₆ . ) is charged. Thus, the bootstrap capacitor C _B is
When charging the data line, the voltage drop due to MOST ₃ is reduced to almost zero, thereby helping to increase the charging potential of the data line. On the other hand, MOSTQ ₃
Since the node n of the bootstrap capacitor C _B connected to the gate of is held at a low potential (0 (V)), the capacitance of this capacitor is almost equal to zero. The potential of node n hardly increases even if signal _φ1 is applied.

As described above, the potentials of the data lines d ₀ and ₀ are discharged or charged to different levels depending on the read storage signal of the memory cell. Using the potential of the data line after charging or discharging, the signal is rewritten to the original memory cell, and the data line
The potential of d ₀ , ₀ can be sent to the outside and used as an amplification signal for the storage signal of the memory cell. In particular, in the present invention, the data line d ₀ , _{0 is placed approximately halfway between the potentials of the data lines d 0 and 0} after being charged and discharged.
Precharge d ₀ and ₀ in advance. The conductance of MOSTQ ₃ , ₆ for charging this data line d ₀ and the conductance of MOSTQ ₆ for discharging this data line d 0
The conductances of MOSTs ₄ and ₅ are selected so that charging and discharging of the respective data lines are performed while giving the same potential change over time. moreover,
The conductance of MOSTQ ₄ , Q ₅ for discharging data line d ₀ and for charging data line d ₀
The conductances of MOSTs ³ and ₆ are selected so that the respective data lines are discharged and charged while giving the same potential change over time.

As described above, after reading the signal from the memory cell and rewriting it to the memory cell,
Return all control signals to their original precharge levels. In this manner, the memory cell read cycle is completed.

According to this embodiment, when a word line is driven to read storage information from a memory cell connected to one data line, the dummy word line of the other data line is driven, so that the combined voltage is applied to both data lines. This creates a balance and ensures an operating margin.

In addition, since the dummy cell is connected to the dummy word line, not only the coupling capacitance between the dummy word line and the data line but also the gate capacitance of the transistor provided between the data line and the dummy word line is added, so the coupling voltage increases. becomes larger and better balanced. This is because the memory cell also has a gate capacitance of a transistor, and the combined voltage is therefore larger than that in the case of only the combined voltage from the word line to the data line.

FIG. 4 shows another circuit example. This memory does not have MOSTQ ₄ , Q ₅ , _{4 , 5 of the} memory shown in FIG. signal
₀ ′ is used. This signal ₀ ′ is the previous signal
It changes from high level (10 (V)) to low level (0 (V)) at the same timing as ₀ . ₀ ′ is the signal
₀ , when the signal _φ1 changes from low level to high level, it changes from this low level to the original high level at the same time. A time chart of various signals and voltages at various points related to the memory shown in FIG. 4 is shown in FIG. In the memory of this circuit example, the data line d ₀ , ₀ charging is performed in exactly the same way as in the memory of FIG. 2. In the memory of this circuit example, the data
The discharges of d ₀ , ₀ are MOST ₀ , ₁ and MOST, respectively.
The difference from the memory shown in FIG. 2 is that the process is performed through Q ₀ and Q ₁ .

The operation until a storage signal is read out from the memory cell onto the data line _d0 , this signal is amplified by the preamplifier PA, and node n or is discharged according to the amplification result is shown in Figure 2. It is exactly the same as the memory of . After this discharge has taken place, the signal φ ₁
MOSTQ ₀ , ₀ is a signal when changing to high level
₁ turns it on. Data as an example
The case where a low level signal is read from the memory cell connected to D ₀ will be described below. In this case, after the signal is amplified by the preamplifier PA, MOSTQ ₁ and ₁ are in the on and off states, respectively. Therefore, data line ₀ will not discharge through MOST ₁ even though MOSTQ ₀ is on. On the other hand, since MOSTQ ₁ is on, data line d ₀ is discharged to signal line ₀ through MOSTQ ₀ and Q ₁ .

Therefore, the charging of data line ₀ by MOSTQ ₃ and Q ₆ and the discharging of data line d ₀ by MOSTQ ₀ and Q ₁ are performed on the first and second data lines so that the voltage changes over time are equal. These MOST
Select the conductance of . Furthermore, similarly
Charging of data line d ₀ by MOSTQ ₃ , Q ₆ ,
The discharge of data line ₀ by MOST ₀ and ₁ is performed so that the voltage changes over time are equal.
Select the MOST conductance.

As can be seen from the above, this embodiment is simpler than the memory shown in FIG. 3 in that MOSTQ ₄ , Q ₅ , ₄ and ₅ are not required.

In this embodiment, as in the previous embodiment shown in FIG. 2, a coupled voltage is generated on each of the pair of data lines and balanced.

FIG. 6 shows an example of another circuit. This circuit is the fourth
The discharge circuit at node n is different from the circuit shown in the figure. Node n, discharges to signal source ₁ ' via MOSTQ ₂ , _2, respectively. FIG. 7 shows a time chart of control signals and voltages at various points related to this embodiment. In the figure data line d ₀ , ₀ , node
The voltage at node n, _d1,1 , indicates a case where _a low level signal is read out by the memory cell connected to data line _d0 . Signal ₁ ′ is preamplifier PA
High level (10 (V)) when the width increase by
It switches from to low level (0 (V)). As a result, only node n is discharged and has a low level voltage. After that, by changing φ ₁ , ₀ ' from low level to high level, data line D ₀
is discharged to ground potential through MOSTQ ₀ , Q ₁ ,
Data line ₀ is charged to about 8 (V) by power supply V _DD through MOST ₃ and ₆ .

In addition, as in the above circuit example, MOSTQ ₃ , Q _6
3 , ₆ and the power supply V _DD can also be connected to _{the node d 1,1 instead} of being connected to _the data line d _0,0 . Similarly, MOST ₄ , ₅ and ₄ , ₅ in the circuit of Figure 2
A discharge circuit consisting of a ground power supply and a data line d ₀ , ₀
Instead of connecting to node d ₁ , 1, it is possible to connect to node d 1 , ₁ . In these cases, the signal in Figure 3
It is necessary to use the signal ₀ ' used in the circuits of FIGS. 5 and 7 instead of ₀ .

[Effects of the Invention] According to the present invention, in a half-precharge type memory, by providing an essentially unnecessary dummy cell, imbalance in data line potential caused by the voltage coupled to the data line by the word line can be reduced. Therefore, it is possible to realize a memory that has a large operating margin and is less likely to malfunction.

[Brief explanation of the drawing]

1A to 1E are diagrams for explaining a conventional memory, and FIG. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a diagram for explaining the operation of the circuit in FIG. 2, FIGS. 4 and 6 are circuit diagrams showing other embodiments of the present invention, and FIGS. FIG. 7 is a diagram for explaining the operation of the circuit shown in FIGS. PA...preamplifier, _D0 , ₀ , _d0 , ₀ ...data line, _Q0 , ₀ ...connection MOST, _Q3 , _Q6 , ₃ , ₆ ...
MOST for charging, Q ₄ , Q ₅ , ₄ , ₅ ... for discharging
MOST, DMC...dummy cell, DW...dummy word line.

Claims (1)

[Scope of Claims] 1. A pair of data lines, a plurality of word lines arranged to intersect the pair of data lines, and a dummy word line arranged to intersect the pair of data lines, each of which: a plurality of memory cells provided at the intersections of the pair of data lines and the plurality of word lines; a dummy cell provided at the intersection of the pair of data lines and the dummy word line; After the dummy cell is connected to the data line and connected to the other data line by the dummy word line, the potential of the data line pair is charged and discharged to a predetermined high potential and a predetermined low potential based on the stored information of the memory cell. a charging/discharging circuit, wherein the pair of data lines are charged to a first potential between the high potential and the low potential before the word line is selectively excited. In the memory, the charging/discharging means discharges the potential of the other data line to the predetermined low potential with a change waveform substantially the same as the change waveform of the potential at the time of charging. 2. In claim 1, the dummy cell, when the dummy word line is excited, sets the data line to which the dummy cell is coupled to approximately the same potential as the potential before the dummy word line was excited. memory. 3. The memory according to claim 1, wherein the predetermined high potential is a power supply potential. 4. The memory according to claim 1, wherein the memory cell comprises a single transistor and a capacitor connected in series with the transistor. 5. The memory according to claim 1, wherein the first potential is approximately an intermediate potential between the high potential and the low potential.