JPS6135607A - Logical filter circuit - Google Patents

Abstract

PURPOSE:To decrease the number of digital comparators by inputting N-set of digital input signals to positive/negative logical operating circuits via common N(N-1)/2-set of digital comparators. CONSTITUTION:N-set (three in this example) of input digital signals and signals through delay circuits 2, 3 are inputted respectively to the 1st and 2nd SW element groups 23, 27 and also inputted to N(N-1)/2-set of digital comparator (DCP) groups 33. An output of the DCP groups 33 is inputted respectively to the 1st and 2nd logical circuits 34, 35, where a prescribed operation is conducted, and output of the circuits 34, 35 controls respectively the SW element groups 23, 27. The DCP groups 33, the circuit 34 and the SW element group 23 constitute the positive logical operating circuit 5P, and the DCP groups 33, the circuit 35 and the SW element group 27 constitute the negative logical operating circuit 5M. A positive noise is suppressed in the circuit 5P and negative noise is suppressed in the circuit 5M, the outputs of the element groups 23, 27 are added (15) and averaged at a 1/2 circuit 16 and the result is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a logical filter circuit for extracting a desired signal from a multiplexed signal of a plurality of signals including noise and the like.

Background technology and its problems For example, in the case of a television signal, the energy of image information is concentrated in integral multiples of the horizontal frequency, so a comb-shaped filter that takes advantage of this property is included in the television signal. It separates noise and separates luminance signals and color signals. An even more advanced technique is Hadamard transform processing, which is used in broadcasting equipment.

However, although these conventional filters improve the S/N, which is the energy ratio between the image signal and unnecessary signals (such as noise), the rise and fall of the steps of the extracted original signal are dulled, resulting in a deterioration in image quality. occurs.

This can be said to be a fundamental problem with conventional filters that separate and extract desired signals in frequency space.

By the way, the inventor of the present application previously proposed a new logical filter device called a logical filter in 1983-9837.
No. 1, etc.). That is, conventional filters convert a signal that changes in the time dimension into a frequency dimension by Fourier transform, and filter the frequency components. In contrast, [logical filters] treat signals that change in the time dimension as a set of patterns, and perform filtering by converting these patterns.

Such a logical filter will be explained below with reference to the drawings.

For example, in the signal fC1> shown in FIG. 4, the sample value f(i) and its neighboring value f(i-1)t f(i+t)
Pattern I) (i) is constructed by the values of the three points.

Similarly, sample value f(i+1) and its neighboring value f(i)*
Pattern I)(i+x) is constructed from f(i+2). The signal f(t) can be regarded as a set of patterns p(t) obtained as follows.

Also, three sample values e.g. f(i-1), f(i)
The pattern p(i) composed of =f(i+1) is the fifth
As shown in Figure 5, by taking the center value f(i) on the B axis and the two neighboring values f(i-1) and f(i+1) on the A and C axes, we can obtain a point in the three-dimensional space. It can be expressed as Therefore, all patterns p(
t) is expressed as a distribution of points in a three-dimensional space, as shown in FIG. 5B. Note that the solid line frame in the figure indicates the range of the maximum value of the six values.

In FIG. 5B, the pattern p(t
) is the three values that change in a stepwise manner as shown in a in the figure, and the pattern p ( on the A axis opposite to the A axis)
t) is a stepwise transition of three values as shown by b+c. In addition, the pattern p(t) on the B axis is one in which three values change in a pulse-like manner as shown in C, and the B
The pattern p (t) on the B axis, which is opposite to the axis, is a pattern in which three values change in a pulsed manner as shown in d. Also C
The pattern p(t) on the axis has three values as shown in e5&C
The pattern p (t) on the C-axis opposite to the C-axis changes in a step-like manner so that the three values indicate fK. The pattern p(t) on the axis connecting the Sarashu origin 0 and the opposing vertex O of the frame is one in which the three values change linearly as shown in g, and the pattern po between these ) are transitions to intermediate shapes.

The space that represents such a pattern is called a pattern space, and in a logical filter, on the above pattern space,
By converting a pattern set in a specific area into another pattern set, a filtering function is obtained.

For example, in an image signal, since the correlation between neighboring pixels is very strong, most of the pattern is
It can be assumed that the pattern area is distributed in a straight line or in a step shape as shown by the I+ line. The pattern in this diagonal area, which includes step-like simple turns, is also an important area for visual overlay.

In contrast, noise is equally distributed over the entire area.

Therefore, K, which removes noise from an image signal containing noise, converts the pulse-like pattern in the area other than the diagonal line in Figure 6 on the pattern space into a straight line or step-like pattern as shown in Figure 6B. All you have to do is suppress it. The idea of a logical filter is to remove and suppress noise without deteriorating the step waveform of an image signal by performing such filtering.

By the way, in the same way that there are two ways of thinking, positive logic and negative logic, in so-called digital logic (on-off logic), it is necessary to think of two logics, positive and negative, in pattern space logic as well.

For example, in Figure 7, A and B have the same waveform. However, A looks like two step-like patterns, while B looks like a pulse-like pattern. The same difference as between A and 8 occurs for D. Therefore, in the following explanation, these will be defined as 5 as follows.

In other words, the view of Figure 7 A and C based on the low level is called positive logic, and the view of Figure 7 B%D based on the high level is called positive logic.
This way of thinking is called negative logic.

Therefore, the pattern on the C-0 axis in Fig. 5 is C-0 in Fig. 7.
, D, and can be said to be a pulse pattern with positive logic.

The pattern on the Co axis is a negative logic pulse pattern.

In order to suppress noise here, both of these pulse patterns must be suppressed. Let me explain with reference to the drawings.

First, the above f(i) and its neighboring pixel f(i-t)-
Let f(i+t) be the pattern p(i)・P(i) ”(f(i-i) gf(i)-f(i+t)
) ...°・(1) This pattern P(i)
The set ■ whose elements are P = (P(i) IP(i)
= (f(i-1)s f(i)p f(i+i)
) pi=1, 2, 3,...)...(
2), and K that suppresses the positive pulse pattern is the fifth
As shown in the figure, the set P is defined as a positive subset G that does not contain the positive Nohalus pattern by the function Q:P-+G; (GCIP)
It would be better to convert it to '.

Then, the ordered pair of pattern G(i) of the transformed subset G is G(i)=(a, b, C) −
------ (3) ajbtc: post-implementation tBjCM, then the function q: 1p-4G is expressed by the following equation.

However, MAX indicates that the maximum value within the parentheses below is extracted, and MIN indicates that the minimum value is extracted.

Therefore,'(i)=(f(i-t), nuICMIN(f(i-t
)−f(i)), MIN(f(i), f(i+t):
+1))...(5) The B-axis value of the pattern G(i) converted in this way is converted into a new video signal f(i) that has been filtered.
It's fine if you do this.

f(i')=厘(MIN(f(i-i),f(i)),
MIN(f(i)gf(i+t)))=Xx...(
6) (See Figure 8) Similarly, let the function that suppresses the pulse pattern in negative logic be r, and the converted pattern H(i)*H(i)=(
asb*c) and the set of putter yH(i) as an element becomes ■, then the function r:P→H becomes, and then [H(Todoroki)"(f(i-1), MINCMAyC(f(i
-sat f(1))#N[IN(f(i)sf(1)
+1)))of(1...(8)).

Further, the output f(i) is expressed by the following formula.

f(i) = MIN(MAX(f(i-1), f(i)
), MAX(f(i)-f(i+1))"l=Xg ・
(9) (See FIG. 9) A logical filter is one that obtains desired filter characteristics by a combination k of such logical processing.

Therefore, if input signals are supplied to the positive logic processing system and the negative logic processing system, the positive logic processing system will suppress noise in the positive direction, and the negative logic processing system will suppress noise in the negative direction. If we add the values to / and then perform a belldown, the noise will be suppressed by 6 dB IC in both directions.

5 in FIG. 10 when constructing a logical filter circuit using input signals from three sampling points adjacent to each other.

In Fig. 10, does the signal from input terminal (1) correspond to the time difference (sampling interval) of the reliability calculation? The signals from this input terminal (1) and the delay circuits (2), (
3), the signal at the output end is supplied to a positive logic operation circuit (5P) and a negative logic operation circuit (5M).

The positive logic operation circuit (5P) is composed of minimum value (MIN) logic operation means +6), (71) and maximum value (MAX) logic operation means (8), and MIN means (6) and (7).
Two points adjacent to each other (f(i-1)tf(i))e
The MIN at cf(i)gf(1+1):l is determined, the MAX of these MIN is determined by the MAX means (8), and the calculation of equation (6) is executed.

The negative logic operation circuit (5M) has a pair of MAX means αυ, az
and MIN means 0, and the logical operation of equation (9) is executed.

Each output X1 of positive and negative logic operation circuit (5P), (5M)
.degree. Therefore, an output signal in which the positive and negative pulses are each suppressed to 8 is obtained at the output terminal αη.

In this way, for three amplitudes: the amplitude f(i) of an arbitrary pixel and the amplitude f(i-1)tf(i+t) of two neighboring pixels, Xa 鵠(i)→MAX(MIN(f( i-t
)-f(i)), MIN(f(i)gf(i+t)))
・+(61Xs = (h(t) → MINCMAX(f
(i-t)tf(i disease MAX(f(i)#f(i+t)
)) ”(91Xo=(fo(t)→ω(t)+h(i
))/z -.-5uI on the entire screen, it is possible to obtain a video signal with suppressed noise without deteriorating the frequency band of the luminance signal.

By the way, when digitizing the logical filter circuit ao shown in FIG.
All means must be constructed of a digital comparator and a selector for selecting one of the digital inputs according to the output of the comparator, and must be constructed as shown in FIG.

In FIG. 11, the symbol ``■'' indicates a digital comparator, and the so-called selector.

Therefore, when performing digital signal processing, there is a disadvantage that the number of digital comparators increases and the circuit scale increases. If the number of sample points is increased to three or more, the number of digital comparators will further increase, and the circuit scale will further increase.

OBJECT OF THE INVENTION Therefore, the present invention makes it possible to significantly reduce the number of digital comparators even when a logical filter circuit is configured digitally.

Summary of the Invention In this invention, when a digital input signal is converted into digital input signals of N mutually adjacent reference points and logical calculation processing is performed, it is possible to classify them into 81 signals according to their amplitude relationships. When calculating the positive and negative logic operation outputs XI * X2 from the magnitude relationship of the amplitudes of
1) It focuses on the fact that it can be uniquely determined by a combination of 72 digital comparators and a simple p-thick circuit.

Therefore, in the logical filter circuit according to the present invention,
A group of N digital input signals is supplied to the first and second switching means, and is also supplied to N (N-1) 72 digital comparators commonly used for positive logic operations and negative logic operations. , the comparator outputs obtained from these are supplied to a positive logic operation logic circuit and a negative logic operation logic circuit, and the first and second switching means are controlled by the first and second switching pulses obtained from each. By doing so, the first switching means obtains a first digital output signal in which a pulse signal of positive polarity is suppressed, and the second switching means obtains a second digital output signal in which a pulse signal of negative polarity is suppressed. obtained,
These are combined to obtain an output signal in which positive and negative pulses are suppressed.

Embodiment Next, an example of the logical filter circuit according to the present invention will be explained in detail with reference to FIGS. 1 to 3. However, as mentioned above, KN=3 Let me explain using an example.

When the sample value N is 3, the amplitude relationship obtained by the combination k of these 3 sy7'' points, that is, the pattern set P, is #!2 as shown in figure 5 K IP, to 6 from P6.
1 [All of them can be expressed by patterns of class (3!=6). Then, by performing a positive logic operation (its output is Xi) and a negative logic operation (its output is X2) for each of these pattern sets P, pattern sets P1 to IP6 are obtained.
The relationship between the outputs X1 and X2 is as shown in FIG.

Furthermore, two specific sample points among the sample points constituting the pattern set, namely (f(1-t) and f(i)
] * Cf(i) and f(1-1)] and [f(i-t
) and r(4+t)) as each pattern set I
When P1 to P6 are compared, an output relationship as shown in FIG. 3 is obtained. Here k, "1" indicates that the comparison output is large, and "0" indicates that it is small.

Comparing and considering these amplitude relationships and the relationship between the logical operation outputs X1 and X2, it is found that among the positive logical operation outputs X1, f(i
-1) can be obtained by simply looking at the magnitude relationship between the amplitudes of I and summer (dashed line area), and for f(i+1), the output of 7 can be obtained just by looking at the magnitude relationship between the amplitudes of summer and ■ (dashed line area). is obtained,
The remaining output f(i) can be easily obtained by calculating from f(i-1) and f(i+1).

Similarly, the negative logic calculation output X2 can be easily obtained by calculation from the amplitude relationship in the solid line area in FIG.

Therefore, to obtain the positive and negative logic operation outputs Xl, It can be realized using a device and a simple logic circuit. In other words, the circuit scale can be significantly reduced compared to the case where logical operations according to equations (6) or (9) are performed.

FIG. 1 shows an example of a main part of a logic filter circuit (1) that is embodied based on this idea.

In the figure, the delayed signals and current signals of delay circuits (2) and (3) are supplied to a power supply (151Vc) through corresponding switching elements (2) to
).

The delayed signals and current signals in (3) are supplied to the adder α51 via corresponding switching elements (to) to (4), respectively.

Then, each delayed signal of the delay circuit (21, (31) is supplied to the first digital comparator (to), and the current signal and the delayed signal of the delay circuit (3) are supplied to the second digital comparator (0).
The current signal and the delayed signal of the delay circuit (2) are supplied to the third digital comparator (2).

The first to third comparator outputs are supplied to two first and second logic circuits, and the output of the first logic circuit (2) controls the switching of the first switching element group (c). , and the switching of the second switching element group is controlled by the output of the second logic circuit (to). Therefore, the digital comparator group (2), the first logic circuit (3), and the first switching element group (3) are used as positive logic operation means (3).
5P) is configured, and the digital comparator group, the second logic circuit (to), and the second switching element group (5) constitute a negative logic operation means (5M), and the digital comparator group is commonly used. be done.

The first logic circuit (goods) is a pair of AND circuits (40, (4
1) and a NOR circuit (6), the second comparator output and the third comparator output via the inverter are supplied to the AND circuit, and the AND output A1 controls the switching element (to). . Further, the output of the third comparator 7- and the output of the second comparator via the inverter are supplied to the AND circuit Oυ, and the AND output A2 controls the switching element (21+). tA2 is supplied to the NOR circuit (4), and its NOR output N1 turns on the switching element.

Therefore, for example, in the case of pattern set P2, the outputs of the first to third digital comparators are "0".

Since rlJ j rOJ, only the AND output Al is “
1'', only the switching element - is turned on, and only the delayed signal of the delay circuit (3) is output.

In the case of pattern set IP3, the first to third comparator outputs are rOJ # rOJ # rlJ, so only AND output A2 becomes "1", only switching element (2) is turned on, and only the current signal is output. If it happens, I'll be disappointed.

In other cases, AND outputs A, , A2 are all "0", so in this case only NOR output N1 is "1".
''K, the switching element Q11 is turned on and the delayed signal of the delay circuit c111 is selectively output. The outputs of these switching element groups (to) are positive logic operation outputs X1 for each pattern set P.

The logic circuit in building 2 (to) is also composed of a pair of AND circuits -26υ and six NOR circuits, making it a pair of AND circuits (to).

61 has the same signal relationship as in the first logic circuit r34 [first to third combiner 9] are supplied, but as is clear from FIG. 3, the logical values are reversed, so
A pair of AND circuits with corresponding polarity −26υ
The first to third comparator outputs are supplied to the first to third comparator outputs. Therefore, the AND circuit is supplied with the first comparator output and its phase inverted by the inverter, and the other AND circuit is also supplied with the second comparator output and its phase inverted by the inverter. What is provided is supplied.

Then, the AND output causes the switching element (goods), the AND output Ab causes the switching element (c), and the NOR output N
The switching elements (2) are respectively controlled by a.

It is clear that by configuring the second logic circuit (to) in this manner, negative logic operation outputs X2 as shown in Figure 3 of C-connection 3 can be obtained corresponding to each pattern set IP.

In the above, the case where N=3 has been explained in each case, but in the case where N=5, for example, the positive logic operation is as follows, and it is sufficient to use 10 digital converters.

As described in detail, according to the present invention, the positive logic operation means and the negative logic operation processing means can share the digital comparator, and even when 4IKN sample values are used, the position ← It only takes one night to digitally compile σ pieces,
The circuit scale can be reduced accordingly. Therefore, according to the present invention, it is possible to significantly reduce the cost of the logical filter circuit. Therefore, the present invention is extremely suitable for removal of noise contained in a luminance signal and for application to a logical filter circuit such as a Y/C separator.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an example of a logical filter circuit according to the present invention, FIG. 2 is an explanatory diagram of a pattern set for explaining the operation of the present invention, FIG. 3 is a diagram for explaining the present invention, and FIG. 〜FIG. 9 is a diagram for explaining the present invention, FIG. 1
0 and 11 are system diagrams of logical filter circuits used to explain the present invention. (5P) is a positive logic operation means, (5M) is a negative logic operation means, (to) is a digital comparator group, (c), @ is a switching element group, (goods), (c) are the first and second It is a logic circuit. Figure 5 r

Claims (1)

[Claims] A digital input signal is converted into digital input signals of N reference points adjacent to each other, and these N digital input signal groups are supplied to first and second switching means, and a positive logic operation and a negative logic operation are performed. N commonly used in
(N-1)/2 digital comparators,
The comparator outputs obtained from these are supplied to a positive logic operation logic circuit and a negative logic operation logic circuit, and the first and second switching means are controlled by the first and second switching pulses obtained from each. A first digital output signal in which a positive polarity pulse signal is suppressed is obtained from the first switching means, and a second digital output signal in which a negative polarity pulse signal is suppressed is obtained from the second switching means. are obtained, and these are combined to obtain an output signal in which positive and negative pulses are suppressed.