JPS6135337A - Pattern inspecting method - Google Patents

Abstract

PURPOSE:To perform pattern design inspection speedily and properly by converting design data on an IC into a binary picture signal and converting the duty factor of the picture signal into an analog picture signal. CONSTITUTION:The range of 100 by 100mum of the chip of an IC is regarded as one screen and pattern design data is read out of a magnetic tape. Then, a picture signal converter decides a picture element area of, for example, 0.1 by 0.1mum to display picture elements 31 in a pattern as ''1'' and picture elements 31 outside the pattern as ''0'' and perform conversion into a binary picture signal as shown in a figure (b). Then, the duty factor of the picture signal is set substantially to ''1'' as shown in a figure (c) to perform conversion into an analog picture. Then, plural analog picture signals are superposed. Therefore, the analog signals are collated mutually, so the collation inspection of the pattern shape and design reference value of the IC becomes possible and the inspection of the IC is performed speedily.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a pattern inspection method capable of extremely quickly inspecting the suitability of pattern design of electrical solid-state devices such as semiconductor integrated circuit devices with sufficient accuracy. Regarding.

[Technology background]

Microelectronics has become the basis of modern industrial progress and has a great impact on social life. The main character of microelectronics is a semiconductor integrated circuit device (hereinafter abbreviated as IC), and efforts are being made to increase its degree of integration and improve its characteristics, and its application fields are rapidly expanding.

The issue of how to integrate the circuitry of a system into ICs determines the most basic aspects of the performance and price of the system's hardware, and as a feedback, it also has a large impact on the specifications of the entire system. This has long been an important concern in system design. Recently, as system requirements have become more sophisticated, customization of ICs has become commonplace, and in order to cope with this, it has become increasingly important to reduce the time and cost required for development from design to practical application. It has become.

[Conventional technology and problems]

When designing an IC, design target values are set based on the electrical functions required by the user, input/output bias conditions, operating environment conditions, required reliability, transaction conditions, etc., and the design standards are followed. The design is performed according to the design target values and manufacturing process.

Design standards are set to standardize the basic functions, reliability, and external shape of semiconductor devices. stipulate.

Patterning plays a major role in IC design. The pattern design data for each layer is, for example, as shown in FIG.
Coordinates of the vertex as a reference regarding the axis (Xr, Yl)
The length of one side is X,,Y,) and the angle θ that side X1 makes with the X axis
The ratio of 180° to 180° is approximately 1-.Numerator and denominator [For example, when 30°/180°-1/6 (1,6J) is combined, XI, Yl, XI, Yl, (1,6) It is digitally displayed and recorded, for example, on magnetic tape.

To manufacture a reticle mask or the like according to this design data, an electron beam exposure device or other pattern generating device is used, for example. ICs designed using this mask are prototyped and evaluated, but as a result the design often needs to be improved.

Designed patterns are often examined by enlarging the fabricated reticle mask onto a film and superimposing it on other layers or on the butter before the design change. However, this method can be implemented only after the reticle mask has been manufactured, and a long waiting time is required to judge or confirm the quality of the design data.

In order to improve this current situation, a method of comparing and examining digital design data as exemplified above has already been attempted. In this method, for example, digital displays before and after a design change are sequentially compared in the order in which they were recorded, and only data that differs between them is extracted. It is also possible to add the outside of this extracted data part to the video signal, but for example, the data of the unchanged pattern adjacent to the changed pattern is extracted and the relative arrangement of both patterns after the role change is designed. It is impossible to consider whether or not it violates the standards.

In addition, it is possible to consider the minimum line width in principle, but
The number of steps involved is extremely large, making it difficult to put this into practical use.

Furthermore, for example, when contact holes are formed in the edge layer for the impurity-introduced region and the electrode that contacts it, matching the pattern position between the previous and subsequent processes is more difficult than considering the minimum line width. .

This is not limited to overlapping ICs due to expansion of IC integration scale or customization, but is equally important to other solid-state devices such as magnetic bubble devices, piezoelectric, electrostrictive devices, and membrane integrated circuit devices, although there are differences in degree. .

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to address the above-mentioned problems and provide a pattern inspection method that can quickly and accurately inspect the design of patterns of electrical solid-state devices.

[Structure of the invention]

The objects of the present invention are as follows: 1. A plurality of design data of patterns of electrical solid-state devices;
After converting into a value image signal, converting the image signal into an analog image signal with a duty factor of substantially 1,
A pattern inspection method according to the present invention, in which a plurality of analog image signals are superimposed and the plurality of analog image signals are compared with each other.

and 2. After converting the single or multiple design data of the pattern of the electrical solid state device into a binary image signal, converting the image signal into an analog image signal with a duty factor of substantially 1, and converting the image signal into an analog image signal. A pattern inspection method according to the present invention, which compares one analog image signal or a plurality of superimposed analog image signals with design reference data.

This is achieved by

That is, according to the present invention, a necessary and sufficiently fine pixel area 31 is assumed as shown in FIG. The design data is displayed in 1 bit of 10'' and converted into a binary image signal that scans the pixel area 31 (bl
The signal processing speed is increased by converting the image signal into an analog signal by setting the duty factor of the image signal to substantially 1 as shown in the figure (C1).

By superimposing and displaying a plurality of image signals converted in this way and comparing the sum of the image signals, you can, for example, compare and confirm patterns before and after a design change, or use a single image signal converted in this way. By comparing the image signal or the image signal of multiple superimposed processes one after another with the design standard data, it is easy to determine whether the design pattern passes or fails the design standard, etc., at high speed. I can do it.

[Embodiments of the invention]

The present invention will be specifically explained below using examples.

FIG. 3 is a block diagram showing an example of a pattern design inspection apparatus according to the present invention. This apparatus is roughly divided into two parts, the first of which is an image signal converter l that converts digital design data recorded on, for example, a magnetic tape into an image signal, and a plurality of equivalent parts are provided. The second part is a central processing unit 2 that includes a comparator for comparing converted image signals, a monitor, and a printing device. In the image signal converting unit 1 shown in FIG. 2, 11 is a magnetic tape device, 12 is a RAM that temporarily stores data on magnetic tape
, 13 is an image signal converter that converts the design data into an image signal, and 14 is a RAM that temporarily stores the converted image signal.
, 15 is an image signal sending circuit, and 16 is a control device for controlling the above image signal conversion section.

Further, in the central processing unit 2, 21 is an image signal comparator;
22 is a coordinate axis matching circuit, 23 is an input/output interface, 24 is an RJtM that stores extracted data, etc., 25
is a ROM, 26 is an MPU that controls the system, 27A,
, 27B is a monitor for each image signal, 27C is a monitor for the image signal of a signal comparator, 28 is a printing device, and 29 is a control panel.

In this example, the chip is, for example, 100 μm×10
The pattern design data displayed as in the above example is read out from the magnetic tape, with the range of 0 μ trout as one screen, and the image signal converter 13 converts the pixel area into, for example, 01 μ bait x 01 μw IJ pixels within the rainbow pattern. 1″, 1″
, 0# outside the pattern is excluded and converted into a binary image signal to be displayed with 1 bit. If this binary image signal is sent out with a data factor of 100, analog image processing means can be used.

For example, when confirming the changes after making a design change, input the design data before the change, schematically shown in FIG. The changed design data shown in is input to the other image signal converter 1.The two signals converted as described above are compared by the image signal comparator 21, and the desired pattern portion is displayed on the monitor 27C. In this case, the display shown in Figure 4(C) can be observed, and the coordinates of these different parts are RA.
Recorded in M24.

This device also performs a check to compare the relative arrangement of design patterns of different layers, such as a mask pattern defining an impurity introduction region and a contact hole pattern of an insulating film provided above, with design reference values. be able to. Note that the design reference value can be recorded, for example, at the beginning of a magnetic tape on which design data is recorded and input into the system.

FIG. 5 (al) shows an example in which a design pattern of a field effect Y transistor element is inspected using three image signal converters l; gate electrode pattern A1; ion implantation mask pattern B for source and drain regions; A contact hole pattern C of the drain electrode is created manually, and these are superimposed using analog image processing means to form a pattern D.
get. In this embodiment, the image signals of the area where the patterns are superimposed are "0#,""05" as shown in FIG.
By comparing the width of each portion of this image signal with the design standard, compliance with the design standard can be inspected, and positional deviation between layers can be detected.

In this method, the resolution is, for example, 01μ as in the above embodiment.
It is possible to detect the bladder in units of 0.1 μl, with 0.1 μl as 1 bit, and further miniaturization is possible if necessary, allowing inspection to be performed with sufficient accuracy.

Also, using the apparatus of the above embodiment, for example, about 10 mm
It is possible to carry out pattern design inspection of a large-scale integrated circuit device having an area of I Omm in about 20 minutes,
If we were to implement the above-mentioned inspection method that directly handles digital design data, it would take approximately 6 to 8 hours, depending on the pattern density (compared to this, its effectiveness is extremely large). .

〔Effect of the invention〕

As explained above, according to the present invention, when designing a pattern for an electrical solid-state device, analog image processing of a binary image signal is used to quickly and accurately compare the pattern shape and the design reference value of the designed pattern. This makes it possible to carry out inspections such as cross-checking, and has the effect of significantly reducing the development period and cost of large-scale semiconductor integrated circuit devices, which are rapidly expanding in scale and number of types.

[Brief Description of the Drawings] Fig. 1 is an explanatory diagram of pattern design data, Fig. 2 is a diagram showing image signal formation of the present invention, Fig. 3 is a block diagram showing an embodiment of the present invention, Fig. 4 and FIG. 5(a) is a schematic diagram of the pattern display of this embodiment, and FIG. Central processing unit, 1
1 is a magnetic tape device, 12.14 and 24 are RJM, l
3 is an image signal converter, 15 is an image signal sending circuit, 16
21 is an image signal comparator; 22 is a control device for a signal converter;
is a matching circuit, 23 is an input/output interface, 25 is R
OM, 26 is MPU. 27A, 27B and 27C are monitors, 28 is a printing device,
29 is a control panel, and 31 is a pixel area. (b) Base 5 Figure (oL)

Claims (1)

[Claims] 1. A plurality of design data of patterns of an electrical solid state device 2.
After converting into a value image signal, converting the image signal into an analog image signal with a duty factor of substantially 1,
A pattern inspection method characterized by superimposing a plurality of analog image signals and comparing the plurality of analog image signals with each other. 2. After converting single or multiple design data of a pattern of an electrical solid-state device into a binary image signal, converting the image signal into an analog image signal with a duty factor of substantially 1, and converting it into a single image signal. A pattern inspection method characterized by comparing an analog image signal or a plurality of superimposed analog image signals with design reference data.