JPS613394A - C-mis sensor amplifier - Google Patents

Abstract

PURPOSE:To precharge digit lines quickly immediately before reading and to obtain stable actions irrespective of the fluctuation of a digit line voltage by providing two MISTrs for connecting a pair of digit lines to the 1st and 2nd terminals connected to two power sources through an MIS transistor Tr. CONSTITUTION:Before a memory cells is read out, a clock signal phi3 and an inversion phi3 are at a high level and a low level, respectively. Digit lines D1 and D2 are precharged at the same potential together with a terminal N3 through n-MOS transistors TrsQ7 and Q8. Simultaneously a terminal N4 is also precharged at the same potential (VDD/2) through p-MOS TrsQ9 and Q10. Then, the phi3 and the inversion phi3 go to a low level and a high level, respectively, and the TrsQ7-Q10 become nonconductive, which causes the memory cell to be read. Consequently the digit line is quickly precharged prior to reading, and acts stably irrespective of the fluctuation of the digit line voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sense amplifier used in an integrated memory, particularly a C-MIS integrated memory.

[Prior art]

1-transistor random access memory (hereinafter referred to as RA)
(referred to as M), the large charge accumulated in the storage capacity of the memory cell is transmitted to the digit line via a switching transistor, which is a selection gate, and the signal is amplified by a highly sensitive sense amplifier and sent as an output signal. A method is adopted in which the amplified signal is rewritten into the memory cell at the same time as the signal is output.

Conventionally, n-MOS has been used as a sense amplifier for integrated RAM.
A device consisting only of transistors was used, but recently an integrated R using a C-MOfS sense amplifier has been developed to simplify the circuit and provide a large operating margin.
AM is attracting attention. As a conventional example of a C-MO8 sense amplifier, for example, the I.
International Solid Stained Circuits Conference (1984 IEE)
E INTER-NATIONAL 5OLID-5
TATE CIRCUITS CONFERENCE)
Stock of Technical Papers (l5
SCCDIGEST OF TEC) INICAL P
APER8) pages 278-279 (distributed simultaneously at the February 1984 conference)
Sub 100ns 256K DRAM in
0MO8 [I Tg-chnology') J, which was introduced in a paper by Mr. Kusg et al.

The structure of the fcC-MO3 sense amplifier introduced in the above paper is shown in FIG. That is, the sense amplifier A (shown surrounded by a broken line in the figure) is composed of n-MOS transistors Q and Qt.
and p-MOS transistors Q and Q4, and the output points N and N of the flip-flop circuit are connected to the digit lines D8 and D2 of the memory circuit, respectively. Both have the same load capacity.

When one memory cell 5 of the memory cells connected to the digit line D1 is read out, the memory cell 6 connected to the other digit line D2 is not read out, and in step 9, the memory cell information 11 is transferred from the dummy cell 8. ' and 1
A reference potential intermediate between 0'' and 0'' is supplied to the digit training. Conversely, when the memory cell 6 is read out, the transistor Qy', to which the reference potential is supplied from the dummy self to the digit line, pre-primes both digit lines to the same potential before the information in the memory cell is read out to the digit line. It is for charging.

FIG. 4 shows operating waveforms of the conventional circuit shown in FIG. 3.

The operation of the conventional circuit shown in FIG. 3 will be explained below using the waveforms shown in the same figure.

The digits #D□ and #D are precharged to the same potential through the entire transistor QS by time t8. After clock signal G1 falls from high level □ to low level at time t, for example, if address line 9 is selected by the address signal at time t, then when address line 9 becomes high level, the memory cell 5 information is digit line D1
is read out. On the other hand, the digit line is given a potential intermediate between the cell information 'I'' and 1ON by the dummy cell 8. As a result, a potential difference of about 0.1 V is generated between the digit line D1 and the digit line D1 before time t. At time t, the clock signal G is set to high level, and the n-MOS
When the transistor q is made conductive to activate the sense amplifier A, due to the positive feedback effect of the transistors Q1 and Q, the one with the lower potential among the digit lines D1 and D1 quickly falls below the threshold voltage vth of the transistor. At the 0th order, which suppresses the potential drop of the digit line on the high level side, time t
When the clock signal G is lowered from a high level to a low level at step 4 and the p-MOB register Q6 is made conductive, the digit line on the high level side is lifted by the power supply voltage VDDi, and the potential difference between the two digit lines is become maximum. During this time, the signal on the digit line is transmitted to the outside, and is rewritten into the memory cell, completing reading from the memory cell.

[Problems with conventional technology]

By the way, in the conventional C-MO8G amplifier as shown in FIG. 3, before reading memory cell information, the transistor Qt' is made conductive and the pair of digit lines and D2 are connected.
A method is used in which the two are precharged to the same potential. For example, assuming that the voltages on digit line D1 and D1 before transistor Q7 conducts are Ov and 5V, the digit line voltage after the channel is approximately 2.5V. At this time, the voltage at terminal N, the threshold voltage of transistor Q, is VtA (
Ql)/In this case, there will be a Q-constant voltage between 2.5V-Vth(Qx) and 2.5v. Also, the voltage of terminal N4 is a constant voltage between 2.5 V (VthCQa) and 2.5V (VthCQ<) is the voltage of transistor Q4.
threshold voltage). In the worst case, the voltage across terminals N and N4 will be 2.5 V VtA (Qt), and the voltage across terminal N4 will be 2-5 V VtA (Q4), and even small fluctuations in the digit line voltage will cause the transistor Qs + Q
The flip-flop circuit consisting of t r Qs +Q4 is in a state where it starts an amplification operation. In other words, when reading memory cell information, if there is a slight difference in the read time between the memory cell and the dummy cell, there is a risk that the one read first will be amplified faster and malfunction. There is also a drawback that malfunction occurs due to fluctuations in the digit line voltage of fc.Furthermore, during precharging, terminal N is charged through transistors Qt' and Q, while terminal N4 is charged through transistors off,' and Qat.
Therefore, it took a long time for the terminals N, N4 to reach a stable potential, and accordingly, it took a long time for the digit line voltage to become stable.

[Purpose of the invention]

An object of the present invention is to quickly precharge the paired digit lines to the same potential when precharging the digit lines immediately before reading memory cell information, and at the same time, to operate stably regardless of fluctuations in the digit line voltage. C-MIS sensing and sensing amplification are provided.

[Structure of the invention]

The C-MIS sense amplifier of the present invention includes a first C-MIS sense amplifier coupled to first and second power supplies respectively via MIS transistors.
and a second terminal, a first p-MIs transistor having a source coupled to the first terminal, a drain to the first digit line, and a gate to the second digit line; a second p-MIS transistor having a drain coupled to the second digit line and a gate coupled to the first digit line; a source coupled to the second terminal and a drain coupled to the first digit line; a first n-MIS transistor having a source coupled to the second terminal, a drain coupled to the second digit line, and a gate coupled to the first digit line; a second p-MIS each coupled to a digit line; a C-MIS having a transistor;
In the sense amplifier, first and second M digit lines are coupled to the first terminal and the first and second digit lines, respectively.
an IS transistor, and third and fourth MIS transistors that couple the second terminal and the first and second digit lines, respectively.
IS sense amplifier.

[Operation/principle of the present invention]

The C-MIS sense amplifier according to the present invention cross-couples the paired digit lines and the common source of the fcp-MIS transistor and the n-MIS transistor before reading memory cell information.
This is very advantageous for large-capacity memories because the common sources of the S transistors can be quickly brought to the same potential, and at the same time, it is resistant to variations in the threshold voltage of cross-coupled MIS transistors and voltage fluctuations in the digit line.

〔Example〕

EXAMPLES Hereinafter, in order to better understand the present invention, the present invention will be explained using examples.

(Example 1) FIG. 1 shows a first example of the present invention. The n-M)S transistors F1 and Q have their drains and gates cross-coupled to each other and connected to terminals N1 and N8, respectively, and their sources connected to terminal N3. p-M
OS transistors Qs and Q4 have their drains and gates cross-coupled to terminal N2 and N, respectively, and their sources to terminal N. The n-MOS transistor Q has its drain connected to the terminal N, its gate connected to the first clock line 961, and its source connected to the zero potential power supply GND, and the p-MOS transistor Q6 has its drain connected to the terminal N, The gate is connected to the second clock line, and the source is connected to the high potential power supply VDD.
are connected to each. n, -MOS) Rungis p
Q, and Q, and p-MOS transistor Q=,Q4
constitutes a flip-flop circuit as described above, and the present invention provides, in addition to the first and second nine-MOS transistors and the first and second p-MOS transistors constituting the above-mentioned flip-flop circuit. first and 217th) MOS transistors that respectively couple the terminal N4 and the digit lines DI and D; and third and fourth MOS transistors that couple the terminal N and the digit lines D1 and D2, respectively. This is provided in place of the transistor Q7 shown in FIG. In the embodiment, n-MO8 transistors Qt and Q are used as the first to fourth transistors.
Although a combination of s and p-MO8 transistors Qo + Q+o is used, the example is not necessarily limited to this example.

Specifically, the n-MO8 transistors Q7 and Q are:
Its drain is connected to the terminals N and N, its gate is connected to the third clock line yi3, and its source is connected to the terminal N, respectively.
L, p-MO8) Lang Ruri Q, and Ql. connects its drain to terminals N1 and N, its gate to the fourth clock line, and its source to terminal N4.

Transistors Q1 to Qso surrounded by broken lines constitute the C-MO8 sense amplifier A of the present invention. In the circuit diagram of FIG. 1, the circuit elements other than the sense amplifier A described above are the same as those of the conventional example shown in FIG.

Identical components are given the same numbers and their explanations will be omitted.

The circuit operation of this example is as follows: h l Q@
rQe, Qt. is the conventional transistor Q in Fig. 3.
This is the same as the conventional example except that it has the same function as t'.

The circuit operation of this embodiment will be explained using the operation waveforms shown in FIG. Here, it will be explained as an inverted signal of the clock signal 〆, beam/lock signal 〆. By time t1, before reading of memory cell information begins, clock signal 〆, is at high level, y3 is at low level, digit line, and D2 are connected to terminals through n-MOB transistors Q and Q. P-MO8 transistors Q and Ql are simultaneously precharged to the same potential with N, and p-MO8 transistors Q and Ql. Through this, terminal N4 is also precharged to the same potential. The precharge voltage is approximately VDD/2. At time t8, clock signal G falls from high level to low level and clock signal N rises from low level to high level, causing transistors Q71 Qll QsoQ,. becomes non-conducting. Thereafter, at time t2, the address line 9 or IO becomes high level, and reading of memory cell information begins.

The C-MO8 sense amplifier of this embodiment connects terminals Ns, N and digit lines D□,
D, is precharged to an equal potential. Therefore, when reading a memory cell, even if the address line 9 or IO is set to high level and the cell information is read to the digit line, the voltage fluctuation of the digit line is small, so the transistors Q, , Q + Qs * Q4 are conductive. Instead, the clock ms is raised to a high level, and the voltage at the terminal N is lower than the voltage at the digit line of the transistor Q1 or Q.

When the voltage is lowered below the threshold voltage, the transistor Ql or Q starts conducting, and the amplification operation begins. Therefore, when reading memory cell information, it is possible to prevent malfunctions caused by a slight difference in read time between the memory cell and the dummy cell. Also, 5-MO8) 5-diodes fi Qy and Qs pMOS transistors Q and Ql for precharging. Since the four signals used to drive the digit lines , , and 4 are in opposite phase to each other, the capacitive coupling to the digit lines, , and D, caused by the level switching of the S, , S, signals at the end of precharging cancels each other out, and the digit lines This also has the advantage of increasing the operating margin because voltage fluctuations in the voltage are alleviated. Furthermore, digit line D1. D, is precharged by n-MOS transistors Q, , Q, and p-MOS transistors.
5 transistors Q-, Qs.

The precharging time can also be shortened because the precharging is performed from two directions, and the upper i transistor operates in the triode region just before the end of the precharging.

(Embodiment 2) FIG. 2 shows a second embodiment of the present invention. The embodiment shown in FIG. 2 is an example in which the C-MO8 sense amplifier of the present invention is applied to a folded digit line type one-transistor type RAM. The circuit symbols described in the embodiment of FIG. 2 are all the same as those of the embodiment of FIG.
The circuit layout of the 'ss amplifier is p-MO8 transistor part Q3 * Qa * Qa + Qta and n-MO8
Transistor part Q8. Q2. Q7. Qs is divided, and furthermore, p-MO8 transistor Q6 for charging and n for discharging.
- MO8 transistor Q, etc., which are commonly coupled to a number of sense amplifiers. The circuit operation of this embodiment is the same as that of the first embodiment, except that the p-MO8 transistor section and the n-MO
Since the eight transistor sections are arranged separately, the layout is easy and there is an advantage that the increase in area peculiar to a C-MOS circuit can be prevented. Other advantages of using this sense amplifier, such as increased operating margin, are:
This is the same as the first embodiment.

The present invention is not limited in any way to the embodiments shown in FIGS.
It extends to all integrated circuits in which S-sense amplifiers are used. In the embodiments shown in FIGS. 3 and 4, the inverted signal of the clock signal G was used as the input signal to the gate of the p-MO8 transistor Q* + Qio, but this input signal does not contain memory cell information. It is sufficient that the clock signal makes the p-MO8 transistor Q*4QIO conductive only before the reading start time t, and there is no need for it to be an inverted signal of the clock signal.

I have explained the trillion transistors above, but the general KM
Needless to say, it can be applied to IS) U/JISTA.

〔Effect of the invention〕

As described above, according to the present invention, a sense amplifier with a wider operating margin than conventional examples can be obtained, which is free from malfunctions when reading memory cell information and whose operation is stable regardless of fluctuations in the digit line. It has many effects such as:

[Brief explanation of the drawing]

1 and 2 are circuit diagrams of C-MOS sense amplifiers showing first and second embodiments of the present invention, respectively, and FIG. 3 is a circuit diagram for explaining a conventional C-MO8 sense amplifier. be. FIG. 4 is a waveform diagram for explaining the operation of the sense amplifier of FIG. 3 and the present invention. In the symbols in the figure, Q8~Q8° are transistors, 01~Q8° are transistors,
〆, is the clock signal, VDD is the high potential power supply, GND
indicates a zero potential power supply, N1 to N4 indicate the terminals of the circuit or their potentials, and D□lDt indicates the digit line or its potential, respectively. Patent applicant: NEC Corporation Representative: Susumu Uchihara, patent attorney Figure 2b
bFigure 4j+ Lz t3t4

Claims (1)

[Claims] (1) first and second terminals respectively coupled to the first and second power supplies via MIS transistors, with the source connected to the first terminal, the drain connected to the first digit line, and the gate connected to the second digit line; the first p respectively coupled to the digit lines of
- a MIS transistor with a source connected to the first terminal;
a second p-MIS having a drain coupled to the second digit line and a gate coupled to the first digit line;
a first n-MIS transistor having a source coupled to the second terminal, a drain coupled to the first digit line, and a gate coupled to the second digit line, and a source coupled to the second terminal; and a second n-MIS transistor having a drain coupled to the second digit line and a gate coupled to the first digit line. and first and second MIS transistors that respectively couple the second terminal and the first and second digit lines, and third and fourth MIS transistors that couple the second terminal and the first and second digit lines, respectively. A C-MIS sense amplifier characterized by: