JPS6133565A - Program loading system - Google Patents

Abstract

PURPOSE:To reduce a program loading time by setting up a common storage means formed on a common bus as a program area to be used for plural processors in common and executing a program without reading it in a main storage device of a processor. CONSTITUTION:A data processing system has the 1st and 2nd processors 10, 20, an auxiliary storage means 30 is connected to the 2nd processor 20 and a common storage means 50 is connected to a common bus 40. The common storage means 50 is set up in a common program area to the processors 10, 20 and a program to be executed in each time is loaded from the auxiliary storage means 30 to the program area, so that the program is executed as it is without being read in the exclusive main storage means 13, 23 included in respective processors 10, 20.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention includes a plurality of processors that are interconnected via a common bus, an auxiliary storage means that is attached to at least one of the processors and stores a program, and a common processor that is provided on the common bus. A method of loading programs in a data processing system equipped with a storage means, especially a program loading method in a data processing system that is composed of a plurality of relatively small processors and a storage means, but has to execute a wide variety of programs.
This invention relates to a program loading method suitable for small data processing systems such as O8 devices.

[Prior art and its problems]

As is well known, when the type and amount of data processing to be performed by one processor or one CPU increases and it is no longer possible to handle this increase, multiple processors are used. Especially in cases like the PO8 device mentioned above,
In order to make the device compact and inexpensive, CPUs that are relatively small and have limited data processing capabilities are used, so it is advantageous to make the data processing system with so-called multi-CPUs. This allows complex data processing
This is because, in addition to being able to meet administrative demands, it is also possible to share data processing jobs or to proceed with control operations in parallel, thereby improving processing speed. In such a data processing system using multiple processors, each processor is provided with an attached RAM that stores the programs that the processor is responsible for and should execute. Normally, all programs are stored in advance in RAMs attached to each of these plurality of processors. In this way, when processing data, each processor can sequentially or simultaneously read programs from its attached RAM and process data quickly, but on the other hand, when the amount of programs increases, A program area must be secured in each RAM, the RAM storage capacity required for the entire data processing system must be increased, and a common data bus for all processors must be allocated on a common data bus that links multiple processors. A RAM is provided and programs necessary for the entire data processing system are stored in it, and each processor accesses this common RAM and reads out the necessary programs as needed. Theoretically, there is an advantage that there is no need to repeatedly store commonly required programs in each processor, but when executing each program, the program in the common RAM is first read into the RAM attached to each processor and then executed. This method is not very effective in reducing the total required RAM capacity, and is particularly unsuitable for small data processing systems such as PO8 devices. In addition, there is a method in which an auxiliary storage means such as a magnetic disk device provided commonly to all processors is selected as a permanent storage location for programs, and a program commonly required for each processor is loaded from this means to all processors at the same time.
There is also a known method in which programs are sent to all processors in parallel, but the receiving processor reads only the programs it needs based on the identification code attached to the program. It is still necessary to load the program into the RAM attached to the processor, and it is not necessarily effective in eliminating the total amount of RAM required.

[Purpose of the invention]

Based on the above-mentioned problems of the prior art, the present invention provides a system that uses a plurality of common storage means having the minimum necessary storage capacity even if the amount of programs required for a data processing system including a plurality of processors increases. To provide a program loading method that does not require essentially increasing the storage capacity of a main storage means such as a RAM attached to each processor by simply providing processors on a common bus that cooperates with each other. Further, a secondary object of the present invention is to suppress the time required for loading a program within a practical range.

[Key points of the invention]

According to the present invention, the above object is achieved in a data processing system equipped with an auxiliary storage means as described in Wm, in which the common storage means is set as a common program area accessible from processors within the system. Whenever it becomes necessary to load a program to be executed in the first processor, the first processor issues a program loading command to the second processor equipped with the auxiliary storage means and receives the command. The second processor loads the program designated by the first processor from the auxiliary storage means into the common storage means based on the command, and gives a loading completion notification to the first processor, and
This is easily achieved by a program loading method that allows the processor to execute the program loaded into the common storage means based on the notification. In a data processing system in which the method of the present invention is adopted, each processor has its own basic job to perform, and the main storage means such as RAM attached to it stores programs necessary to perform the basic job. The program to be executed by the processor each time is only transferred from the auxiliary storage means to the common storage means, and remains on the common storage means when the specific program that issued the load instruction for the program is executed. executed by the processor. Of course, during this execution the programs required by other processors not provided with auxiliary storage means cannot be transferred to the common storage means, but during this time the other processors can perform their basic dup. but,
This provides the great advantage that the main storage means attached to each processor does not need to have extra capacity necessary to read the programs to be executed each time. Moreover, since the program is transferred from the auxiliary storage means to the common storage means by the processor equipped with the auxiliary storage means, the processor receiving the program does not need to execute a program for transferring the program. (Accordingly, there is no need to provide storage capacity for storing transfer programs in each main storage means attached to the processor.) The load command and load completion notification described above are effective in increasing the data processing speed of the system by using a common bus. Advantageously, the interrupt commands are supplied from one processor to the other processor via the processor or via a separate command line in the form of interrupt commands, which interrupt commands are then loaded into the common storage means. the verification code of the program to be
In the case of a 112-load command, the identification code of the processor issuing the load command can be included. Further, all or part of such commands and notices can be given to the other party via a common storage means, and in this case, the common storage means stores the verification code of the program and the identification code of the processor. It is possible to set up an area with a promised address for the purpose, and have one processor write the contents of commands and notifications to this area, and the other processor that receives them to read them.However, in practice, In this case, it is advantageous to give the fact that there is a command or notification to the other party in the form of an interrupt command, and to transmit the specific contents to the other party via the common storage means. In addition, when transferring a program from the auxiliary storage means to the common storage means, problems such as deformation of the program data may be discovered, so it is important to check whether the program has been transferred successfully or not, and if there is a problem, identify it. It is effective to transmit the indicated error code to the other party as status information in order to maintain the operational reliability of the system. in this case,
In order to convey status information in detail, it is preferable to reserve a storage area for the status information in the common storage means in advance and to transmit the information via this area. Furthermore, in order to increase the overall data processing speed of the system,
It is advantageous to reduce the transfer time by dividing the program to be transferred each time to the common storage means into a plurality of program parts so that the program parts transferred at one time are shortened. Although this does not necessarily shorten the transfer time of the entire program, in the case of a multi-program program, it is preferable to start execution of the first part of the program earlier than to have a slight delay in the middle of execution. For example, in the case of a POS device, even if the sales registration program and the subsequent receipt typeout program are separated and the latter is automatically transferred after the former is executed, there will be no problem in sales activities. In such a specific case, by dividing the program, the partial program length can be shortened to at most two records, or about 512 bytes, and even if a floppy device with a relatively long access time is used as the auxiliary storage means, the program can be saved. The time required to complete execution can be reduced to 0.5 seconds or less. Also, the storage capacity of the common storage means can be reduced accordingly, and if the partial program length is around 500 bytes as described above, Even if a storage area for commands and notification contents and a storage area for status information are added, the required storage capacity can be sufficiently suppressed to within 1 kilobyte.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. This embodiment will be explained by taking as an example a PO8 device to which the present invention is advantageous, particularly a PO51x for a refueling service station such as a gas station. FIG. 1 is a block diagram showing the hardware configuration of such a PO8 device, in which the first processor in the system of the present invention is 10. The second processor is 20. The auxiliary storage means attached to the second processor is 309; the common bus linking both processors is 40°; the common storage means provided on the common bus is shown at 50;
The first processors 10 and 20 are themselves microcomputers each equipped with an input/output device, and the core CPU 21 is a processor in the narrow sense. It is used in a broad sense. The first processor 10 is, so to speak, the central part of this PO8 device, and in addition to the input/output device shown schematically at 60, this PO8 device and, in a special form, are installed at an outdoor gasoline sales site located a little away from the main body of the PO3 device. A vending machine section 70 installed in the machine is attached. Although only one set of the vending machine section 70 is shown in the figure, several sets are normally provided in parallel. Up to this point, it's just one micropro. However, if the system becomes larger, a plurality of first processors 10 may be provided, all using a common bus 4.
Of course, there will be a need for mutual cooperation in 0. The first processor IO itself is a CPU 11 as usual.
．． ROM12. RAM13. Address decoder 14°, consists of input/output ports 15 to 18, etc., and address bus 10a
and are communicated by a data bus 10b. Kapo in and out
) 15.16 are connected to an input/output device 60, and this input/output device 60 includes a display device 61.) such as a CRT. Keyboard 62. Card reader 63. It includes a printer 64 and the like, and is connected to input/output ports 15 and 16 via controllers or signal converters whose respective symbols have a suffix a. Note that 62a is a display device 61. This controller is shared by the keyboard 62, and 62b is an attached interface dedicated to the keyboard 62. The vending machine section 70 is connected to the first processor 10 via an input/output capo 17.18 and a card league 71. printer 7
2. In addition, it includes a control switch 73 that drives a gasoline pump 74 as a vending machine, and a pulse generator 75 that measures the flow rate of gasoline. This vending machine section 70 is connected online with the processor 10, and the actual vending operation is carried out using, for example, a card reader 7.
The process begins with the insertion of the customer card 71a into the card 1. This starts the sales program, and the program is loaded into the common storage means 50 as described below. Whether or not the customer's card verification code is legitimate is determined by comparing it with the stored value in the RAM 13 as the main storage means in the processor 10, and if it is legitimate, the input/output capo) 1B
A command to unlock the gasoline pump is issued to the control switch 73 via. This unlocks the pump 74 and allows the salesperson to service the customer via the hose 76. The refueling amount is taken into the processor 10 in the form of pulses from the pulse generator 75 via the pulse coupler 18a and the input/output hoard 18, and is stored in the refueling amount storage area in the RAM 13 as an integrated value. R.A.
M13 also remembers the unit price list, and at the time it receives the signal from the previous card reader 71, it knows which service station the signal came from and therefore what kind of gasoline it is. , the sales amount is calculated according to the program from the unit price and oil supply amount for that item. For example, the program moves to the next printing program, and the necessary data including the calculation results and the amount of oil supplied are transferred to the input/output port 17.
The data is output to the printer 72 via the printer 72, and a receipt is created. Further, when a deposit is made at the same time as a sale, a deposit key in the keyboard 62 is operated, thereby starting a deposit processing program. In addition to the above-mentioned sales operation programs, various data processing and control programs are stored on the keyboard 62. Each input from Card League 63.71. Alternatively, the RAM 13 in the first processor 10 stores variables such as sales volume, item, payment terms, customer verification code, unit price, etc. during these data processing operations and control operations. It is mainly used as a storage area for constants and as a register area for data processing result values, and programs that specify data processing formats using such variables and constants are stored in the common storage means 50 from the second processor 20 side as necessary. be transferred. However, the unique programs for the input/output device f60 attached to the first processor 10 and the vending machine section 70 that are not related to such constants and variables should be resident in the ROM 12 or RAM 13 rather than being transferred from the second processor 20. It goes without saying that it is more advantageous to keep the program running in the first processor 10 (it goes without saying that it is more advantageous). It can be compressed to the minimum necessary level.Now, the second processor 20 on the side that transmits the program
As before, CPU21. ROM22. RAM23.
Address decoder 24. It is a single microcomputer with input/output ports 25 and 2611, and is connected via the input/output ports 26 to an auxiliary storage means 30 where programs reside. The means 30 is, for example, a floppy device! 31 and its controller 32. Also the second
The processor 20 includes a MODEM for offline communication via a communication line 28 with a host computer in the management data center using the illustrated data processing system as a terminal.
27 etc. are connected via the input/output port 25. The address bus 10a, 20a and the data bus 10b, 20b of the first and second processors 10.20 are connected to the address bus 40a+data bus 40b of the common bus 40 via bus switching means 41.42, respectively, which are simply shown. They are linked in a switchable manner. Various publicly known methods are known for bus connection and its switching control in a multiprocessor system, and any of these methods may be used to implement the present invention.
0 consists of, for example, a single small-capacity RAM 51, and is directly connected to both the address and data buses 40a and 40b of the 1 common bus 40, for example. Next, the operation of the method of the present invention in a data processing system having the hardware configuration as exemplified above will be explained with reference to FIGS. 2 and 3. FIG. 2 schematically shows the operation of the method of the present invention,
FIG. 3 is a flowchart of the operation, and operation steps S1 to S12 in the flow are used as common symbols in both figures. In this embodiment, the aforementioned program load command LS and load completion notification AS are issued in the form of interrupt commands, and the verification code PN specifying the transfer program and transfer status information qps are transmitted via the common storage means 50. This corresponds to the mode of doing so. The starting command for the program to be executed by the first processor 10 in FIG. 10 starts the operation flow on the first nophrosetter side shown in the right column of FIG. In step S1, the verification code or program number PN of the program corresponding to the startup command is stored in the program verification area 50 of the common storage means 50.
Write in b. This program number PM is a number indicating a sales program in the case of a start command from the card reader 71, and at this time, the data written in the program verification area 50b includes a load command LS if necessary. The verification code of the processor that issued the message, for example the number 1 of the first processor, can be added. In the following step S2, the load command LS is directly transmitted to the second processor 20 in the form of an interrupt command in this example. The format of this command can be to specify a so-called interrupt level or to include a verification code of the previous processor. The second processor 20 starts the operation flow shown in the left column of FIG. 3 by reading this interrupt command S written into the latch of its interrupt reception circuit, for example, and starts the operation flow shown in the left column of FIG. In S3, the program number PN is read from the program matching area 50b of the common storage means 50, and the physical address in the auxiliary storage means 30 where the program P with the number PN requested for transfer is stored is determined, and then the next step is performed. The means 30 in S4
issues a program transfer command. The auxiliary storage means 30 immediately transfers the program P designated by the command to the program area 50a of the common storage means 50, preferably via a known DMA circuit, but during this transfer, the second processor 20 Watch whether the transfer is completed. However, in this embodiment, the transfer time of the program P within two records may be very short, so the flow immediately moves to 86 and the transfer status information ps is stored in the status information area 50 of the common storage means 50.
The status information PS written in c can include, in addition to indicating whether or not the transfer is normal as described above, an error code indicating the type of abnormality if the transfer is not normal. In either case, the flow enters the next status information S7,
A load completion notification ^S is sent to the first processor in the form of an interrupt command, and the operation flow on the second processor side is thus completed. If there are multiple first processors,
It is also possible to store the verification code of the processor that issued the load command LS in the previous step S2 or S3, and to specify the processor to issue the load completion notification As. After issuing the load command LS in the previous step S2, the first processor 10 side watches whether or not the transfer from the second processor 20 side is completed in the subsequent step S8. When the completion notification ^S is written, for example, to the lunch for accepting interrupt commands, the process immediately enters the next step S9, reads the status information @PS from the status information area 50c of the common storage means 50, and checks whether the transfer was normal or not. To check. If the transfer is normal, the flow moves to step 510 as planned and enters the step of executing the program P, but if not, the flow moves to the right side of the diagram and the display 6 is displayed at step Sll.
Step 51 where the flow is immediately terminated after displaying an error code as status information PS in step 1.
In G, the program is executed while the program P remains in the program area 50a of the common storage means 50. Therefore, the first processor sets the so-called program counter to the start address of the program area 50m, and then starts the execution stage. The count may be incremented sequentially according to the Depending on the program to be executed, it is necessary to automatically start another program subsequently, and after the program is executed in step 310, it is determined in step S12 whether or not it is necessary to start a subsequent program, and if not, of course The flow is terminated, but if necessary, the flow automatically returns to step S1 and repeats the above-mentioned process. The designation of the subsequent program can be written in advance in the preceding program, stored in the RAM 13 in the first processor 10, or determined in the first processor each time. By dividing a program into relatively short units and sequentially transferring and executing them in this way, the storage capacity required for the common storage means can be reduced, and the time required for one transfer can be shortened. It is possible to speed up the process. Not limited to the specific embodiments described above, the method of the present invention can be widely used as a program loading method for a data processing system consisting of any plurality of processors, and can be applied to various embodiments different from the above embodiments. can be implemented within the spirit of the invention. Effects of the Invention As described above, according to the method of the present invention, a data processing system consisting of a plurality of processors each having an auxiliary storage means in which a program is resident, at least one of which is provided on a common bus. A shared storage means is set as a program area shared by multiple processors, and the program to be executed each time is loaded from the auxiliary storage means into the area, without loading the program into the dedicated main storage means attached to each processor. Since the program is executed as is, even if the amount of programs required to operate the data processing system increases, there is no need to increase the storage capacity of the main memory attached to each processor as in the past. Since the loading or transfer of programs is all performed by the processor having auxiliary storage means, each receiving processor is completely free from the burden of running a program for program transfer or storing the programs necessary for transfer. will be released. The program loading method according to the present invention is essentially suitable for a data processing system that is a complex system of processors with relatively small processing power and storage capacity, but on the other hand, it is necessary to execute a wide variety of programs as needed. This method is particularly suitable for POS devices that require processing capacity of medium capacity or less, and by adopting this method, the economic efficiency of this type of PO8 device can be significantly improved. Furthermore, the operating speed of a data processing system implementing the method of the present invention is naturally slower than a method in which all necessary programs are stored in the main storage means attached to the processor.
Compared to the conventional method in which a program is read from the auxiliary storage means to the main storage means each time, this method is about the same speed, or rather faster due to the fact that the program is not transferred from the common storage means to the main storage means, so there is no problem in practical use. However, if the program to be executed is divided into multiple parts in a form suitable for processing and each partial program is unified, the loading time of the program can be further reduced. By configuring a complex processing program by combining the following, the total amount of the necessary program can be compressed, and great convenience can be obtained in terms of program file management.

[Brief explanation of the drawing]

The figures are all for the purpose of explaining the method of the present invention, of which Figure 1 is a block circuit diagram of a POS device for a refueling service station suitable for application of the program loading method according to the present invention, and Figure 2 is a block circuit diagram of the method of the present invention. FIG. 3 is a flowchart illustrating the operation flow of the method of the present invention. In FIG. 0, 10: first processor, 20: second processor, 3
0: Auxiliary storage means, 40: Common bus, 50: Common storage means, 50m+program area, 50b Niprogram verification area, 50C: Status information area, ^S:
Load completion notification, LS: load command, P nib program,
This is the verification code of the PN program, PS: status information.

Claims (1)

[Scope of Claims] 1) A plurality of processors interconnected via a common bus, an auxiliary storage means attached to at least one of the processors and storing a program, and a plurality of processors connected to the common bus. A program loading method in a data processing system comprising a common storage means provided in a first processor in the system, wherein the common storage means is set as a common program area accessible from a first processor in the system.
When it becomes necessary to load a program to be executed in a second processor, the first processor issues a program load command to the second processor equipped with the auxiliary storage means, and the first processor receives the command. Based on the instruction, the second processor loads the program designated by the first processor from the auxiliary storage means to the common storage means and gives a load completion notification to the first processor, and the first processor responds to the notification. 1. A program loading method, characterized in that a program loaded into said common storage means can be executed based on said common storage means. 2) In the method described in claim 1, the load command from the first processor is sent as an interrupt command to the second processor.
A program loading method characterized in that the program is given to a processor. 3) A program loading method according to claim 1, characterized in that a loading completion notification from the second processor is given to the first processor as an interrupt command. 4) In the method described in claim 1, an area for storing a program verification code is set in the common storage means, and the first processor stores the program verification code in the common storage means. 1. A program loading method characterized in that a program to be loaded is specified, and the second processor reads the verification code written in a verification code area based on the load command. 5) In the method described in claim 1, an area for storing status information of a program loaded into the common storage means is set, and the second processor stores the status information of the program when loading the program. A method for loading a program, characterized in that information is written in the area, and the first processor is able to read the status information based on a loading completion notification. 6) A program loading method according to claim 1, characterized in that a load command or a load completion notification is given to the other processor via a common bus. 7) In the method described in claim 1, the program to be executed by the first processor is divided into a plurality of program parts and loaded into the common storage means for each program part. 1. A program loading method characterized in that one processor issues a load command for the next program portion to a second processor each time execution of one program portion is completed.