JPS6133519A - Reference voltage source circuit - Google Patents
Reference voltage source circuitInfo
- Publication number
- JPS6133519A JPS6133519A JP15587284A JP15587284A JPS6133519A JP S6133519 A JPS6133519 A JP S6133519A JP 15587284 A JP15587284 A JP 15587284A JP 15587284 A JP15587284 A JP 15587284A JP S6133519 A JPS6133519 A JP S6133519A
- Authority
- JP
- Japan
- Prior art keywords
- reference voltage
- transistor
- resistor
- collector
- voltage source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、集積回路に用いられる、基準電圧源回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a reference voltage source circuit used in integrated circuits.
従来例の構成とその問題点
近年、集積回路の低電圧化に伴ない、ツェナーダイオー
ドを用いた基準電圧源に代わって、バンドギャップ型の
基準電圧源が多く用いられてきている。以下に、従来の
バンドギャップ型の基準電−圧源回路について説明する
。Conventional Structures and Their Problems In recent years, as the voltage of integrated circuits has become lower, band gap type reference voltage sources have been increasingly used in place of reference voltage sources using Zener diodes. A conventional bandgap reference voltage source circuit will be described below.
第１図は従来のバンドギャップ型基準電圧源の回路例を
示すものであり、図において、１はＮＰＮトランジスタ
、２はエミッタ面積の大きなＮＰＮトランジスタ、３，
４は抵抗、６，６はエミッタ面積の等しいＰＮＰ トラ
ンジスタ、７は電源端子、８は基準電圧端子である。FIG. 1 shows a circuit example of a conventional band gap type reference voltage source. In the figure, 1 is an NPN transistor, 2 is an NPN transistor with a large emitter area, 3,
4 is a resistor, 6 and 6 are PNP transistors having the same emitter area, 7 is a power supply terminal, and 8 is a reference voltage terminal.
第１図において、トランジスタ２とトランジスタ１との
エミッタ面積の比をｎ、抵抗３の抵ｍｌ値をＲ１とする
と、トランジスタ１のコレクタ電流Ｉｃは、下のように
表わされる。In FIG. 1, if the ratio of the emitter areas of transistor 2 and transistor 1 is n, and the resistance ml value of resistor 3 is R1, the collector current Ic of transistor 1 is expressed as below.
ＩＣ＝ｋＴ／（ｉ−Ｒ１）
（ｋはボルツマン定数、Ｔは絶対温度）又、トランジス
タ１のベース、エミッタ電圧をＶｂｅ、抵抗４の抵抗値
をＲ２とすると、端子８の電圧は、下のように表わされ
る。IC=kT/(i-R1) (k is Boltzmann's constant, T is absolute temperature) Also, assuming that the base and emitter voltages of transistor 1 are Vbe and the resistance value of resistor 4 is R2, the voltage at terminal 8 is It is expressed as follows.
■８＝ＩＣ−Ｒ２＋ｖｂｅ
＝ｋＴ−Ｒ２／（洲・Ｒ４）＋ｖｂｅ
次Ｋ、端子８の電圧の温度依存性は次のように表わされ
る。8=IC-R2+vbe=kT-R2/(S-R4)+vbe Next, the temperature dependence of the voltage at terminal 8 is expressed as follows.
ｄ■８／ｄＴ＝に−Ｒ２／（ε・Ｒ１）＋ｄｖｂｅ／ｄ
Ｔ
こコテ、ｄｖｂ８／ｄＴ〜−１，８ｍｖ／℃ であり、
一方、ｋ−Ｒ２／（ｔ−Ｒ１）は正数であるので、適当
なＲ２の値を選べば、端子８の電位ｖ８の温度係数をゼ
ロにすることができる。d■8/dT=to-R2/(ε・R1)+dvbe/d
T here, dvb8/dT~-1.8mv/℃,
On the other hand, since k-R2/(t-R1) is a positive number, if an appropriate value of R2 is selected, the temperature coefficient of the potential v8 of the terminal 8 can be made zero.
しかしながら、上記のような構成では、端子８の電位ｖ
８の温度係数をゼロにするには、抵抗４の抵抗値Ｒ２の
値が固定されてしまうため、基準電圧源の電圧値が自由
に設定できないという問題点を有していた。因みに、第
１図の従来例の場合には基準電圧値（出力）は約１，２
ｖである。However, in the above configuration, the potential v of the terminal 8
In order to make the temperature coefficient of 8 zero, the resistance value R2 of the resistor 4 has to be fixed, so there is a problem that the voltage value of the reference voltage source cannot be set freely. Incidentally, in the case of the conventional example shown in Figure 1, the reference voltage value (output) is approximately 1.2
It is v.
発明の目的
本発明は、上記従来の問題点を解消するもので、電圧の
温度係数がゼロで、しかも電圧値を自由に設定できる基
準電圧源回路を提供することを目的とする。OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems and aims to provide a reference voltage source circuit in which the temperature coefficient of voltage is zero and the voltage value can be freely set.
発明の構成
本発明は、エミッタを電源端子に接続し、ベースとコレ
クタとを共通接続した第１のＰＮＰ トランジスタのベ
ースを、同じくエミッタを電源端子。Structure of the Invention The present invention is based on a first PNP transistor whose emitter is connected to a power supply terminal and whose base and collector are commonly connected.
ニ接続した第２のＰＮＰ トランジスタのベースニ接続
するとともに、エミッタを接地し、ベースとコレクタを
共通接続した第１のＮＰＮ トランジスタのベースを、
エミッタを他端を接地した第１の抵抗に接続した、前記
第１のＮＰＮトランジスタよりエミッタ面積の大きい第
２のＮＰＮトランジスタのベースに接続し、かつ前記第
１のＰＮＰ トランジスタのコレクタを前記第２のＮＰ
Ｎ）う゛ンジスタのコレクタに、前記第２のＰＮＰトラ
ンジスタのコレクタを前記第１ＯＮＰＮトランジスタの
コレクタに接続した構成を具備し、かつ、エミッタを電
源端子に接続し、ベースを前記第１のＰＮＰ トランジ
スタのベースに接続した第３のＰＮＰトランジスタを設
け、この第３のＰＮＰトランジスタのコレクタに、他端
を、カソード側を接地した１個又は直列接続した複数個
のダイオードのアノード側に接続した第２の抵抗と他端
を接地した第３の抵抗とを接続し、前記第３のＰＮＰト
ランジスタのコレクタを基準電圧端子とする基準電圧源
回路である。The base of the second PNP transistor is connected to the base of the first NPN transistor, whose emitter is grounded, and whose base and collector are commonly connected.
A second NPN transistor having an emitter area larger than that of the first NPN transistor is connected to the base of the second NPN transistor whose emitter is connected to a first resistor whose other end is grounded, and the collector of the first PNP transistor is connected to the second NPN transistor. NP of
N) The collector of the transistor has a configuration in which the collector of the second PNP transistor is connected to the collector of the first ONPN transistor, the emitter is connected to the power supply terminal, and the base is connected to the collector of the first PNP transistor. A third PNP transistor connected to the base is provided, and a second PNP transistor whose other end is connected to the anode side of one or a plurality of series-connected diodes whose cathodes are grounded is provided. This is a reference voltage source circuit in which a resistor and a third resistor whose other end is grounded are connected, and the collector of the third PNP transistor is used as a reference voltage terminal.
実施例の説明
第２図は、本発明による基準電圧源の回路例を示すもの
であり、図において、９はＮＰＮトランジスタ、１ｏは
ＮＰＮ トランジスタ９よりエミッタ面積の大きなＮＰ
Ｎトランジスタ、１１，１５゜１６は抵抗、１２，１３
．１４はエミッタ面積の等しいＰＮＰトランジスタ、１
７はダイオード、１８は電源端子、１９は基準電圧端子
である。DESCRIPTION OF EMBODIMENTS FIG. 2 shows a circuit example of a reference voltage source according to the present invention.
N transistor, 11, 15° 16 is a resistor, 12, 13
．． 14 is a PNP transistor with equal emitter area, 1
7 is a diode, 18 is a power supply terminal, and 19 is a reference voltage terminal.
以上のように構成された本実施例の基準電圧源回路につ
いて、以下その動作を説明する。The operation of the reference voltage source circuit of this embodiment configured as described above will be described below.
第２図において、トランジスタ１４のコレクタ電流Ｉｃ
は、従来例と同様にして
Ｉｃ＝ｋＴ／（ら・Ｒ１）１
で表わされる。ただし、抵抗１１．１５．１６の抵抗値
をそれぞれＲ１’、Ｒ２，Ｒ３とする。又、端子１９の
電圧Ｖ１９ は、下のように表わされる。In FIG. 2, the collector current Ic of the transistor 14
is expressed as Ic=kT/(ra·R1)1 in the same manner as in the conventional example. However, the resistance values of resistors 11, 15, and 16 are assumed to be R1', R2, and R3, respectively. Also, the voltage V19 at the terminal 19 is expressed as below.
ｖ１９＝Ｒ２・Ｒ３・工Ｃ／（Ｒ２中Ｒ３）＋Ｒ３・ｖ
ｂｅ／（Ｒ２中Ｒ３）
端子１９の電圧Ｖ１９ の温度係数をゼロにするには、
ｄｖ１９／ｄＴ＝０
すなわち
Ｒ２＝−（ｄｙｂｏ／ｄｒ ）−（ｉｉｉ・Ｒ１）／に
とすればよい。この時、Ｒ３の値は自由に選べるので、
Ｒ３の値を適当に選ぶことにより、Ｒ３が無限大の場合
の端子１９の電圧
Ｖ１９＝Ｒ２−Ｉａ＋Ｖｂｅ
を最大値として、これ以下の自由な電圧を設定する事が
できる。v19=R2・R3・Work C/(R3 in R2)+R3・v
be/(R3 in R2) To make the temperature coefficient of the voltage V19 of the terminal 19 zero, it is sufficient to set dv19/dT=0, that is, R2=-(dybo/dr)-(iii·R1)/. At this time, the value of R3 can be chosen freely, so
By appropriately selecting the value of R3, it is possible to set the voltage at the terminal 19, V19=R2-Ia+Vbe, as the maximum value when R3 is infinite, and set any voltage below this value.
以上のように本実施例によれば、従来のバンドギヤング
型の基準電圧源回路に第３の抵抗を付加する事により、
基準電圧の温度係数がゼロで、従来の基準電圧値（約１
．２Ｖ ）以下の自由な電圧値の設定が可能な基準電圧
源を構成する事ができる。As described above, according to this embodiment, by adding the third resistor to the conventional bandgyoung type reference voltage source circuit,
The temperature coefficient of the reference voltage is zero, and the conventional reference voltage value (approximately 1
．． It is possible to configure a reference voltage source that can freely set a voltage value of 2V or less.
なお、実施例において、ダイオード１７は単一のダイオ
ードとしたが、これを直列接続した複数個のダイオード
としてもよい。この場合、ダイオードの個数を適当に選
ぶごとにより、より広い範囲の基準電圧値の設定が可能
となる。In the embodiment, the diode 17 is a single diode, but it may be a plurality of diodes connected in series. In this case, by appropriately selecting the number of diodes, it becomes possible to set the reference voltage value in a wider range.
発明の効果
本発明によれば、従来のバンドギャップ型の基準電圧源
回路に第３の抵抗を付加することにより、電圧の温度係
数がゼロで、しかも電圧値を自由に設定できる優れた基
準電圧源回路を実現できる。Effects of the Invention According to the present invention, by adding a third resistor to the conventional band gap type reference voltage source circuit, an excellent reference voltage with a voltage temperature coefficient of zero and which can freely set the voltage value can be obtained. A source circuit can be realized.
第１図は従来のバンドギャップ型基準電圧源の回路図、
第２図は本発明の実施例における基準電圧源の回路図で
ある。
１、２ 、９ 、１ ｏ・−−・ＮＰＮ ） ランジス
タ、５゜６．１２，１３．１４ ・・・ＰＮＰ トラ
ンジスタ、３、．４，１１．１５，１４３・・・・・・
抵抗、１７・・・・・ダイオード、７，１８・・・・・
・電源端子、８，１９・・・−・・基準電圧端子。Figure 1 is a circuit diagram of a conventional bandgap reference voltage source.
FIG. 2 is a circuit diagram of a reference voltage source in an embodiment of the present invention. 1, 2, 9, 1 o・---・NPN) transistor, 5° 6.12, 13.14...PNP transistor, 3, . 4,11.15,143...
Resistor, 17...Diode, 7, 18...
- Power supply terminal, 8, 19...--Reference voltage terminal.
Claims (1)
通接続した第１のＰＮＰトランジスタのベース、コレク
タを、同じくエミツタを電源端子に接続した第２のＰＮ
Ｐトランジスタのベースに接続するとともに、エミツタ
を接地し、ベースとコレクタを共通接続した第１のＮＰ
Ｎトランジスタのベースを、エミツタを他端を接地した
第１の抵抗に接続した、前記第１のＮＰＮトランジスタ
よりエミツタ面積の大きい第２のＮＰＮトランジスタの
ベースに接続し、かつ前記第１のＰＮＰトランジスタの
コレクタを前記第２のＮＰＮトランジスタのコレクタに
、前記第２のＰＮＰトランジスタのコレクタを前記第１
のＮＰＮトランジスタのコレクタに接続した構成を具備
し、かつ、エミツタを電源端子に接続し、ベースを前記
第１のＰＮＰトランジスタのベースに接続した第３のＰ
ＮＰトランジスタを設け、この第３のＰＮＰトランジス
タのコレクタに、他端を、カソード側を接地した１個ま
たは直列接続した複数個のダイオードのアノード側に接
続した第２の抵抗と、他端を接地した第３の抵抗とを接
続したことを特徴とする基準電圧源回路。A first PNP transistor whose emitter is connected to a power supply terminal, and whose base and collector are commonly connected, is connected to a second PN transistor whose emitter is also connected to a power supply terminal.
The first NP is connected to the base of the P transistor, its emitter is grounded, and its base and collector are commonly connected.
The base of the N-transistor is connected to the base of a second NPN transistor having a larger emitter area than the first NPN transistor, the emitter of which is connected to a first resistor whose other end is grounded, and the first PNP transistor The collector of the second PNP transistor is the collector of the second NPN transistor, and the collector of the second PNP transistor is the collector of the first NPN transistor.
A third PNP transistor is connected to the collector of the first PNP transistor, has an emitter connected to a power supply terminal, and has a base connected to the base of the first PNP transistor.
An NP transistor is provided, and a second resistor is connected to the collector of the third PNP transistor, and the other end is connected to the anode side of one or a plurality of diodes connected in series, the other end of which is grounded. A reference voltage source circuit characterized in that a third resistor is connected to the reference voltage source circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15587284A JPS6133519A (en) | 1984-07-26 | 1984-07-26 | Reference voltage source circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15587284A JPS6133519A (en) | 1984-07-26 | 1984-07-26 | Reference voltage source circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6133519A true JPS6133519A (en) | 1986-02-17 |
Family
ID=15615345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15587284A Pending JPS6133519A (en) | 1984-07-26 | 1984-07-26 | Reference voltage source circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6133519A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05206755A (en) * | 1992-01-29 | 1993-08-13 | Nec Corp | Reference voltage generating circuit |
-
1984
- 1984-07-26 JP JP15587284A patent/JPS6133519A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05206755A (en) * | 1992-01-29 | 1993-08-13 | Nec Corp | Reference voltage generating circuit |
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