JPS61294582A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To decrease the quantity of hardware and also to facilitate a comparison operation by using a fixed decimal point addition/subtraction circuit and a positive/negative deciding circuit to perform comparison operation between operands. CONSTITUTION:When a comparison operation is carried out between operands Ai and Bi, these operands are held by operand holding registers 21 and 22 of a fixed decimal point addition/subtraction device. Then an arithmetic mode signal is supplied to an arithmetic circuit 234 and an arithmetic exception detecting circuit 24 respectively from an input device to suppress the report of an arithmetic exception state. The circuit 23 uses both operands Ai and Bi for execution of an arithmetic operation and this arithmetic result is applied to a selection circuit 26 as well as to a selection circuit 26 via an inverting circuit 25. The circuit 26 selects an input according to the output given from the circuit 24 and applies it to an output holding register 27. The output of the register 27 is supplied to a positive/negative deciding circuit for comparison with zero.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an arithmetic device having a function of performing a comparison operation between operands, and particularly to an arithmetic device having a function of performing a comparison operation between two fixed-point operands. Regarding.

(Prior Art) Generally, a conventional arithmetic unit having a function of processing a comparison operation between operands includes a dedicated circuit for executing a comparison operation between operands.

Here, an example of the above-mentioned dedicated circuit will be described with reference to FIG. 5. First operand A (SA: code).

A6 r AI + A2 + A3 Awn →: Numerical part) is held in the second manual register 52. The first operands A and B are input to arithmetic circuits 53 and 54 as shown. The arithmetic circuit 53 calculates the first opera using the logical formula shown in equation (1).

The magnitude relationship between the second operand A and the second operand B is determined.

The remaining days x = (3, △S,) V (SA = SR) △ ((AOABO
)■(AO=BO)△(Lice to A1)(AO=BQ)(
At =Bt)△(AZAB2)(AO=BO)△
(At = Bt)△(A2=B2)△(A3AB3
)...(1) On the other hand, the arithmetic circuit 54 compares whether the first operand A and the second operand B are equal using the logical expression shown in equation (2).

y=(SA=SB)△(AO~, -B0~3)
(2) The outputs of the arithmetic circuits 53 and 54 are stored in the output renosters 55 and 56, respectively. In this way, a comparison operation between operands A and H is performed.

(Problems to be Solved by the Invention) As described above, the conventional arithmetic device equipped with the function of performing comparison operations between operands has a new dedicated circuit (comparison operation circuit) for performing comparison operations between operands. Because of this, there is a problem that the amount of hardware increases.

An object of the present invention is to provide an arithmetic device that requires less hardware than conventional arithmetic devices.

Hereinafter, Kanpaku (means for solving the problem) Generally, in an arithmetic device, there is a fixed-point addition/subtraction circuit that performs addition/subtraction of fixed-point data.

A positive value that determines the magnitude relationship between the input operand and zero.
A negative or zero judgment circuit is minimally required.

In the arithmetic device of the present invention, in the case of 1 normal arithmetic operation.

Outputs the operation result that reports the operation exception state, but does not report the operation exception state when performing a comparison operation between operands, and inverts and outputs the operation result when the operation exception occurs. It is equipped with a fixed-point addition/subtraction circuit, and a judgment circuit to which the calculation result of the fixed-point addition/subtraction circuit is input in the case of the above-mentioned comparison operation, and which judges whether the calculation result is positive, negative, or zero. Comparison operations between operands are performed based on the results.

(Example) The present invention will be explained below with reference to Examples.

FIG. 1 is a diagram for explaining a comparison operation between operands of an arithmetic device according to the present invention, and FIGS. 2 and 3 are diagrams showing a fixed-point addition/subtraction circuit and a fixed-point addition/subtraction circuit, respectively.

FIG. 2 is a block diagram showing a negative and zero determination circuit.

With reference to FIGS. 1 to 3, the first operand Ai and the second operand Bi stored in vector register 1
(7t, i=l, 2, 3, . . . , n) is input to the fixed-point adder/subtracter 2. The first operand A1 and the second operand Bi are fixed point adders and subtracters 2, respectively.
is held in the first operand holding register 21 and second operand holding register 22.

When performing normal operations (operations other than comparison operations, such as subtraction), a normal operation mode signal 201 for reporting an operation exception state is input to the operation circuit 23 and the operation exception detection circuit 24. The arithmetic circuit 23 is the first operand holding register 2
The first operand Ai and the second operand Bi' (j) are input from the first and second operand holding renostars 22, respectively, and a normal operation (subtraction) is performed.The operation result (output) of the operation circuit 23 is output by the operation exception detection circuit 24. is monitored, and when an arithmetic exception state occurs, the host unit (not shown) reports the K arithmetic exception state.In the case of normal arithmetic operations, the selection circuit 26 always uses the signal line in response to a command from the arithmetic exception detection circuit 24. 203 is selected, and the operation result of the arithmetic circuit 23 is stored in the output storage register 27. In addition, when an operation exception state does not occur, the operation exception state is not reported and the operation result is stored in the output storage register 27. The operation result stored in the output storage register 27 is stored in the vector register 1 via the selection circuit 11 (portion C1), after which it is further processed or output to an output device (not shown). Ru.

When performing a comparison operation between operands Ai and 81, vector register 1 to first operand Ai and second operand B are transferred to first operand holding register 21 and second operand holding register of fixed-point adder/subtractor 2, respectively. It is held at 22. An arithmetic mode signal 202 indicating subtraction that suppresses (does not perform) reporting of an arithmetic exception state is input from the input device 4 to the arithmetic circuit 23 and the arithmetic exception detection circuit 24 .

The arithmetic circuit 23 inputs the land held by the first operand Ai and the second operand Bi from the land holding register 22 into the first operand holding register 21 and the second operand holding register 21, respectively, and Ai+Bi.
Perform the calculation indicated by +1 and output the calculation result.

The arithmetic exception detection circuit 24 receives the arithmetic result through the signal line 203 and detects an arithmetic exception state.

On the other hand, the calculation result of the calculation circuit 23 is input to the inversion circuit 25 and inverted by 2 (hereinafter referred to as the inversion calculation result).

It is output to the signal line 204.

When the arithmetic mode signal 202 indicates subtraction that suppresses arithmetic exception state reporting, when the arithmetic exception detection circuit 24 detects an arithmetic exception state, a logic "1"i is sent to the signal line 205 without reporting to the upper unit. Output. When logic "1" is input to the selection circuit 26, the 2 selection circuit 26 selects the signal line 204 and stores the 2 inversion operation result in the output holding register 27. On the other hand, when the arithmetic exception detection circuit 24 does not detect an arithmetic exception state, that is, when there is no arithmetic exception state, a logic pass 0# is output to the signal line 205, and the selection circuit 26 selects the signal line 203. Then, the calculation result is held in the output holding register 27.

Note that in the subtraction instruction that suppresses operation exception status reporting,
When an operation exception occurs during fixed-point addition or subtraction, the sign of the operation result is always inverted. For example, if the sign is a logic "1" and the numerical part is all logic "0" and an operation exception occurs, if only the sign is inverted, both the sign and the numerical part become logic "0", resulting in two The result is the same as when the two lands are equal.Therefore, it is necessary to invert the sign and numerical part of the operation result.

The operation result or the inversion operation result held in the output holding register 27 is sent to the vector level vector C by the selection circuit 11.
1 (hereinafter referred to as operation result C).

Thereafter, this calculation result C is input to the positive/negative/zero determination circuit 3.

As shown in FIG. 3, this calculation result Ci is input to a comparison circuit 32 via an input register 31.

Further, 0 (zero) is input to this comparison circuit 32.

A comparison operation is performed between the operation result ci and zero according to the comparison conditions shown in FIG. That is, as shown in FIG. 4, for 2, for example, the comparison condition C, >0, the detection condition is that the sign of the calculation result C1 is O (zero) and the numerical part is not a number (
At least one bit must be 1). Then, the detection condition corresponding to each comparison condition is detected, and the result is stored in the bit position of the result storage register 34 designated by the write address control circuit 33.

In this way, a comparison operation between the first operand Ai and the second operand B is performed.

(Effects of the Invention) As is clear from the above description, according to the arithmetic device of the present invention, comparison operations between operands are performed using the fixed-point addition/subtraction circuit and the sign/minus/zero determination circuit included in the arithmetic device. This has the effect of reducing the amount of hardware compared to conventional arithmetic devices. It also has the advantage that comparison operations are easier than conventional arithmetic devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main part of an embodiment of the present invention, FIG. 2 is a block diagram showing the fixed-point addition/subtraction circuit shown in FIG. 1, and FIG. 3 is a block diagram showing the positive/negative zero determination circuit shown in FIG. 1. figure,
FIG. 4 is a diagram showing the comparison conditions and detection conditions of the positive/negative zero determination circuit, and FIG. 5 is a diagram showing a dedicated circuit for comparison calculation used in a conventional calculation device. DESCRIPTION OF SYMBOLS 1... Vector register, 2... Fixed-point addition/subtraction circuit, 3... Positive/negative zero determination circuit, 4... Input device, 1
DESCRIPTION OF SYMBOLS 1... Selection circuit, 21... First operand holding register, 22... Second operand holding register, 2
3... Arithmetic circuit, 24... Arithmetic exception detection circuit, 25
... Inversion circuit, 26 ... Selection circuit, 27 ... Output holding register, 31 ... Input register, 32 ... Comparison circuit, 33 ... Write address control circuit, 34 ...
Output register. 51.52...Input register, 53.54...Arithmetic circuit, 55.56...Output register. Figure 1 Figure 2 Figure 3 i Figure 4 A B x y (A>B) (A=B)

Claims (1)

[Claims] 1. In an arithmetic unit equipped with the function of performing a comparison operation between operands, in the case of a normal operation, an operation result that reports an operation exception state is output, whereas in the case of a comparison operation, an operation result that reports an operation exception state is output. A fixed-point addition/subtraction circuit that inverts and outputs the operation result if the operation result is not reported and an operation exception state occurs, and in the case of the comparison operation, the operation result of the fixed-point addition/subtraction circuit is input and 1. An arithmetic device comprising: a determination circuit that determines whether the operand is positive, negative, or zero; and a comparison operation between operands is performed based on the determination result of the determination circuit.