JPS61290184A - Electric controller for door open-close system for car - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a vehicle door opening/closing system, and particularly to a vehicle door opening/closing system that can be opened and closed laterally along the entrance/exit of a vehicle such as a wagon or a bus. The present invention relates to an electric control device for a vehicle opening/closing system in which opening/closing of a door provided therein is controlled by a rotating electric motor.

[Prior art]

Conventionally, in an electric control device for this type of vehicle door opening/closing system, a resistor is connected in series with a rotary electric motor to control the rotation of the rotary electric motor, as disclosed in Japanese Patent Laid-Open No. 58-69980, for example. When the rotational speed falls below the allowable lower limit value, the resistor is short-circuited and the voltage applied to the rotary motor is increased by the amount corresponding to the resistor short-circuit, thereby preventing an unnecessary decrease in the rotational speed of the rotary motor. There is an attempt to maintain the time required for closing or opening the door within a substantially constant range without causing any damage.

[Problem that the invention seeks to solve]

However, in such a configuration, when the load on the rotary motor is light, the rotational speed of the rotary motor increases too much during the door closing or opening process, causing the door closing speed or opening speed to increase too much. On the other hand, when the load on the rotary motor is heavy, there is a problem that the rotational speed of the rotary motor decreases too much during the closing/opening process of the door, and the closing/opening speed becomes too low. Moreover, such a problem was even more serious because the above-mentioned allowable lower limit value remained unchanged.

In order to cope with this problem, the present invention determines the upper and lower limits of the allowable rotational speed range of a rotary electric motor in a vehicle door opening/closing system based on the rotational speed after a predetermined period of time has passed after the rotary electric motor is started. It is an object of the present invention to provide an electric control device that does the following.

[Means for solving problems]

In solving this problem, the structural features of the present invention are as follows:
It is commonly used in door opening/closing systems equipped with a rotary electric motor that opens and closes the door by rotating in one direction and closing it by rotating in the other direction.
an operating means that generates a first operating signal when opening the door and a second operating signal when closing the door; and operating means that enters a first driving state in response to the first operating signal and rotates the rotary electric motor in one direction. The rotating electric motor is supplied from the power source via the resistor to the rotary electric motor so as to allow power to be supplied from the power source via the resistor to the rotary electric motor, and to enter a second drive state in response to the second operation signal and rotate the rotary electric motor in the other direction. a driving means for allowing power to be supplied to the rotary motor; a speed detecting means for detecting the rotational speed of the rotary motor and generating a speed detection signal; and a shorting means for selectively shorting the resistor in accordance with the value of the speed detection signal. In the electric control device comprising: the first (
or (2) a timer signal generating means for generating a timer signal when a predetermined period of time has elapsed after the generation of the operation signal; determining means that determines whether the detection signal is large (or small) depending on the value of the detection signal and generates an upper limit signal and a lower limit signal, respectively; output signal generating means for generating an output signal when the speed detection signal becomes smaller than the value of the lower limit value signal, and extinguishing the output signal when the value of the speed detection signal becomes smaller than the value of the lower limit signal; 1 (or a second) drive state, and in response to the disappearance of the output signal, the first drive state of the drive means is
(or second) control means for controlling to permit return to the (or second) driving state (or return and short-circuiting of the resistor by the short-circuiting means).

[Effect]

By configuring the present invention in this way, when the vehicle is stopped tilting in the opening/closing direction of the door, when opening and closing the door, the own weight of the door is applied during the opening and closing processes. Even if the load on the rotary electric motor is reduced in one of the opening and closing processes, and the load on the rotary electric motor is increased in the other of the opening process and the closing process, after the first (or second) operation signal is generated. The values of the upper limit signal and the lower limit signal generated by the determining means in response to the timer signal order from the timer signal generating means are determined to be the values of the speed detection signal, that is, the rotary motor at the time when the timer signal is generated. The higher (or lower) the rotational speed based on the load of the rotary motor, the larger (or smaller) it is determined, and the generation timing and extinction timing of the output signal from the output signal generating means are determined according to the rotational speed according to the load of the rotary motor. It is determined by the time when the value of the speed detection signal reaches the value of the upper limit value signal and the value of the lower limit value signal based on the increase and decrease, and the control means controls the first drive means by the generation of the output signal. (or a second) drive state is eliminated to reduce the rotational speed of the rotary electric motor, and the rotary motor is returned to the first (or second) drive condition by the disappearance of the output signal, or this return is performed. At the same time, the resistor is short-circuited by the short-circuiting means to increase the rotational speed of the rotary motor, so that the rotational speed of the rotary motor is determined to be low (or high) depending on the magnitude (or small) of the load. As a result, the opening speed (i.e., opening time) and closing speed (i.e., closing time) of the door are always maintained within the speed range, and the accuracy is always maintained regardless of the load fluctuation of the rotary motor. Can be kept constant.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
2 and 2 show an example in which the electric control device according to the present invention is applied to the opening/closing mechanism 20 of the bus layer 10, and the door 1
0 is disposed at an entrance provided on the side wall of the bus so that it can be opened and closed in the front and rear directions along the entrance. Opening/closing mechanism 2
0 is equipped with a stepped drive shaft 21 that is vertically installed on a part of the floor surface of the bus, and this drive shaft 21 has a support arm that extends horizontally from a part of the inner wall of the bus. 22 and a portion of the floor surface so as to be rotatable in the horizontal direction. A pair of upper and lower connecting arms 21a, 21a extending horizontally from the large diameter portion of the drive shaft 21 have a diameter of 5ii10 at each tip.
The door 10 is connected to the inner wall portion of the drive shaft 21 so as to be rotatable relative to the inner wall portion in the horizontal direction, so that when the drive shaft 21 rotates counterclockwise in FIG. When the drive shaft 21 rotates clockwise in this state, the door 10 opens toward the rear of the bus (toward the left in FIG. 2) due to the action of the connecting arms 21a, 21a accompanying the rotation of the bus. , 21a closes toward the front of the bus (toward the right in FIG. 2). Also,
The opening/closing mechanism 20 includes a large-diameter spur gear 23 pivotally supported at the lower end of the large-diameter drive shaft 210, and a small-diameter spur gear 24 that meshes with the spur gear 23. It is integrally supported by the output shaft of a DC motor M mounted on the surface. In addition, when the door 10 is fully opened (or fully closed), the door 10 is in the fully open state (
or fully closed).

Further, forward rotation (or reverse rotation) of the DC motor M corresponds to opening (or closing) of the door 10.

As shown in FIG. 1, the electric control device includes an operation switch 3
0, fully open detection switch 40a, fully closed detection switch 4
0b, auxiliary detection switch 40c, and operation switch 30
The bus has relays 50, 60, and 70 connected to the bus, and the operation switch 30 is located near the driver's seat of the bus.
It includes a double-throw contact 31 connected to the positive terminal of the DC power supply B via the ignition switch IG of the bus, and a pair of fixed contacts 32 and 33. However, operation switch 3
0 generates a first operation signal at a high level necessary for opening the door 10 in response to the connection of the double-throw contact 31 with the fixed contact 32, and connects the double-throw contact 31 with the fixed contact 33. In response to this, a second operating signal necessary for closing slo is generated at a high level, and both fixed contacts 32 and 33 of the double-throw contact 31 are
In the neutral state, the generation of the first and second operation signals is stopped.

The fully open detection switch 40a is of a normally closed type, and is opened only when the door 10 is fully opened to generate a fully open detection signal at a high level. The fully open detection switch 40b is a normally closed type, and the switch 40b is a normally closed type.
It is opened only when 10 is fully open and generates a fully closed detection signal at a high level. The auxiliary detection switch 40c is of a normally open type, and is closed when the door 10 is closed to the position immediately before fully closed, and generates a completely closed position detection signal at a low level.

The relay 50 has an electromagnetic coil 51 and a double-throw switch 52, and the double-throw switch 52 connects the double-throw contact 52a to the fixed contact 52 by excitation (or demagnetization) of the electromagnetic coil 51.
b (or 52C).

In this case, the double-throw contact 52a is connected to the first input terminal of the DC motor M, the fixed contact 52b is connected to the positive terminal of the DC power supply B, and the -blade fixed contact 52c is grounded.

The relay 60 has an electromagnetic coil 61 and a double-throw switch 62, and the double-throw switch 62 changes the double-throw contact 62a to the fixed contact 62b by excitation (or demagnetization) of the electromagnetic coil 61.
(or 62C).

In such a case, the double-throw contact 62a is connected to the second input terminal of the DC motor M via the load resistor 80, and the fixed contact 62a is connected to the second input terminal of the DC motor M through the load resistor 80.
2b is connected to the positive side terminal of DC power supply B, and -blade fixed contact 62C is grounded. The relay 70 includes an electromagnetic coil 7
2, and a normally open switch 72 that is closed (or opened) by excitation (or demagnetization) of the electromagnetic coil 72, and the switch 72 is connected in parallel to a load resistor 80.

Further, as shown in FIG.
00a, 100b), and the negative AND gate 100a has its first inverting input terminal connected to the fixed contact 32 of the operating switch 30 through the inverter 90'a.
The second inverting input terminal thereof is connected to ground via a fully open detection switch 40a. Therefore, the negative AND gate 100a receives the first signal from the operation switch 30.
A low level signal (or high level signal) is generated in response to disappearance (or generation) of the full open detection signal from the full open detection switch 40a under the inverting action of the inverter 90a in response to the generation of the operation signal. Further, when the first operation signal from the operation switch 30 disappears, the negative AND gate 1oOa generates a high level signal.

The negative AND gate 100b has a first inverting input terminal connected to the fixed contact 33 of the operation switch 30 via an inverter 90b, and a second inverting input terminal of the negative AND gate 100b is connected to the fully closed detection switch 4.
It is grounded via 0b. However, negative AN
The D gate 100b generates a low level signal in response to the disappearance (or generation) of the full open detection signal from the full open detection switch 40b under the inverting action of the inverter 90b in response to the generation of the second operating signal from the operating switch 30. (or a high level signal). Furthermore, when the second operation signal from the operation switch 30 disappears, the negative AND gate 10
0b produces a high level signal.

Further, the electric control device includes a negative NAND gate 11
0 (negative logic AND gate 110), a pair of inverters 120a and 120b, and a pair of negative NAND
The negative NAND gate 110 has a first inverting input terminal connected to the output terminal of the negative AND gate 100b.
Its second inverting input terminal is grounded via an auxiliary detection switch 40c. Thus, the negative NAND gate 110 generates a high level signal in response to the disappearance (or generation) of the immediately before fully closed position detection signal from the auxiliary detection switch 40:c while the negative AND gate 100b is generating the low level signal. (or low level signal). In addition, the negative NAND gate 110 is a negative
A high level signal is generated in response to a high level signal from D gate 100b.

Negative NAND gate 130a is connected at its first inverting input terminal to the output terminal of negative AND gate 100a;
The second inverting input terminal of a is grounded through the inverter 120a and the fully closed detection switch 40b. Therefore, the negative NAND gate t3oa receives the inverting action of the inverter 120a in response to the generation (or disappearance) of the fully closed detection signal from the fully closed detection switch 40b after the generation of the low level signal from the negative AND gate 100a. Generates a high level signal (or low level signal). Further, NAND gate 130a generates a low level signal in response to a high level signal from negative AND gate 100a.

The negative NAND gate 130b is connected at its first inverting input terminal to the output terminal of the negative AND gate 100b.
The second inverting input terminal of the switch b is grounded through the inverter 120b and the full-open detection switch 40a. Therefore, the negative NAND gate 130b receives the inverting action of the inverter 120b in response to the generation (or disappearance) of the fully open detection signal from the fully closed detection switch 40a after the generation of the low level signal from the negative AND gate 100b. Generates a high level signal (or low level signal). Further, NAND gate 130b generates a low level signal in response to a high level signal from negative AND gate 100b. The monostable multivibrator 140a generates a timer signal at a high level in response to the high level signal from the negative NAND game 130a, and the stable multivibrator 1-40b generates a negative NAND signal.
High in response to a high level signal from gate l30b;
Generates a timer signal at the level.

In such a case, both vehicle stability multi-by-breaks 140a, 1
The generation time of each timer signal from 40b corresponds to the initial opening operation of the door 10 and the time required for the initial opening operation, respectively.

The timer circuit 160 receives the first (or second) operation signal from the operation switch 30 through the OR gate 150, measures the elapsed time after the generation of the same operation signal, and when this measured value reaches a predetermined elapsed time To. Generates a timer signal at high level. In this case, the predetermined elapsed time value To corresponds to the initial rotational speed increase time of the DC motor M that starts when the first (or second) operation signal is generated. Speed sensor 170 detects the rotational speed N of DC motor M and generates a series of pulse signals having a frequency proportional to this. A frequency-voltage converter 180 (hereinafter referred to as F-V converter 180) converts the frequency of each pulse signal from the speed sensor 170 into a speed voltage at a level proportional to the frequency. In such a case, the level of the speed voltage from the F-V converter 180 corresponds to the rotational speed N of the DC motor M.

The sample and hold circuit 190 is shown in FIG.
It has a normally open type analog switch 191, and as shown in FIGS. 1 and 3, this analog switch 191 has an input terminal 191a connected to the output terminal of the F-V converter 180, and controls the It is connected to the output terminal of the timer circuit 160 at a terminal 191b. Thus, the analog switch 191 closes in response to the timer signal from the timer circuit 160, and the speed voltage from the F-V converter 180 is generated from the output terminal 191C. The field effect transistor 193 has its gate terminal connected to the output terminal 191C of the analog switch 191 via a capacitor 192, the drain terminal of this transistor 193 is grounded via a resistor 194, and the source terminal of the transistor 193 is It is connected to the DC power supply in order to receive the power supply voltage +Vcc from the DC power supply. Thus, transistor 193 holds the speed voltage from analog switch 191 in cooperation with capacitor 192, and generates a hold voltage from its drain terminal.

As shown in FIGS. 1 and 4, the load region determining circuit 200 includes a voltage divider 201 and a comparator 202.2 connected to the voltage divider 201 and the sample-and-hold circuit 190.
03 and the AN connected to both comparators 203 and 204.
D gates 205 and 206. The voltage divider 201 includes resistors 201a and 20 connected in series with each other.
1b and 201c, this voltage divider 201 connects the power supply voltage +Vcc from the DC power source to three resistors 2018.
．． Voltage is divided by 201b and 201C, and both resistors 201a
, 201b and a common terminal of both resistors 201b and 201c, first and second divided voltages are generated, respectively. In such a case, the resistors 201a, 201b, 201c are connected so that the first and second divided voltages from the voltage divider 201 correspond to the upper limit rotational speed in the heavy load region and the upper limit rotational speed in the medium load region, respectively. The resistance value is specified.

The comparator 202 compares the hold voltage from the sample and hold circuit 190 with the first divided voltage from the voltage divider 201, and when the hold voltage is lower (or higher) than the first divided voltage, a high level signal (or low level signal). This means that the comparator 202
This means that the high level signal is generated as the first determination signal representing the heavy load region of the DC motor M (N<the upper limit of the rotational speed in the heavy load region). The comparator 203 is
The hold voltage from the sample and hold circuit 190 is compared with the first divided voltage from the voltage divider 201, and when the hold voltage is higher (or lower) than the first divided voltage, a high level signal (or low level signal) is generated. occurs. The comparator 204 compares the hold voltage from the sample and hold circuit 190 with the second divided voltage from the voltage divider 201, and when the hold voltage is higher (or lower) than the second divided voltage, a high level signal (or low level signal).

The AND gate 205 has a non-inverting input terminal connected to the output terminal of the comparator 203, and an inverting input terminal of the AND gate 205 is connected to the output terminal of the comparator 204. Thus, the AND gate 205 generates a high level signal in response to the high level signal from the comparator 203 and the low level signal from the comparator 204, and passes this high level signal to the comparator 204.
It is made to disappear in response to a high level signal from the comparator 203 or a low level signal from the comparator 203. This means that AN
This means that the D gate 205 generates a high level signal as a second determination signal representing the medium load region of the DC motor M (the heavy load region rotational speed upper limit value<N<the medium load region rotational speed upper limit value). . AND gate 206 generates a high level signal in response to each high level signal from both comparators 203 and 204, and converts this high level signal into
It disappears in response to a low level signal from comparator 203 (or 204). This means that AND gate 2
06 means that a high level signal is generated as the third determination signal representing the light load region of the DC motor M (the upper limit of rotational speed in the medium load region <N).

The speed determination circuit 210 includes a voltage divider 2 connected to the load area determination circuit 200, as shown in FIGS. 1, 4, and 5.
10a, this voltage divider 210a and F-V converter 180
Comparators 210b, 210c, 210d connected to
and 210e. Voltage divider 210
a has transistors 211, 212, and 213, and the base of the transistor 211 is connected to the output terminal of the comparator 202 via a resistor 211a (
(See Figures 4 and 5). Further, the transistor 211 is
Its emitter is grounded, and its collector is connected to the positive terminal of a DC power source (not shown) through resistors 214, 217, 218, and 219 connected in series. Therefore, the transistor 211 is connected to the comparator 2
It becomes conductive (or non-conductive) in response to the generation (or disappearance) of the first determination signal from 02.

The transistor 212 has its base connected to the output terminal of the AND gate 205 via a resistor 212a.
The emitter of this transistor 212 is grounded, while the collector of this transistor 212 is connected to the positive terminal of the DC power supply through resistors 216, 217, 218, and 219 connected in series with each other. Thus, transistor 212 becomes conductive (or non-conductive) in response to the generation (or disappearance) of the second decision signal from AND gate 205. Transistor 213 has a resistor 213 at its base.
The emitter of this transistor 213 is grounded, and the collector of this transistor 213 is connected to the output terminal of the AND gate 206 through a resistor 216, 217, 218, and 219 connected in series with each other. Connected to the positive terminal. Thus, transistor 213 becomes conductive (or non-conductive) in response to the generation (or disappearance) of the third decision signal from AND gate 206.

Moreover, each series resistor 214, 217, 218, 219 is
Under conduction of the transistor 21.1, the power supply voltage +Vcc from the DC power supply is divided, and each of these divided voltages is converted into a first voltage.
．． Each output terminal Pi serves as the second and third heavy load reference voltage.
, P2 and P3 (see FIG. 5), respectively.

Each series resistor 215, 217, 218, 219 divides the supply voltage +Vcc from the DC power supply while the transistor 212 is conductive, and divides each of these divided voltages into the first . Second and third medium load reference voltages are generated from respective output terminals P1, P2 and P3 (see FIG. 5), respectively. Further, each series resistor 216, 217, 218, 219 divides the power supply voltage +Vcc from the DC power supply while the transistor 213 is conductive, and converts each of these divided voltages into the first . Second and third light load reference voltages are generated from respective output terminals Pi, P2 and P3 (see FIG. 5), respectively.

In such a case, the first . 2nd and 3rd
The heavy load reference voltage corresponds to a rotation speed lower limit value NIH, a rotation speed intermediate value N2H, and a rotation speed upper limit value N3H in the heavy load region of the DC motor M, respectively. Further, the first, second and third medium load reference voltages from the voltage divider 210a are the lower limit value N of the rotational speed in the medium load region of the DC motor M.
IM, rotation speed intermediate value N2M and rotation speed upper limit value N3M
correspond to each. Furthermore, the first . The second and third light load reference voltages correspond to a rotational speed lower limit value NIL, a rotational speed intermediate value N2L, and a rotational speed upper limit value N3L in the light load region of the DC motor M, respectively. However, the resistance value of the resistor 214, the resistance value of the resistor 215, and the resistance value of the resistor 216 are obtained, and NIH<NI
M<NIL.

N2H<N2M<N2L, N3H<N3M<N3L.

Comparator 210b goes high only when the speed voltage from F-V converter 180 is lower than the first heavy load reference voltage, first medium load reference voltage or first light load reference voltage from output terminal P1 of voltage divider 210a. The comparator 210C generates a level signal, and the comparator 210C determines that the speed voltage from the F-V converter 180 is a second heavy load reference voltage, a second medium load reference voltage, or a second light load reference voltage from the output terminal P2 of the voltage divider 210a. The comparator 210d generates a high level signal only when the speed voltage from the F-V converter 180 is higher than the second heavy load reference voltage from the output terminal P2 of the voltage divider 210a,
Generates a high level signal only when lower than the second medium load reference voltage or the second light load reference voltage, and comparator 2
10e is a high level only when the speed voltage from the F-■ converter 180 is higher than the third heavy load reference voltage, third medium load reference voltage, or third light load reference voltage from the output terminal P3 of the voltage divider 210a. Generate a signal.

As shown in FIGS. 1, 4, and 6, the timer circuit 22.0 includes a load area determining circuit 200 and a speed determining circuit 21.
0 and positive NOR gate 280, this timer circuit 200 is connected between the speed determination circuit 21
0 and the load area determination circuit 20
voltage divider 220b connected to 0, comparator 220C connected to integrator 220a and voltage divider 220b, and A connected to speed discrimination circuit 210 and comparator 220C.
ND gate 220d.

The integrator 220a receives a high level signal from the comparator 210e through the buffer 221, integrates the generation time of this high level signal using a resistor 222 and a comparator 223, and generates an integral signal.

Voltage divider 220b includes transistors 224, 225.22
6, and the transistor 224 has its base connected to the output terminal of the comparator 202 via a resistor 224a. The transistor 224 is grounded at its emitter, and both resistors 227 and 22 at its collector.
9a and is connected to the positive terminal of the DC power supply.

Thus, the transistor 224 is turned on (or turned on) in response to the generation (or disappearance) of the first decision signal from the comparator 202.
or non-conducting). The transistor 225 has its base connected to the output terminal of the AND gate 205 through a resistor 225a, the emitter of this transistor 225 is grounded, and the collector of this transistor 225 is connected to the DC power supply through both resistors 228 and 229a. Connected to the positive terminal. Therefore, the transistor 225 is A
It becomes conductive (or non-conductive) in response to the generation (or disappearance) of the second determination signal from the ND gate 205.

The transistor 226 has its base connected to the output terminal of the AND gate 206 via a resistor 226a.
The emitter of this transistor 226 is grounded, while the collector of this transistor 226 is connected to both resistors 229 and 22.
9a and is connected to the positive terminal of the DC power supply.

Thus, transistor 226 becomes conductive (or conductive) in response to the generation (or disappearance) of the third decision signal from AND gate 206.
or non-conduction). Each series resistor 227.2293 is
When the transistor 224 is conductive, the power supply voltage +Vcc from the DC power supply is divided and output as a first divided voltage to the output terminal d.
(See Figure 6).

Each series resistor 22B, 229a divides the power supply voltage Vcc from the DC power supply under conduction of the transistor 225, and generates a second divided voltage from the output terminal d. Under conduction, the power supply voltage +Vcc from the DC power supply is divided and generated from the output terminal d as a third divided voltage. In this case, the resistance values of the resistors 227, 228, and 229 are determined to be successively smaller so that the first divided voltage>the second divided voltage>the third divided voltage.

The comparator 220c is the first one of the voltage dividers 220b.
When the second or third divided voltage is higher (or lower) than the level of the integrated signal from the integrator 220a, a high level signal (or low level signal) is generated. AND game 1-2
20d generates a high level signal (or a low level signal) in response to both high level signals (or one of each low level signal) from both comparators 210e and 220c. This means that the AND game 220d generates the high level signal as a timer signal.

In this case, the generation time of the timer signal from the AND gate 22od becomes sequentially shorter as the first to third divided voltages are generated from the voltage divider 220b.

As shown in FIGS. 1 and 5, the RS flip-flop 230 has its set terminal S connected to the output terminal of the comparator 210e of the speed discrimination circuit 200, and its reset terminal R connected to the output terminal of the comparator 210d. It is connected to the.

Thus, RS flip-flop 230 is set in response to a high level signal from comparator 210e and generates a low level signal from its output terminal Q through buffer 231, and also in response to a high level signal from comparator 210d. is reset and a high level signal is generated from its output terminal Q through the buffer 231. RS flip-flop 240 has its set terminal S connected to the output terminal from comparator 210C, and the reset terminal R of RS flip-flop 240 is connected to the output terminal of comparator 210b. Therefore, the RS flip-flop 7 240 is connected to the comparator 210C.
It is reset in response to a high level signal from the comparator 210b to generate a low level signal from its output terminal Q, and is reset in response to a high level signal from the comparator 210b to generate a high level signal from its output terminal Q. .

The negative NAND gate 260 has a first inverting input terminal as shown in FIG. This negative NAND gate 2
The second inverting input terminal of 60 is an RS flip-flop 230
is connected to output terminal Q of. The OR gate 250 generates a high level signal (in response to the high level signal from the negative NAND gate 110 and the occurrence of one of each timer signal (or the disappearance of all three signals) from the vehicle stability multi-bye breaks 140a, 140b. or low level signal).

Negative NAND gate 260 is OR gate 250
and generates a low level signal in response to at least one of both high level signals from the OR gate 250 and the RS flip-flop 230, and generates a high level signal in response to the double-level signals from the OR gate 250 and the RS flip-flop 230. .

Negative AND gate 270a generates a high level signal in response to at least one of the high level signals from negative AND gate 100a and negative NAND gate 260, and generates a high level signal in response to each low level signal from negative AND gate 100a and negative NAND gate 260. Generates a low level signal in response. This means that the electromagnetic coil 51 of the relay 50 is energized (or demagnetized) in response to the low level signal (or high level signal) from the negative AND gate 270a. Negative AND game) 270b is negative AND game)
D gate 100b and negative NAND gate 260
generates a high level signal in response to at least one of the high level signals from the negative AND gate 1oo;
A low level signal is generated in response to each low level signal from the negative NAND gate 260 and the negative NAND gate 260. This means that the electromagnetic coil 61 of the relay 60 is a negative AND
270b (also a high level signal from the RS flip-flop 240 and the OR gate 2)
A low level signal (or high level signal) is generated in response to the occurrence of one of the high level signals from 50 (or the disappearance of these three signals). This means that the electromagnetic coil 71 of the relay 70 is excited (or excited) in response to the low level signal (or high level signal) from the positive NOR gate 280.
or demagnetized).

In this embodiment configured as described above, the bus running with the ignition switch IG closed is traveling on a running road surface corresponding to the medium load region of the DC motor M (for example, a relatively flat running road surface). ) is assumed to have stopped at the top. However, in this state, since the door 10 is in the fully closed state, the fully closed detection switch 40b generates a fully closed detection signal, and the auxiliary detection switch 40c generates a fully closed position detection signal. On the other hand, each operation signal from the operation switch 30 and the full-open detection signal from the full-open detection switch 40a have disappeared. Further, the speed voltage generated from the F-V converter 180 in cooperation with the speed sensor 170 is applied to the DC motor M.
It becomes zero based on the stoppage of .

In such a state, the operation switch 3 is pressed to open the door 10.
0 to the first operation signal (symbol a in Fig. 7).
), the negative AND gate 100
When the full-open detection signal from the full-open detection switch 40a disappears, the signal a generates a low level signal under the inverting action of the inverter 90a in response to the first operation signal from the operation switch 30, and the negative NAND gate 130a Under the inverting action of the inverter 120a in response to the fully closed detection signal from the fully closed detection switch 40b, a high level signal is generated in response to the low level signal from the negative AND gate 100a, and a timer signal is generated from the monostable multi-bi break 140a. to occur.

Further, the RS flip-flop 230 is connected to the operation switch 30.
is set by an OR gate 150 responsive to a first operation signal from the negative NA to generate a high level signal.
ND gate 260 is monostable multivibrator 140a
The negative AND gate 270a generates a high level signal in response to the high level signal from the RS flip-flop 230 under the action of the OR gate 250 responsive to the timer signal from the negative AND gate 100.
A low level signal is generated in response to the low level signal from the negative NAND gate 260 and the low level signal from the negative NAND gate 260. Also, the positive NOR gate 280 is connected to the OR gate 250 from the monostable multi-bibreak 140a.
It receives the timer signal through the circuit and generates a low level signal.

Further, the timer circuit 160 is connected to the OR from the operation switch 30.
A first operation signal is received through the game controller 150, and the elapsed time after the first operation signal is generated is measured and recorded.

Then, the relay 50 connects to the negative AND gate 270a.
The double-throw contact 52a of the double-throw switch 52 is closed to the fixed contact 52b by excitation of the electromagnetic coil 51 in response to a low level signal from the double-throw switch 52 (see reference numeral b1 in FIG. 7). In addition, the relay 70 closes the switch 72 and short-circuits the load resistor 80 by excitation and magnetization of the electromagnetic coil 71 (see reference numeral C1 in FIG. 7) in response to a low level signal from the positive NOR signal 280. At this time, the relay 60 is negative A
Under the high level signal from the ND gate 270b, the first
It is in the state shown in the figure. Therefore, the power supply current from the DC power supply B is transmitted to the fixed contact 52b and the double-throw contact 52a of the relay 50.
The current flows into the DC morph M from its first input terminal, flows out from the second input terminal of the DC motor M, passes through the switch 72 and the double-throw contact 62a of the relay 60, and flows into the fixed contact 62c. In other words, when the DC motor M directly receives the power supply voltage from the DC power supply B with the load resistor 80 short-circuited, the normal rotation speed starts to increase along the curve d1 in FIG. Then, the spur gear 23 becomes the spur gear 24 which is interlocked with the DC motor M.
The drive shaft 2 is rotated counterclockwise by the
1 begins to open 5ii10 to the left in FIG. 2 using its connecting arms 21a, 21a against the engagement force with the fully closed locking mechanism.

In the process described above, when a timer signal is generated from the timer circuit 160, the sample and hold circuit 190
The load range determining circuit 200 holds the speed voltage (corresponding to the initial rotational speed value in the medium load range of the DC motor M) generated at the current stage from the F-V converter 180 in cooperation with the speed sensor 170 as a hold voltage. granted to.

Then, in this load region determining circuit 200, the hold voltage from the sample and hold circuit 190 is applied to the voltage divider 2.
01 between the first and second divided voltages, the first decision signal from the comparator 202 and the first decision signal from the comparator 20
Upon each disappearance of the high level signal from 4, the comparator 203 generates a high level signal and the AND gate 205 generates a second decision signal. In addition, AND gate 206
The third decision signal from continues to disappear.

Next, in the speed determination circuit 201, the transistor 212 is connected to the AND game (205) of the load area determination circuit 200.
Each series resistor 215 conducts in response to a second decision signal from
．． 217, 218, 219 are the respective output terminals Pi, P2 . P
3 to 1. A second medium load reference voltage and a third medium load reference voltage are generated, respectively. At this stage, based on the increase in the normal rotation speed of the DC motor M, the speed sensor 170 is output from the F-V converter 180.
The speed voltage generated in cooperation with the speed determination circuit 210
When the voltage becomes higher than the second medium load reference voltage from voltage divider 210a, comparator 210c generates a high level signal and each comparator 210b, 210d, 210
e both generate low level signals.

Then, the RS flip-flop 240 becomes the comparator 2.
A low level signal is generated in response to the high level signal from the monostable multi-bi break 140a, and a high level signal is generated from the positive NOR gate 280 when the timer signal from the monostable multi-bi break 140a is discontinued.
When the electromagnetic coil 71 disappears (see reference numeral c2 in FIG. 7), the switch 72 is opened and the short circuit of the load resistor 80 is released. This means that the DC motor M receives a voltage obtained by subtracting the voltage drop due to the load resistor 80 from the power supply voltage from the DC power supply B, and increases the normal rotation speed along the curve d2 in FIG. . In such a case, as can be understood from the biconvex lines di and d2, the degree of increase in the normal rotation speed of the DC motor M is higher at N2M<N<N3M than at NIM<N<N2M in relation to the load resistance 80. It becomes gradual and becomes saturated. Therefore, the door 10 continues to open while decreasing the degree of increase in the opening speed. In other words, in the medium load region (see symbol ■ in Fig. 7), the rotational speed of the DC motor M is N2M<N.
The upward saturation tendency is maintained within the range of <N3M, and the opening speed of the door 10 is maintained approximately constant.

When the door 10 is fully opened, the fully open detection switch 4a generates a fully open detection signal, the negative AND gate 100a generates a high level signal, and the negative AND gate 27
0a generates a high-level signal, and the relay 50 demagnetizes the electromagnetic coil 51 to close the double-throw contact 52a to the fixed contact 52c, cutting off the DC motor M from the DC power supply B. As a result, the DC motor M stops normal rotation, thereby stopping the opening action of the drive mechanism 20 on the door 10. In this case, door 10
However, due to the inertia due to its opening speed, it easily engages the fully open locking mechanism and is maintained in the fully open state. In addition, after the alo is fully opened in this way, the operation switch 3
Set 0 to neutral state (.

In such a state, the operation switch 3 is pressed to close the door 10.
0, the second operation signal (symbol A in Fig. 7) is generated by the operation.
), the negative AND gate 100
b generates a low level signal under the inversion action of the inverter 90b responsive to the second operation signal when the fully closed detection signal from the fully closed detection switch 40b disappears, and negative NAND gate 130b is the fully open detection switch Under the inverting action of inverter 120b in response to the full-open detection signal from gate 40a, a high level signal is generated in response to the low level signal from negative AND gate 100b, causing monostable multivibrator 140b to generate a timer signal.

Further, the RS flip-flop 230 is connected to the operation switch 30.
The negative NAND gate 260 is set by the OR gate 150 in response to the 211i operation signal from the monostable multi-bi break 14 to generate a low level signal.
The negative AND gate 270b generates a high level signal in response to the low level signal from the RS flip-flop 230 under the action of the OR gate 250 which responds to the signal from the negative AND gate 1.
A low level signal is generated in response to a low level signal from 00b and a low level signal from negative NAND gate 260. Also, positive NOR gate 280
is the OR gate 2 from the monostable multivibrator 140b.
50, it receives a timer signal and generates a low level signal. Further, the timer circuit 160 receives a second operation signal from the operation switch 3o through the OR game 150 and starts counting the elapsed time after the generation of the second operation signal.

Then, the relay 60 connects to the negative AND gate 270b.
The double-throw contact 62a is activated by excitation of the electromagnetic coil 61 in response to a low level signal from the
is applied to the fixed contact 62b, and the relay 70 becomes positive N.
The switch 72 is closed by excitation of the electromagnetic coil 71 (see reference numeral CI in FIG. 7) in response to a low level signal from the OR gate 280, thereby shorting the load resistor 80. At this time, the relay 50 is in the state shown in FIG.

Therefore, the power supply current from the DC power supply B passes through the fixed contact 62b, the double-throw contact 62a of the relay 60, and the switch 72 of the relay 70, and flows into the second input terminal of the DC motor M, and the first input terminal of the DC motor M. It flows out from the terminal, passes through the double-throw contact 52a of the relay 50, and flows into the fixed contact 52c. In other words, when the DC motor M directly receives the power supply voltage from the DC power source B with the load resistor 80 short-circuited, the reverse rotation speed begins to increase along the curve D1 in FIG. Then, the spur gear 23 is rotated clockwise by the spur gear 24 interlocked with the DC motor M, and in response, the drive mechanism 20 uses its connecting arms 21a, 21a to apply an engaging force to the alo with the fully open locking mechanism. It resists and begins to close forward.

In the process described above, when a timer signal is generated from the timer circuit 160, the sample and hold circuit 190 generates a hold voltage in the same manner as described above, and the load area determination circuit 2
00 generates the second decision signal upon disappearance of the first and third decision signals, and the voltage divider 210a of the speed discrimination circuit 210 generates the first decision signal as described above. Second and third medium load reference voltages are generated. At this stage, as the reverse speed of the DC motor M increases, the speed voltage generated from the F-V converter 180 in cooperation with the speed sensor 170 becomes higher than the second medium load reference voltage from the voltage divider 210a. , comparator 210c generates a high level signal, and each comparator 210b, 210d, 210e generates a low level signal.

Then, the RS flip-flop 240 becomes the comparator 2.
In response to the high level signal from 10c, a low level signal is generated, and in response, the positive NOR gate 28
0 generates a high level signal when the timer signal from the monostable multi-by break 140b disappears, and the relay 70 opens the switch 72 by demagnetizing the electromagnetic coil 71 (see symbol C2 in FIG. 7), and the load resistor 80 Release the short circuit.

This means that the DC motor M receives a voltage obtained by subtracting the voltage drop caused by the load resistor 80 from the power supply voltage from the DC power supply B, and increases the reversal speed along the curve D2 in FIG. . In such a case, both drawing lines D1. As understood from D2, in relation to the load resistance 80, the degree of increase in the reverse rotation speed of the DC motor M becomes slower when N2M<N<N3M than when NIM<N<N2M, and is saturated. Therefore, the door 10 continues to close with a reduced increase in its closing speed. In other words, in the medium load region (see symbol ■ in Fig. 7), the rotational speed of the DC motor M is N2M<N<N3.
The upward saturation tendency is maintained within the range of M, and the closing speed of the door 10 is maintained approximately constant.

When the door 10 reaches the position immediately before fully closed and a completely closes position detection signal is generated from the auxiliary detection switch 40c, the negative NAN
D gate 110 generates a high level signal, and positive NOR gate 280 responds to the high level signal.
generates a low level signal under the action of gate 250;
Relay 70 shorts load resistor 80 by closing switch 72. Then, the voltage applied to the DC motor M increases by the amount of the short circuit of the load resistor 80, and the reverse rotation speed of the DC motor M increases, increasing the closing force on the door 10. This means that the door 10 easily engages with the fully closed locking mechanism under the action of the drive mechanism 20 and becomes fully closed.

When alo is fully open in this way, the fully closed detection switch 4
0b generates a fully closed detection signal, negative AND gate 100b generates a low level signal, and negative AND gate 100b generates a low level signal.
Gate 270b generates a high level signal and relay 60
By demagnetizing the electromagnetic coil 61, the double-throw contact 62a is connected to the fixed contact 62c, and the DC motor M is cut off from the DC power supply B. As a result, the DC motor M stops the reverse rotation, thereby stopping the closing action of the drive mechanism 20 on the slo.

In this case, ]jfklO easily engages with the fully closed cane mechanism and is maintained in the fully closed state due to inertia due to its closing speed. Note that after the door 10 is fully opened in this manner, the operation switch 30 is kept in the neutral state.

In addition, in the above explanation of the operation, it is assumed that the bus is stopped on the boarding road surface with its forward direction directed toward the top of the boarding road surface. When the first operation signal is generated from the operation switch 30 to open the door 10 in such a state, the DC motor M starts supplying power from the DC power supply B with the load resistor 80 short-circuited in the same manner as described above. Directly receiving the voltage, the drive mechanism 20 begins to rotate forward, and in response, the drive mechanism 20 begins to open the door 10 against the engagement force with the fully closed lock mechanism. In this case, door 10
The separation from the fully closed cane mechanism is made easier by the rearward weight of 810.

In the above process, when the timer circuit 160 generates a timer signal in the same manner as described above upon completion of time measurement, the sample and hold circuit 190 detects the speed generated by the F-■ converter 180 in cooperation with the speed sensor 1.70. The voltage (corresponding to the initial rotational speed value of the DC motor M in the light load region) is held as a hold voltage and applied to the load region determining circuit 200. Then, this load area determination circuit 2
At 00, the hold voltage from the sample and hold circuit 190 is higher than the second divided voltage from the voltage divider 201, so both comparators 203 and 204 are connected to the comparator 20.
The AND gate 206 generates a third decision signal under the disappearance of the second decision signal from the AND gate 205.

Then, in the speed determination circuit 210, the transistor 213 is connected to the AND gate 206 of the load region determination circuit 200.
Each series resistor 213 conducts in response to a third decision signal from
, 217, 218, 219 are the respective output terminals Pi, P2 . P
3 to 1. Second and third light load reference voltages are generated, respectively. At this stage, the speed voltage generated from the F-V converter 180 in cooperation with the speed sensor 170 based on the increase in the normal rotation speed of the DC motor M is applied to the second light load from the voltage divider 210a of the speed discrimination circuit 210. higher than the reference voltage (when the DC motor M receives a voltage obtained by subtracting the voltage drop due to the load resistor 80 from the power supply voltage from the DC power supply B with the load resistor 80 short-circuited in the same manner as described above). In this case, the rearward weight of the door 10 acts to reduce the load on the DC motor M, so that the normal rotation speed of the DC motor M reaches the curve d3 in FIG. The rising speed increases the opening speed of the door 10.

Based on the increase in the normal rotation speed of the DC motor M, the F-V converter 18
When the speed voltage from 0 is higher than the third light load reference voltage from voltage divider 210a, comparator 210e generates a high level signal, and in response, RS flip-flop 230 generates a low level signal. In the timer circuit 220, the voltage divider 220b generates a third divided voltage under the conduction of the transistor 226 in response to the third determination signal from the AND game 206 of the load area determination circuit 200, and the integrator 220a generates an integral signal when the integration starts in response to the high level signal from the comparator 210e, and the comparator 220c generates a high level signal when the third divided voltage>the level of the integral signal. Then, a timer signal is generated from the negative AND gate 1-220d.

As described above, when a low level signal is generated from the RS flip-flop 230 and a timer signal is generated from the timer circuit 220, the negative NAND gate 260 generates a high level signal in response to the low level signal from the RS flip-flop 230, and the negative AND gate 270a generates a high level signal, while positive NOR gate 280 generates a low level signal in response to the timer signal from timer circuit 220. Then, relay 50
causes the double-throw contact 52a to close to the fixed contact 52c by demagnetizing the electromagnetic coil 51 in response to the high-level signal from the negative AND gate 270a (see reference numeral b2 in FIG. 7), while the relay 70 closes the fixed contact 52c. 2
Energization of electromagnetic coil 71 in response to a low level signal from 80 closes switch 72 to short circuit load resistor 80 .

As a result, when the load resistor 80 is short-circuited, the DC motor M
is directly shorted at both input terminals, resulting in a strong dynamic braking action. As a result, the normal rotation speed of the DC motor M starts to decrease as soon as it reaches the rotation speed upper limit value N3L (as shown by curve d4 in FIG. 7). suppress it.

Next, when the speed voltage from the F-V converter 180 decreases below the second light load reference voltage from the voltage divider 210a after the timer signal from the timer circuit 220 disappears based on the decrease in the normal rotation speed of the DC motor M. , the comparator 210d generates a high level signal, the RS flip-flop 230 generates a high level signal, and the negative NAND gate 26
0 generates a low level signal and negative AND gate 2
70a generates a low level signal, and the relay 50 excites the electromagnetic coil 51 (see reference numeral b3 in FIG. 7) to close the double-throw contact 52a to the fixed contact 52b. Then, the DC motor M stops its dynamic braking operation and receives the power supply voltage from the DC power supply B via the load resistor 80, thereby increasing the normal rotation speed along the curve d5 in FIG. This suppresses a decrease in the opening speed of the door 10. Thereafter, in the same manner, the DC motor M repeats a decrease in the normal rotation speed due to the dynamic braking operation and an increase in the normal rotation speed due to the cancellation of the dynamic braking operation. In other words, the DC motor M operates in its light load region (
7), the opening speed of StO is maintained almost constant while increasing and decreasing the normal rotation speed within the range of N2L≦N≦N3L.

In this case, since N2L>N2M and N3L>N3M, the rotational speed range of the DC motor M during light loads is maintained higher than the rotational speed range during medium loads, and as a result, the opening speed of the door IO is is maintained constant with high accuracy based on a rotational speed range that matches the actual load of the DC motor M. Note that the action when the door IO is fully open is the same as described above.

In such a state, when the second operation signal is generated from the operation switch 30 to close the door 10, the DC motor M is connected to the DC power supply B under the short circuit of the load resistor 80 in the same manner as described above. The drive mechanism 20 begins to close the door 10 forward against the full-open lock mechanism. In such a case, the dissociation of the alo from the fully open locking mechanism is easily accomplished in connection with the short circuit of the load resistor 80, despite the rearward weight of the door IO. Note that the electromagnetic coil 61 of the relay 60 is in an excited state (see reference numeral B2 in FIG. 7).

In the process described above, when the timer 160 generates a timer signal in the same manner as described above upon completion of time measurement, the sample and hold circuit 190 outputs the speed voltage from the F-V converter 180 (the rotation of the DC motor M in the heavy load region). (corresponding to the initial speed value) is held as a hold voltage and applied to the load region determining circuit 200. Then, in this load region determination circuit 200, the sample hold circuit 19
Since the hold voltage from 0 is lower than the first divided voltage from voltage divider 201, comparator 202 generates a second decision signal after each low level signal from both comparators 203, 204.

Then, in the speed determination circuit 210, the transistor 211 is connected to the comparator 202 of the load area determination circuit 200.
Each series resistor 214 conducts in response to a first decision signal from
, 217, 218, and 219 are the respective output terminals P1. P2. P
3 to 1. Second and third heavy load reference voltages are generated, respectively. At this stage, when the speed voltage from the F-V converter 180 becomes higher than the second heavy load reference voltage from the voltage divider 210a of the speed discrimination circuit 210 due to an increase in the reverse speed of the DC motor M, the DC motor M , in the same way as above,
With the short circuit of the load resistor 80 removed, the reversal speed is attempted to be increased while receiving a voltage obtained by subtracting the voltage drop due to the load resistor 80 from the power supply voltage from the DC power supply B. However, since the dead weight acts toward the rear of slo to increase the load on the DC motor M, the reverse speed of the DC motor M decreases along the curve d6 in FIG. When the speed voltage from the F-V converter 180 drops below the first heavy load reference voltage from the voltage divider 210a due to the decrease in the reverse speed of the DC motor M, the comparator 210b generates a high level signal. RSS flip flop 24
generates a high level signal, positive NOR gate 2
80 generates a low level signal, and relay 70 closes switch 72 by energizing its electromagnetic coil 71 (see reference numeral C3 in FIG. 7) to short-circuit load resistor 80.

Then, due to the short circuit of the load resistor 80, the DC motor M directly receives the power supply voltage from the DC power supply B, and resists the weight of the door 10.
The reversal speed is increased along the curve d7 in the figure. This suppresses a decrease in the closing speed of the door 10.

Then, based on the increase in the reverse speed of the DC motor M, the speed voltage from the F-V converter 180 increases to the second voltage from the voltage divider 210a.
When the voltage becomes higher than the heavy load reference voltage, the comparator 210c
generates a high level signal, and the RS flip-flop 24
0 generates a low level signal and inverts the low level signal from the positive NOR gate 280 to a high level signal, and the relay 70 demagnetizes the electromagnetic coil 71 (see symbol C4 in FIG. 7) to open the switch 72 and remove the load. Release the short circuit of resistor 80. Then, the voltage applied to the DC motor M decreases by the voltage drop caused by the load resistor 80, and the reverse rotation speed of the DC motor M decreases along the curve d8 in FIG. Thereafter, in the same manner, the DC motor M repeats an increase in the reverse rotation speed due to the short circuit of the load resistor 80 and a decrease in the reverse rotation speed due to the release of the short circuit.

In other words, the DC motor M increases and decreases its reverse speed in the range of NIH≦N:5N2H in its heavy load region (see symbol ■ in Fig. 7)
The closing rate of O is maintained approximately constant. In such a case, N.I.
Since H<NIM and N2H<N2M, the rotational speed range of DC motor M under heavy load is maintained lower than the rotational speed range under medium load, and as a result, the closing speed of door 10 is The rotational speed is maintained constant with high accuracy based on the rotational speed range that matches the actual load of the DC motor M. Note that the action when alo is fully closed is the same as described above.

Further, in the above-described operation, when the DC motor M is rotating in a medium load region or a heavy load region, the rotation speed of the DC motor M is equal to or lower than the rotation speed upper limit value N3M or N3.
In the explanation above, it is assumed that F-V is not reached during the rotation of the DC motor M under the medium load region.
When the speed voltage from converter 180 is higher than the third medium load reference voltage from voltage divider 210a, comparator 210
e generates a high level signal and RS flip-flop 2
A low level signal is generated from 30. In the timer circuit 220, the voltage divider 220b generates a second divided voltage under the conduction of the transistor 225 in response to the second determination signal from the AND gate 205 of the load area determination circuit 200, and the integrator 220a generates an integral signal in response to the high level signal from the comparator 210e, and the comparator 220c generates a high level signal when the second divided voltage is greater than the level of the integral signal.
Gate 220d generates an instant signal.

Then, the negative AND gate 270a, in cooperation with the negative NAND gate 260 that responds to the low level signals from the RSS flip-flops 230, closes the double-throw contact 52a of the relay 50 to the fixed contact 52c in the same manner as described above, while the positive NOR gate 280 responds to a timer signal from timer circuit 220 to short circuit load resistor 80 via relay 70 in the same manner as described above. This results in
When the load resistor 80 is short-circuited, the DC motor M is directly short-circuited at its re-input terminal, resulting in a strong dynamic braking action. In this case, the generation time of the timer signal from the timer circuit 220 is maintained longer than when the DC motor M is under a light load, so that the effect of reducing the rotational speed of the DC motor M after reaching the rotational speed upper limit value 83H is effective. can be realized very quickly.

In addition, when rotating the DC motor M under heavy load,
When the speed voltage from the -V converter 180 is higher than the third heavy load voltage from the voltage divider 210a, the comparator 210
e generates a high level signal and RS flip-flop 2
A low level signal is generated from 30. Further, in the timer circuit 220, the voltage divider 220b generates a first divided voltage under conduction of the transistor 224 responsive to the first determination signal from the AND gate 202 of the load area determination circuit 200, and the integrator 220a generates an integral signal in response to the high level signal from the comparator 210e, and the comparator 220C generates a high level signal based on the first divided voltage>the level of the integral signal.
A timer signal is generated from 220d.

Then, the negative AND gate 270a, in cooperation with the negative NAND gate 260 that responds to the low level signal from the RS flip-flop 230, closes the double-throw contact 52a of the relay 50 to the fixed contact 52c in the same way as described above, while the positive NOR gate 280 responds to a timer signal from timer circuit 220 to short circuit load resistor 80 via relay 70 in the same manner as described above. This results in
When the load resistor 80 is short-circuited, the DC motor M is directly short-circuited at its re-input terminal, resulting in a strong dynamic braking action. In this case, the generation time of the timer signal from the timer circuit 220 is maintained longer than when the DC motor M is under medium load, so that the effect of reducing the rotational speed of the DC motor M after reaching the rotational speed upper limit value N3L is effective. can be realized very quickly.

In addition, in the above-mentioned operation, the case where the bus is stopped on the boarding road surface with its forward direction facing the top of the boarding road surface has been described, but this is not limited to this. Substantially the same effect as described above can be achieved even when the advancing direction hits the top of the pitched road surface and is stopped.

In the above embodiment, an example was described in which the present invention was applied to a door 10 provided at a boarding/disembarking port provided on the side wall of the bus so as to be able to be opened and closed in the front/rear direction along the boarding/disembarking port. However, the present invention is not limited to this, and the present invention may be applied to a door provided at the entrance/exit located on the rear wall of the bus so that it can be opened and closed in the left and right directions along this entrance; in this case, 2. The application target is not limited to buses, but may also be applied to wagons, for example.

Further, in implementing the present invention, instead of the door 10, the present invention may be applied to a door provided on a bus or the like so that it can be folded back and forth.

[Brief explanation of the drawing]

1 and 2 are overall configuration diagrams showing one embodiment of the present invention,
3 is a detailed circuit diagram of the sample and hold circuit in FIG. 1, FIG. 4 is a detailed circuit diagram of the load area determining circuit in FIG. 1, and FIG. 5 is a detailed circuit diagram of the speed discrimination circuit in FIG. 6 is a detailed circuit diagram of the timer circuit (connected to the load area determining circuit) in FIG. 1, and FIG. 7 is a time chart for explaining the present invention in detail. Explanation of symbols B: DC power supply, M: DC motor, 10: Door, 20: Drive mechanism, 30: Operation switch, 40
c...Auxiliary detection switch, 50°60.70...Relay, 80...Load resistance, 90a, 90b, 120a
, 120b...-inverter, 100a, 100b, 1
70a, 170b...Negative AND gate, 11
0.130a, 130b, 260...Negative N
AND gate, 140a, 140b---monostable multipipe leak, 160... timer circuit, 170...
Speed sensor, 180...F-V converter, 190...
Sample hold circuit, 200...Load area determination circuit,
210...Speed discrimination circuit, 230.240...RS
Flip-flop, 280...Positive NOR gate.

Claims (1)

[Claims] It is commonly used in door opening/closing systems equipped with a rotary electric motor that opens and closes the door by rotating in one direction and closing it by rotating in the other direction.
an operating means that generates a first operating signal when opening the door and a second operating signal when closing the door; and operating means that enters a first driving state in response to the first operating signal and rotates the rotary electric motor in one direction. The rotating electric motor is supplied from the power source via the resistor to the rotary electric motor so as to allow power to be supplied from the power source via the resistor to the rotary electric motor, and to enter a second drive state in response to the second operation signal and rotate the rotary electric motor in the other direction. a driving means for allowing power to be supplied to the rotary motor; a speed detecting means for detecting the rotational speed of the rotary motor and generating a speed detection signal; and a shorting means for selectively shorting the resistor in accordance with the value of the speed detection signal. an electric control device comprising: timer signal generation means for generating a timer signal when a predetermined time has elapsed after generation of the first (or second) operation signal; and upper and lower limits of an allowable rotational speed range of the rotary electric motor. determining means for determining a value to be larger (or smaller) depending on the larger (or smaller) value of the speed detection signal in response to the timer signal and respectively generating an upper limit value signal and a lower limit value signal; and the speed detection signal. output signal generating means for generating an output signal when the value of the speed detection signal becomes larger than the value of the upper limit value signal and extinguishing the output signal when the value of the speed detection signal becomes smaller than the value of the lower limit value signal; extinguishing the first (or second) driving state of the driving means in response to the occurrence of the output signal, and returning the driving means to the first (or second) driving state in response to the disappearance of the output signal. An electric control device for a vehicle door opening/closing system, characterized in that the electric control device is provided with a control means for controlling to permit (or this return and short-circuiting of the resistor by the short-circuiting means).