JPS6128875A - Median detector for received electric field - Google Patents

Abstract

PURPOSE:To estimate a statistical median as defined, by determining the frequency distribution and cumulative frequency distribution of levels of reception in the totalization of a specified number of samples in the past accurately each time a received electric field is sampled to calculate and output the median from the results. CONSTITUTION:An A/D converter 1 converts an input L into digital level information LD0 at each pulse of a sample clock SCL to be memorized into a shift register 2 for (n) samples. All addresses of a RAM4 which memorizes the frequency distribution of level information necessary for the detection and calculation of the median are scanned with a timing generation circuit 3 or the like and a cumulative frequency pattern is generated for the integration output SUM with an integration circuit 9. In addition, the results are compared with the constant M of the cumulative frequency by a comparator 10 and the output thereof is turned to the H level when SUM>=M. Then, at the rising thereof, the output AS of an address scanning circuit 6 is memorized and held with a register 11 and a register 12 is used to produce an output LDm as median detection output of the level distribution in the current (n) samples synchronizing a clock SCL.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a device for detecting the median value of received electric field strength used for evaluating line quality in land mobile communications.

(Prior art) In land mobile communications, the field strength of received radio waves is often several tens of dB due to fading caused by the movement of the mobile station.
It is well known that it fluctuates dramatically over time. To evaluate the received electric field strength in an environment where such fading exists, it is common practice to use a statistical median value obtained from the envelope of the received wave. Conventionally, a device for detecting this statistical median value (hereinafter referred to as the median value) uses a comparator to compare the estimated value of the median value at the present time with the envelope level of the received wave detected after that. It is composed of a negative feedback type follow-up circuit that smoothes and calculates the ratio of magnitude and frequency using an integrator, detects the total amount of error from the state with a frequency of 50, and moves the estimated value in the direction of reducing the error. The majority of things. However, in a detection circuit with such a configuration, the feedback circuit including the integration has a fixed time constant, so it is not possible to accurately follow the receiving input that fluctuates rapidly, and the The drawback was that a value could not be given consistently through definitions.

Note that the following documents exist as conventional techniques.

Reference 1: Matsumoto, Adachi; Digital received electric field median detection circuit for mobile communications. 1981 IEICE General Conference Proceedings 16.2157 p 8
200 Literature 2...Kobayashi, Chunichi; Digital processing type reception level detection circuit. Proceedings of the 1981 National Conference of the Institute of Electronics and Communication Engineers "63 p"0-"°° The effective number of samples and sampling frequency are shown when sampling and statistically estimating the average power or voltage expressed in decibels from the obtained samples.

Reference 3 Adachi, Yoshida; Effective number of samples and sampling frequency in statistical estimation of average received power under Rayleigh fading. Institute of Electronics and Communication Engineers Journal '81
/6 Vow, J64 B, A 6 Tl1)
-556~557 -Reference 4...Adachi; Statistical estimation of median received voltage in Rayleigh fading. Journal of the Institute of Electronics and Communication Engineers '81/ 4 Vow,
J64B, A4pp, 336-33
．． 7 (Object of the Invention) The present invention was carried out to eliminate the drawbacks of the conventional device, and it calculates the defined statistical median value from the frequency distribution of the envelope of the received wave within a given fixed time. The purpose is to make it possible to estimate the value and also to follow fluctuations in the median value by shifting the interval from time to time.

(Configuration of the Invention) FIG. 1 is a block diagram showing an example of the configuration of a received electric field median value detection device embodying the present invention. Symbol 1 in this diagram is A
/D (Analog-to-Digital) converter, whose input is the envelope output of the received wave or the analog level information of its logarithmically compressed value. The A/D converter 1 converts the input into digital level information LDo for each pulse of a sampling clock SCL supplied from outside the device. 2 is a not register which sequentially inputs LDo at the timing of SCL and stores n samples (an appropriate value of n will be explained later). Its output LDn is level information after n samples delay. Reference numeral 3 denotes a timing generation circuit that generates various timing pulses necessary for a series of control no-fences for median value detection calculation every pulse of the sampling clock SCL. 4 is a RAM (random access memory) that stores the frequency distribution of level information necessary for median value detection calculations. 5 is an address switching circuit which switches the address A of the RAM 4. 6 is an address scanning circuit which scans all addresses in the RAM 4 in one cycle. Address switching circuit 5 receives gate switching signal G output from timing circuit 3. lGn.

G, respectively, LDo, LDn, and the address scan output AS of the address scan circuit 6 are switched and outputted as the address A of the RAM 4. The address scanning circuit 6 is activated by the gate switching signal G8 from the timing circuit 3, and also receives the address scanning clock ACL from the circuit 3.
Address scanning of RAM 4 is performed at the timing of . 7 is an increment circuit which has the function of adding +1 to the content read from RAM 4 and storing it at the original address; signal G from timing circuit 3; is activated by 8
is a decrement circuit which has the function of subtracting 1 by 1 in contrast to 7, and is activated by the signal Gn. 9 is an integration circuit,
When the address scanning circuit 6 scans all the addresses in the RAM 4, in synchronization with this, all the contents are integrated and a cumulative frequency pattern of digital values is generated in the integrated output SUM. A comparator 10 compares the absolute values of digital data. One of these inputs is SUM, and the other is a cumulative frequency constant M that gives the median value. Then, the output DET of the comparator 10 becomes H level when the condition of SUM≧M is satisfied. 11 and 12 are registers that store and output input data, and 11 is the output A of the address scanning circuit 6 when the output DET of the comparator O rises from L level to H level.
The contents of S are memorized and the memory retention output ASr
The register 12 stores and outputs n in synchronization with the sampling clock SCL of the A/D converter l. This output L
Dm is the median detection output of the level distribution of the latest n samples.

(Operation of the Invention) The operation of the apparatus having the configuration shown in FIG. 1 will be explained below with reference to FIGS. 2 and 3. However, for convenience of explanation, the number n of samples of level information and the number of level divisions used for detecting the voltage median value are both set to 11 for simplicity.

FIG. 2 is a diagram showing an example of the contents stored in the RAM 4, in which the horizontal axis represents the numerical value of the data content of each address in the address scanning circuit, and is expressed in the form of a bar graph.

The number in parentheses is the value of D. Here, the value of address A is 0~
10 (1 level) corresponds to the value division θ to lO of the level information output LDo of the A/D converter l, and A=RA
Regarding the M address-level information, the data value of each address indicates the number of times the corresponding level information was obtained. With such correspondence, the RAM 4 has a function of storing the frequency distribution for each level information value.

Each time a new LDO is obtained at the start of reception'
Using ILD as an address, the increment circuit 7 increases the data value (=frequency) of the corresponding address,
By repeating this for n (=11) samples, the level frequency distribution for the initial n samples is obtained in the RAM 4. If the frequency distribution at this point is as shown by the thick solid line in Figure 2, the set of n samples from which a new LDO is obtained in the next sample is the n samples from the new LDO to just before LDn. becomes a set of level information, and LDn is discarded from RAM4. Therefore, it is necessary to update the frequency distribution to correspond to the new n samples.

Here, for example, LDo "" 2, , LDn =
If it is 6, increase the frequency of level 2 by +1 [
It is clear that by performing (3) in FIG. 2, new samples are added and old samples are deleted, and a new frequency distribution of n samples is obtained. In FIG. 2, the change in the frequency distribution of Hoko is shown by a dashed line with diagonal lines.

Creating the initial value of the frequency distribution as described above and updating it
'A/D based on the new type and applying the example in Figure 2
Figure 3 shows a time chart of an example of an operation in which the frequency distribution is updated in response to a new set of n samples for each sample of the level information output from the converter 1, and the median value is detected from this. .

In Figure 3, the horizontal axis shows the passage of time, and the leftmost symbol S
CL-LDm indicates each signal shown in FIG. Of these, SCL to ACL and DET are the binary signals explained in FIG. 1, and the binary signals H (signal i) and L (no signal) are displayed at the right end of FIG. Still A (address), ASm (sample output of register 11),
LDm (sample output of register 12) ld: Write numerical values in the large and small rectangular parts to represent the contents,
r) (data content of R, AM4) and SUM (integrated output of integrating circuit 9) are all the same as the format shown in FIG. 2 except that the horizontal axis represents the passage of time.

Now, at the same time as a new level information sample LDo is obtained from the A/D converter 1 by one pulse of the sampling clock SCL at the top of FIG. The address A of the RAM 4 is set to LDo (=2) by the address switching circuit 5. Therefore, RAM4 is at address L.
Do (=2) is accessed, and its content (1) is added by +1 by the increment circuit 7, changing to (2). The time length of this [exist] PAH''' level Tc 4'l
The length may be the minimum length necessary to execute a set of operations of reading data from one address of the RAM 4 and adding and storing +1. Next, instead of Go, the gate switching signal Gn has the same time length T.
Only O becomes II HI+ level, address LDn (= 6) of RAM 4 is accessed, and its contents (4
) is subtracted by 1 by the decrement circuit 8 and changes to (3). The above shows the contents explained in FIG. 2 on the time axis. When the above operation, that is, creation of a new frequency distribution, is completed, the gate switching signal G8 rises to "H", and the address of the RAM 4 is scanned from 0 to 10 by the address scanning output AS of the address scanning circuit 6.

Each of these addresses is clocked by the address scan clock ACL.
Since the address information corresponds to the level information, the data (D) in RAM4 is
~Each frequency corresponding to level 10 is sequentially read out to the integration circuit and integrated at the ACL timing. Therefore, the integrated output SUM becomes a cumulative frequency distribution pattern developed on the time axis as shown in the figure. Here, the period TA of ACL is R
The length may be the minimum length necessary to execute a set of operations of reading data of one address of AM4 and integrating. Now, since the median of the frequency distribution of the number of samples n (n is an odd number) is given at the point where the cumulative distribution reaches (n+1)/2, the other constant input of the comparator 10 M f M= (
n+1)/2 = 6, comparator 1 indicates that the condition of SUM2-M is satisfied.
The value of A (or AS) at the rising point of the output DET of 0 (5 in the example of FIG. 3) is the median value. Register 11 is the third
As shown in the figure, this is stored and held at the rising point of DET, and the value of the output ASm can be updated from the previous median value (6 in the example of FIG. 2) to the new median value (5 above). This is output by the register 12 to the outside as the median detection output LDm when the next sampling clock SCL pulse arrives.

Next, we will discuss various performance issues that will arise when the device according to the present invention described above is put to practical use in detecting the median received field strength in general land mobile communication, such as the range of level information, sampling period, number of samples, etc. Examine from the viewpoint of feasibility and suitability.

It is generally accepted that fading in land mobile radio communications is so-called Rayleigh fading in which the envelope level distribution of the received signal follows a Rayleigh distribution agent. First, regarding the dynamic range (maximum change range of level) of the envelope level, when it is treated as a logarithmically compressed value (decibel; dB), it depends on the performance of the receiver, but it is approximately -30 to +80 dBμV (dBμV is 1μV).
20 times the logarithm value based on (2), that is, 110 dB. Assuming that the measurement accuracy is ±1 dB and the measurement is performed in 1 dB increments, the number of level divisions of the level information will be approximately 110. This is within the range of 0 to 255 that can be expressed as a binary number of 1 byte = 8 bits, and can be realized by using an 8-bit A/D converter.

Next, regarding the sampling period Ts (seconds) required for statistical estimation of the median value, according to the above-mentioned document 3, if it satisfies the maximum drag frequency /D (Hz) of Rayleigh fading, an effective standard deviation can be obtained. It is known that the median value with (1/Ts=f8=sampling frequency)
.

Regarding the number of samples n, it is clear that the standard deviation of the median value decreases as n increases, and according to the above-mentioned document 4, the number n of samples required to obtain a standard deviation of 1 dB is lower. The formula becomes

n≧39 ・・・・・・・・・・・・
...(2) In general, the maximum Doppler frequency f of fading
D is the radio frequency f(H2), and the speed of the moving body is V(,
m/5ec),.

If the speed of light is c = 3 x 108 (m/see), then fD - fv/c...
...(3) and used in land mobile radio
In the 0 MHz band, v = 100 km/h (3
) formula, fD≦74(Hz)...
......(4) Substituting the condition of (4) into (1), Ts≦5xio-a (seconds) ......
・It becomes (5). Therefore, the time required to obtain one median value T=nTs is given by (2) and (5): T=n-TB Gradient 0.195 (seconds) -=-...
・It becomes (6). From the above numerical examples, the time length required for each operation shown in FIG. 3 is as follows.

The time length TO of the H level of Go and Gn is the memory RAM
Assuming that the time required to read and store 4 is twice the time TA based on memory read, then as shown in Figure 3, rs≧2TG+(number of level divisions) ・TA=(4+1)
10)・TA≧114 TA ・・・・・・・・・
...(7), so from both equations (5) and (7), TA <1'8/114≦5X10-3/114≦
44 (μ8) ・・・・・・・・・・・・(8
). General RAM read and store speed is several μs
This TA is for a fully achievable speed considering that:

Further, since the number of stages of the shift register 2 shown in FIG. 1 is made equal to the number of samples n, it is sufficient that it is 39 or more according to equation (2) and can be easily realized. .

Furthermore, you will be given greater calculation speed and storage capacity. It is also possible to replace all functions with microcomputer-based software functions, and in this case, versatility such as the ability to arbitrarily set parameters such as the number of samples can be obtained.

(Effects of the Invention) In the median detection device of the present invention, each time the received electric field is sampled, the frequency distribution and cumulative frequency distribution of the received level, which is a total of a predetermined number of samples in the past, are accurately determined each time,
Since the median value is calculated and output from this, it is possible to eliminate the delay effect due to the integration time constant, that is, the interference effect between a plurality of samples, which is present in the median value detection operation in the conventional negative feedback type follow-up circuit method. In addition, since it is possible to provide a sample with the median value as defined from samples of level values of an arbitrary number of samples t in the range required for the application, it is highly compatible in evaluating the correspondence between the theoretical value and the actual value.

Furthermore, many parts of the circuit configuration can be converted into software, which has the advantage of being suitable for downsizing, high reliability, and cost reduction of devices.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing an example of the configuration of a device embodying the present invention, FIG. 2 is a diagram showing an example of the storage contents of the RAM in FIG. 1, and FIG. 3 is a diagram of the device having the configuration shown in FIG. 1. 3 is a time chart of an operation example of median value detection using the example of FIG. 2; 1...A/D converter, 2...Shift register f13.
...Timing generation circuit, 4...RAM (random access memory), 5...Address switching circuit, 6...Address scanning circuit, 7...Increment circuit, 8...
・Decrement circuit, 9... Integration circuit, 10... Comparator, 11, 12... Register, L... Analog level information, LDo, LDn... Digital level information, SCL... Sampling clock , A...R
AM address, D-RAM data content, Go,
Gn, GB - gate switching signal, ACL...address scan clock, AS...address scan output, SU
M... Cumulative output, M... Cumulative degree value that gives the median value,
DET: Comparator output, ASm: Memory retention output, LD
rrI...median detection output.

Claims (1)

[Claims] An A/D converter samples the envelope of the received wave or its logarithmically compressed value with a sampling clock having a constant sampling period, converts it into digital numerical level information, and outputs the level information for n samples (n is the number of samples required depending on the standard deviation of the desired median value), a shift register for storing the frequency distribution of the level information, a random access memory (RAM) for storing the frequency distribution of the level information, and generation of various timing pulses synchronized with the sampling clock. an address switching circuit that switches addresses in the RAM; an address scanning circuit that scans all addresses in the RAM; an increment circuit that specifies the address of the RAM through the address switching circuit and increases the level information, that is, the frequency of the new level by one; a decrement circuit that specifies the level information through the switching circuit and decreases the frequency of the old level to be discarded by one;
After the increment and decrement circuits update the frequency distribution of the level information stored in the RAM in accordance with the latest n samples, the address scanning circuit reads all addresses in the RAM corresponding to the entire level information range. An integration circuit that integrates the contents when scanning is specified in one cycle and reading out the contents one after another, and whether the cumulative frequency distribution that is the cumulative output is equal to the cumulative frequency that gives the median value determined by the number of samples n. A comparator that detects the first point in time when the output increases, a storage circuit such as a register that stores the address value at the time of detection of the output, that is, a level information value, and a median value is detected by synchronizing the stored contents with the next sampling clock pulse. What is claimed is: 1. A received electric field median value detection device comprising: a circuit that holds and outputs the received electric field as an output;