JPS61288679A - Video scrambling method - Google Patents

Abstract

PURPOSE:To eliminate the deterioration of the picture at the time of reproduction by separating with optional points in the line of the video signal, replacing them, adding the data to show the position of the separating point to the horizontal blanking division and obtaining the video scrambling signal. CONSTITUTION:The output of a synchronizing separator circuit 307 is inputted to a gate pulse generating circuit 311, outputted as the gate pulse for the overlapping data and inputted to a scrambling controller 309 as the starting pulse of the line. The output of an A/D converting device 303 is stored in a memory 304. The scrambling controller 309 adds data A to show the separating point in the line and executes the addressing of the memory 304. An output B of the scrambling controller 309 is the data to show the separating point in the line, the prescribed scrambling is executed by a data scrambling 310, the output is overlapped to the horizontal blanking division of the line by an overlapping circuit 306 and outputted from an output terminal 312.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of scrambling video in systems such as CATV.

2. Description of the Related Art Conventionally, video scrambling methods have been proposed or implemented, such as a method of transforming the synchronization signal portion of a video signal, a method of changing the polarity of a video signal, a method of superimposing an interference wave, and the like.

Problems to be Solved by the Invention In such conventional methods, it is easy to understand the video souffle 2-page pull method by observing the video signal with an oscilloscope, etc., and the received signal is affected by distortion in the transmission path. There were problems such as deterioration of the screen and the inability to play.

The present invention has been made in view of the above, and an object of the present invention is to provide a video scrambling method in which the scrambling method cannot be easily decoded and the reproduced image quality does not deteriorate.

Means for Solving the Problems In order to solve the above problems, the present invention divides the video signal line at arbitrary points, replaces them, and indicates the position of the above break points in the horizontal retrace interval. The present invention provides a video scrambling method characterized by adding data and obtaining a video scramble signal.

Effect of the Invention The present invention uses the method described above to divide a line of video signals at arbitrary points, replace them, and transmit them, so that the scanning start position appears to be different for each line, so that information on the original image is lost. is completely lost, and the correlation between the line and the three penoins before and after it disappears, causing it to appear flickering. Furthermore, if the positions of the break points are limited to a few, the images will overlap each other, making it impossible to recognize the original image. Furthermore, in order to reproduce this scrambled signal, a third party must decode the descrambling data added to the horizontal retrace section and find the position of the break point of the corresponding line. It's impossible.

Embodiment FIG. 3 is a block diagram showing an embodiment of video scrambling in the video scrambling method of the present invention, and FIG.
) is the waveform diagram of the original video signal, and FIG.
), divide the video signal line at any point,
These are replaced, and data indicating the position of the break point is added to the horizontal flyback section and output. Input terminal 3
The video signal input to 01 is supplied to an A/D converter 303 and a synchronous separation circuit 307. Synchronous separation circuit 307
The output is input by the gate pulse generation circuit 311 as a gate pulse for superimposed data and to the scramble controller 309, and is input as a line start pulse. The video signal input to the A/D converter 303 is converted into a digital signal and stored in the memory 304. The scramble controller 309 sends data indicating the position of the break point in the line to the address decoder 308.
In addition, addressing of the memory 304 is performed.

The address decoder 308 sequentially addresses the memory 304 at a timing different from the above-mentioned storage.
The output data of this memory 304 is sent to the D/A converter 305.
is supplied to and converted into an analog signal. The output B of the scramble controller 309 is data indicating the position of a break point in a line, which is scrambled in a predetermined manner by a data scrambler 310, superimposed on the horizontal retrace section of the corresponding line by a superimposition circuit 306, and output from an output terminal 312. be done. This output waveform diagram is shown in Fig. 4, and except for the fact that data is superimposed on the horizontal retrace interval, it is no different from a normal video 5 Beno image signal, and even if a third party observes this waveform, Scrambling methods are difficult to discover. Also, the data superimposed on the horizontal retrace section indicates the position of the break point in the line, but it is difficult to decipher it because it is necessary to discover the data format and it is scrambled. It is.

FIG. 5 is a block diagram showing an embodiment of the video descrambler of the present invention, which receives the output of the video scrambler and reproduces the original video signal. Input terminal 4
A video scramble signal is input to A/D converter 4.
02 synchronization separation circuit 405 and scramble data extraction circuit 407. The A/D converter 402 converts the video scramble signal into a digital signal, and the memory 403 is addressed by address decoder 08.
Write to. The scramble data extraction circuit 407 applies the synchronization signal output from the synchronization separation circuit 40 to the gate pulse generation circuit 406 to generate a gate pulse 6 base/base for data superimposed on the horizontal retrace interval, 2 data is extracted from the video scramble signal using the gate pulse, and the data descrambler 41
Add to 0. The data descrambler 410 performs a predetermined descrambling process on the data, and normal data is input to the descramble controller 409.

The descrambling controller 409 receives the synchronization separation output as a line start pulse, recognizes the position of the line break point in the corresponding line based on the data, controls the address decoder, and stores the memory 403. address. Further, the address decoder sequentially addresses the memory at a timing different from the write, and the output of this memory is D.
/A converter 404 and converted into an analog signal,
It is output from the output terminal 411 as a normal video signal.

Note that Fig. 2(a) shows the original image, Fig. 2(b)
2 is a diagram showing a scrambled image when the position of the break point is not limited, and FIG. 2(C) is a diagram showing a scrambled image when the position of the break point is limited to two.

Effects of the Invention As described above, according to the present invention, the scrambled image appears to have different lines and different scanning start positions, and the information of the original image is completely lost or the breakpoints are different. If the positions are limited to a few points, the image overlaps with the discharge and the original image becomes unrecognizable, resulting in a high video scrambling effect and making it difficult for third parties to decipher the video scrambling method and reproduce the original image. Furthermore, since the amplitude of the synchronization signal and video signal is not manipulated, there is no deterioration in image quality during playback, making it extremely useful in practice.

Figure 2 (8-) is a front view showing the original image;
Figure 2 (bl is a front view showing a scrambled image when the position of the break point is not limited; Figure 2 (C,) is a front view showing a scrambled image when the position of the break point is limited to two; FIG. 3 is a block diagram showing an embodiment of a scrambler embodying the above video scrambling method, FIG. 4 is a waveform diagram showing a video scramble output in the same video scrambling method, and FIG. 5 is an embodiment of the same video scrambling method. FIG. 2 is a block diagram showing an example of a descrambler that performs the following steps.

301...Input terminal, 303...A/D
Converter, 304...Memory, 306...D
/A converter, 306... superimposition circuit, 30a... synchronization separation circuit, 308... address decoder, 309... scramble controller, 31o...・Data scrambler, 311...
... Gate pulse generation circuit, 312 ... Output terminal, 401 ... River input terminal, 402 ... A/D converter, 403 ... Memory, 404 ... 1)
/A converter, 405...Synchronization separation circuit, 406
......Cate pulse generation circuit, 407...mark/scramble data extraction circuit, 408...address decoder, 409...descramble controller, 410...data descrambler , 41
1...°°output terminal.

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Claims (1)

[Claims] A video scrambling method characterized by dividing a line of a video signal at an arbitrary point, exchanging them, and adding data indicating the position of the dividing point to a horizontal retrace section.